ETC MTV048

MTV048
(Rev 0.9)
MYSON
TECHNOLOGY
On-Screen-Display Controller
for CRT/LCD Monitor
FEATURES
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Software control for CRT/LCD applications.
Full screen self-test pattern generator with programmable pattern color.
On-chip PLL circuitry (CRT) or external pixel clock input (LCD) up to 150 MHz.
Horizontal SYNC input up to 150 KHz.
Programmable horizontal resolutions up to 1524 dots per display line.
Full screen display consists of 15 (rows) by 30 (columns).
12x16 or 12x18 dot matrix selection.
A total of 384 fonts including 360 standard fonts, 16 multi-color fonts and 8 user fonts.
8 color selections for character foreground, background and window color.
Character button boxes with programmable box length.
Character bordering, shadowing and blinking effect for display.
Full-screen character double width control.
Double character height and/or width control per row.
Programmable positioning for display screen center.
Row to row spacing control per row to avoid expansion distortion.
4 programmable background windows with multi-level operation and programmable shadow width/height/color.
Software clear bit for full-screen erasing.
Programmable adaptive approach to handle H, V sync collision automatically by hardware.
Fade-in/fade-out or blend-in/blend-out effects.
Compatible with SPI bus or I2C interface with address 7AH (slave address is mask option).
5V or 3.3V power supply.
16-pin PDIP/SOP package.
GENERAL DESCRIPTION
MTV048 is designed for monitor applications to display built-in fonts onto monitor screens. The display operation
occurs by transferring data and controls information from the micro controller to RAM through a serial data
interface. It can execute a full-screen display automatically, as well as specific functions such as character
background, bordering, shadowing, blinking, double height and width, font-by-font color control, button boxes,
frame positioning, frame size control by character height and row-to-row spacing, horizontal display resolution, fullscreen erasing, fade-in/fade-out effect, windowing effect, shadowing on window and full-screen self-test pattern
generator.
MTV048 provides 384 fonts including 360 standard fonts, 16 multi-color fonts and 8 user fonts and 2 font sizes,
12x16 or 12x18 for more efficacious applications. The full OSD menu is formed by 15 rows x 30 columns, which
can be positioned anywhere on the monitor screen by changing vertical or horizontal delay.
BLOCK DIAGRAM
SSB
SCK
SDA
VFLB
HFLB
VCO
RP
9 RAMADDR
SERIAL DATA
INTERFACE
VERTICAL
DISPLAY CONTROL
HORIZONTAL
DISPLAY CONTROL
PHASE LOCK LOOP
R/WEN
8 DATA
DISPLAY & ROW
CONTROL
REGISTERS
(RAM)
9 ROMADDR
SHADOW
LUMA
ROW
COLUMN
WINDOWS & FRAME
CONTROL
WINDOW
FONTS ROM &
USER FONTS RAM
LUMINANCE & BORDER
GENERATOR
COLOR ENCODER
ROUT
GOUT
BOUT
FBKG
INT
VCLK
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Rev 0.9
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MTV048
(Rev 0.9)
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
1
16
VSS
2
15
ROUT
RP/NC
3
14
GOUT
VDDA
4
13
BOUT
HFLB
5
12
FBKG
MTV048N-xx
VSSA
VCO/XIN
SSB
6
11
V33CAP
SDA
7
10
VFLB
SCK
8
9
VDD
2.0 PIN DESCRIPTIONS
Name
I/O
Pin NO.
Descriptions
VSS
-
1
VCO / XIN
I/O
2
RP / NC
I/O
3
VDDA
-
4
HFLB
I
5
SSB
I
6
SDA
I
7
SCK
I
8
VDD
-
9
VFLB
I
10
Analog ground. This ground pin is used for internal analog circuitry.
Voltage control oscillator (bit LCD = 0). This pin is used to control
the internal oscillator frequency by DC voltage input from external
low pass filter.
Pixel clock input (bit LCD = 1). This is a clock input pin. MTV048
can be driven by an external pixel clock source for all the logic
inside. The frequency of XIN must be the integral time of pin HFLB.
Bias Resistor (bit LCD = 0). The bias resistor is used to regulate
the appropriate bias current for internal oscillator to resonate at
specific dot frequency.
No connection (bit LCD = 1).
Analog power supply. Positive 5V / 3.3V DC supply for internal
analog circuitry. And a 0.1uF decoupling capacitor should be
connected across to VDDA and VSSA.
Horizontal input. This pin is used to input the horizontal
synchronizing signal. It is a leading edge triggered and has an
internal pull-up resistor.
Serial interface enable. It is used to enable the serial data and is
also used to select the operation of I2C or SPI bus. If this pin is left
floating, I2C bus would be enabled. Otherwise the SPI bus is
enabled.
Serial data input. The external data transfer through this pin to
internal display registers and control registers. It has an internal pullup resistor.
Serial clock input. The clock-input pin is used to synchronize the
data transfer. It has an internal pull-up resistor.
Digital power supply. Positive 5V / 3.3V DC supply for internal
digital circuitry and a 0.1uF decoupling capacitor should be
connected across to VDD and VSS.
Vertical input. This pin is used to input the vertical synchronizing
signal. It is leading triggered and has an internal pull-up resistor.
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(Rev 0.9)
MYSON
TECHNOLOGY
V33CAP
I/O
11
FBKG
O
12
BOUT
O
13
GOUT
O
14
ROUT
O
15
VSS
-
16
3.3V Regulator Capacitor connection. Connect a decoupling
capacitor to VSS pin when DC supply = 5V, or connect to 3.3V
directly when DC supply = 3.3V.
Fast Blanking output. It is used to cut off external R, G, B signals
of VGA while this chip is displaying characters or windows.
Blue color output. It is a blue color video signal output. And it is a
DAC output if bit LCD = 0 or CMOS output if bit LCD =1.
Green color output. It is a green color video signal output. And it is
a DAC output if bit LCD = 0 or CMOS output if bit LCD =1.
Red color output. It is a red color video signal output. And it is a
DAC output if bit LCD = 0 or CMOS output if bit LCD =1.
Digital ground. This ground pin is used for internal digital circuitry.
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interface
The serial data interface receives data transmitted from an external controller. There are 2 types of buses,
which can be accessed through the serial data interface. One is SPI bus and the other is I2C bus.
3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should start pulling SSB to "low" level, enabling MTV048 to receiving mode, and retain at "low" level
till the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
SSB
SCK
SDA
MSB
LSB
First byte
Last byte
FIGURE 1. Data Transmission Protocol (SPI)
There are three transmission formats, shown as below:
Format (a) R - C - D → R - C - D → R - C - D … ..
Format (b) R - C - D → C - D → C - D → C - D … ..
Format (c) R - C - D → D → D → D → D → D … ..
Where R=Row address, C=Column address, D=Display data
3.1.2 I2C bus
I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should start writing
the slave address 7AH to MTV048. The protocol is shown in Figure 2.
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MTV048
(Rev 0.9)
MYSON
TECHNOLOGY
SCK
SDA
B7
START
B6
first byte
B0
B7
B0
ACK
ACK
second byte
STOP
last byte
FIGURE 2. Data Transmission Protocol (I2C)
There are three transmission formats for I2C write mode, shown as below:
Format (a) S - R - C - D → R - C - D → R - C - D … ..
Format (b) S - R - C - D → C - D → C - D → C - D … ..
Format (c) S - R - C - D → D → D → D → D → D … ..
Where S=Slave address, R=Row address, C=Column address, D=Display data
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data, which will be allocated with a
different row address and column address. Format (b) is recommended for updating data that has the same
row address but a different column address. Massive data updating or full screen data change should use
format (c) to increase transmission efficiency. The row and column address will be incremented
automatically when the format (c) is applied. Furthermore, the undefined locations in display or user fonts
RAM should be filled with dummy data.
TABLE 1. The Configuration of Transmission Formats
Address
b7
b6
b5
b4
Row
1
0
0
R4
Address Bytes Columnab
D8
0
0
C4
of Display Reg. Column
D8
0
1
C4
c
Data
D7
D6
D5
D4
Row
1
0
1
R4
Attribute Bytes Columnab
0
0
x
C4
of Display Reg. Column
0
1
x
C4
c
Data
D7
D6
D5
D4
Row
1
1
0
0
C5
C4
Column
ab
User Fonts
0
1
C5
C4
Columnc
Data
D7
D6
D5
D4
b3
R3
C3
C3
D3
R3
C3
C3
D3
C3
C3
D3
b2
R2
C2
C2
D2
R2
C2
C2
D2
R2
C2
C2
D2
b1
R1
C1
C1
D1
R1
C1
C1
D1
R1
C1
C1
D1
b0
R0
C0
C0
D0
R0
C0
C0
D0
R0
C0
C0
D0
Format
a,b,c
a,b
c
a,b,c
a,b,c
a,b
c
a,b,c
a,b,c
a,b
c
a,b,c
There are 3 types of data, which should be accessed through the serial data interface. One is ADDRESS
bytes of display registers, another is ATTRIBUTE bytes of display registers, and the other is user fonts
RAM data. The protocols are all the same except the bit6 and bit5 of row address and the bit5 of column
address. The MSB (b7) is used to distinguish row and column addresses when transferring data from
external controller. The bit6 of row address is used to distinguish display registers and user fonts RAM data
and the bit6 of column address is used to differentiate the column address for format (a), (b) and format (c)
respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte when it is set to
"0" and ATTRIBUTE byte when it is set to "1". And at address bytes, bit5 of column address is the MSB
(bit8) and data bytes are the 8 LSB (bit7~bit0) of display fonts address to save half MCU memory for
true 392 fonts display. So each one of the 384 fonts can be displayed at the same time. See Table 1. And for
format (c), since D8 is filled while program column address of address bytes, the continued data will be the
same bank of upper 128 fonts or lower 256 fonts until program column address is of address bytes again.
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(Rev 0.9)
MYSON
TECHNOLOGY
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to
format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3 .
FIGURE 3. Transmission State Diagram
3.2 Address Bus Administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when
external write using format (c).
3.3 Vertical Display Control
The vertical display control can generate different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit (CHS),
vertical display height control register (CH6-CH0). The algorithms of repeating character line display are
shown as Table 2 and Table 3. The range of programmable vertical size is 270 lines to 2130 lines maximum.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB
is calculated by using the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = one horizontal line display time
TABLE 2. Repeat Line Weight of Character
CH6 – CH0
Repeat Line Weight
CH6, CH5 = 11
+18*3
CH6, CH5 = 10
+18*2
CH6, CH5 = 0x
+18
CH4 = 1
+16
CH3 = 1
+8
CH2 = 1
+4
CH1 = 1
+2
CH0 = 1
+1
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TECHNOLOGY
MTV048
(Rev 0.9)
TABLE 3. Repeat Line Number of Character
Repeat Line
Repeat Line #
Weight
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
+1
v
+2
v
v
+4
v
v
v
v
+8
v
v
v
v
v
v
v
v
+16
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
+17
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
+18
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Note: “v” means the nth line in the character would be repeated once, while “-“ means the nth line in the
character would not be repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and
HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is
calculated by using the following equation:
For CRT:
Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width
Where P = One pixel display time = One horizontal line display time / (HORR*12)
For LCD:
Horizontal delay time = ( HORD * 6 + 49) * P
Where P = One XIN pixel display time
3.5 Phase lock loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution register (HORR). The frequency of VCLK is determined by the following equation:
VCLK Freq. = HFLB Freq. * HORR * 12
The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB
input is not present to MTV048, the PLL will generate a specific system clock, approximately 2.5MHz, by a
built-in oscillator to ensure data integrity.
3.6 Display & Row Control Registers
The internal RAM contains display and row control registers. The display registers have 450 locations, which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register
has its corresponding character address on ADDRESS byte, its corresponding background color, 1 blink bit
and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for
row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen,
only even column characters could be displayed on screen and the odd column characters will be hidden.
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MYSON
TECHNOLOGY
Column #
Row #
0 1
28 29
30
0
1
Character ADDRESS Bytes
of Display Registers
ROW
CTRL REG
13
14
31
R
E
S
E
R
V
E
D
FIGURE 4. ADDRESS Bytes of Display Registers Memory Map
Column #
Row #
0 1
28 29
30
31
0
1
Character ATTRIBUTE Bytes
of Display Registers
RESERVED
13
14
Column #
Row 15
0
11
12
WINDOW1 ~ WINDOW4
Row 16
22
FRAME CTRL REG.
23
31
RESERVED
Column #
0
1 2
4 5
31
WINDOW SHADOW COLOR
FRAME CTRL REG.
RESERVED
FIGURE 5. ATTRIBUTE Bytes of Display Registers Memory Map
ADDRESS Bytes:
Address registers, (ROW 0 ~ 14, COLUMN 0 ~ 29),
B8
B7
B6
B5
B4
B3
CRADDR
MSB
B2
B1
B0
LSB
CRADDR - Define OSD character address from address 0 to 383.
= 0 ~ 359 ⇒ 360 standard ROM fonts.
= 360 ~ 367 ⇒ 8 user fonts.
= 368 ~ 383 ⇒ 16 multi-color ROM fonts.
Row control registers (ROW 0 ~ 14, COLUMN 30),
B7
B6
B5
B4
B3
B2
BOX
-
B1
CHS
B0
CWS
BOX - Select BGR, BGG, BGB or BOX2, BOX1, BOX0 of attributes bytes to the respective row.
= 0 ⇒ Background color bits BGR, BGG, BGB are selected.
= 1 ⇒ Button boxes bits BOX2, BOX1, BOX0 are selected.
CHS - Define double height character to the respective row.
CWS - Define double width character to the respective row. If double width character is chosen, only even
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TECHNOLOGY
column characters could be displayed on screen and the odd column characters will be hidden.
ATTRIBUTE Bytes:
Attribute registers, (ROW 0 ~ 14, COLUMN 0 ~ 29),
B7
B6
B5
B4
B3
BGR/BOX2 BGG/BOX1 BGB/BOX0 BLINK
B2
R
B1
G
B0
B
BGR, BGG, BGB : These three bits define the background color for their individual relative address
characters. If these three bits are set to (0, 0, 0), no background will be shown
(transparent). Therefore, a total of 7 background colors can be selected.
BOX2-0 - Select the character button boxes format of its relative address character.
= 0, 0, 0 ⇒ Button boxes is disabled.
= 1, 0, 0 ⇒ Start of depressed button box which is more than 1 character button box.
= 1, 0, 1 ⇒ Start of depressed button box which is only 1 character button box.
= 1, 1, 0 ⇒ Start of raised button box which is more than 1 character button box.
= 1, 1, 1 ⇒ Start of raised button box which is only 1 character button box.
= 0, 1, 0 ⇒ Middle of button box.
= 0, 0, 1 ⇒ End of button box.
BLINK = 1 ⇒ Enable blink effect for its relative address character. And the blinking is alternate per 32
vertical frames.
= 0 ⇒ Disable blink effect for its relative address character.
R, G, B - These three bits are used to specify their individual relative address character foreground color.
3.7 Character Button Boxes Generator
There are 4 character button box generators to generate 4 different types of button boxes including
depressed button box with only 1 character, depressed button box with more than 1 character, raised button
box with only 1 character, and raised button box with more than 1 character. The button boxes format is
defined by (BOX2, BOX1, BOX0) bits of attribute bytes. And these bits are described as below:
1). (1, x, x) means the start of character button box, and than BOX1-0 bits define the format of button box.
2). (0, 1, 0) means the middle of character button box.
3). (0, 0, 1) means the end of character button box.
The length of button box is also software control by (BOX2, BOX1, BOX0) bits. For example, if there is 1
raised button box whose length is equal to 6 characters, these BOX2-0 bits will be (1, 1, 0), (0, 1, 0), (0, 1, 0),
(0, 1, 0), (0, 1, 0), (0, 0, 1). And if there is 1 depressed button box whose length is equal to 4 characters,
these BOX2-0 bits will be (1, 0, 0), (0, 1, 0), (0, 1, 0), (0, 0, 1). That is, (0, 1, 0) command's number defines
the button box length. And only 1 byte, the attribute byte of button box start character, should be modified
when changing button box type from raised button to depressed button, or vice versa. This is very easy and
useful for software programming.
3.8 Character ROM
MTV048 character ROM contains 384 characters and symbols including 360 standard fonts, 8 user fonts and
16 multi-color fonts. The 360 standard fonts are located from address 0 to 359. The 8 user fonts are located
from address 360 to 367.And the 16 multi-color fonts are located from address 368 to 383. Each character
and symbol consists of 12x18 dots matrix.
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TECHNOLOGY
B2~B0 = 1, 1, 1
1, 1, 0
0, 0, 1
1, 1, 0
0, 1, 0
0, 1, 0
0, 0, 1
Raised Button Boxes
BOX2-0 = 1, 0, 1
1, 0, 0
0, 0, 1
1, 0, 0
0, 1, 0
0, 1, 0
0, 0, 1
Depressed Button Boxes
FIGURE 6. Character Button Boxes
3.9 Multi-Color Font
The color fonts comprise three different R, G, B fonts. When the code of color font is accessed, the separate
R/G/B dot pattern is output to corresponding R/G/B outputs. See Figure 7 for the sample displayed color font.
Note: No black color can defined in color font, black window underline the color font can make the dots
become black in color.
B
G
R
Magenta
Green
Blue
Cyan
FIGURE 7. Example of Multi-color Font
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TABLE 4. The Multi-color Font Color Selection
R
G
Background Color
0
0
Blue
0
0
Green
0
1
Cyan
0
1
Red
1
0
Magenta
1
0
Yellow
1
1
White
1
1
B
0
1
0
1
0
1
0
1
3.10 User fonts RAM
The user fonts RAM have 288 locations, which are allocated between (row 0, column 0) to (row 7, column 35)
to specify 8 user programmable fonts, as shown in Figure 6. Each user programmable font consists of 12x18
dot matrix which data are stored in 36 bytes registers. And each line of dot matrix consists of 2 bytes data,
which include 4 dummy bits as shown in figure 7 and figure 8. For example, font 0 is stored in row 0 from
column 0 to column 35 and font 1 is stored in row 1 from column 0 to column 35, etc.
ROW #
0
COLUMN #
34 35
1
36
63
0
1
USER FONTS RAM
RESERVED
6
7
FIGURE 6. User Fonts RAM Memory Map
Nth byte
(N+1)th byte
leftmost dot of font
b7
b6
b5
b4
rightmost dot of font
b3
b2
b1
b0
b7
b6
b5
b4
b3
12 bits for one row data of font dot matrix
b2
b1
b0
Dummy bits
Where N=even number
FIGURE 7. Data Format of User Font Dot Matrix
Column#
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Data
00H
00H
3FH
3FH
31H
30H
30H
31H
3FH
3FH
30H
30H
30H
30H
30H
30H
00H
00H
Column#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
Data
00H
00H
00H
80H
C0H
C0H
C0H
C0H
80H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FIGURE 8. Example of User Font Programming
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TECHNOLOGY
3.11 Luminance & Border Generator
There are 3 shift registers included in the design which can shift out of luminance and border dots to color
encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character
will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with
blackedge for right and bottom sides only.
3.12 Window and Frame Control
The display frame position is completely controlled by the contents of VERTD and HORD. The window size
and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure 5.
Window 1 has the highest priority, and window 4 is the least, when two windows are overlapping. More
detailed information is described as follows:
1. Window control registers,
ROW 15
b7
b6
b5
Column
ROW START ADDR
0,3,6 or 9
MSB
Column
1,4,7 or 10
Column
2,5,8 or 11
b7
b4
b3
LSB
MSB
b6
b5
b4
COLUMN START ADDR
b3
MSB
b7
b2
b1
ROW END ADDR
b0
LSB
b2
WEN
b1
-
b0
WSHD
b2
R
b1
G
b0
B
LSB
b6
b5
b4
COLUMN END ADDR
b3
MSB
LSB
START(END) ADDR - These addresses are used to specify the window size. It should be noted that when
the start address is greater than the end address, the window would be disabled.
WEN - Enable the relative background window display.
WSHD - Enable shadowing on the relative window.
R, G, B - Specify the color of the relative background window.
2. Frame control registers,
ROW 15
b7
b6
Column 12
MSB
b5
b4
b3
VERTD
b2
b1
b0
LSB
VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each
step is 4 Horizontal display lines. The initial value is 4 after power up.
b7
Column 13
b6
b5
b4
b3
b2
b1
b0
HORD
MSB
LSB
HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each
step is 6 dots. The initial value is 15 after power up.
Rev 0.9
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(Rev 0.9)
MYSON
TECHNOLOGY
Column 14
b7
-
b6
CH6
b5
CH5
b4
CH4
b3
CH3
b2
CH2
b1
CH1
b0
CH0
CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The
character vertical height is at least 18 lines if the content of CH6-CH0 is less than 18. For
example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines.
And if the content of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17.
See Table 2 and Table 3 for detail description of this operation.
Column 15
b7
-
b6
b5
b4
b3
HORR
b2
b1
MSB
(This byte is used only for CRT monitor application.)
b0
LSB
HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is,
the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater
than or equal to 36 and smaller than 150M / (Hfreq*12). The initial value is 40 after power up.
Column 16
b7
-
b6
-
b5
-
b4
b3
b2
RSPACE
b1
MSB
b0
LSB
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
Column 17
b7
b6
b5
OSDEN BSEN SHADOW
b4
FBEN
b3
b2
b1
b0
BLEND WINCLR RAMCLR FBKGC
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Activate the shadowing effect if this bit is set, otherwise the bordering is chosen.
FBEN - Enable the fade-in/fade-out or blend-in/blend-out effect when OSD is turned on from off state or vice
versa.
BLEND - Fade-in/fade-out or blend-in/blend-out effect select bit. Activate the blend-in/blend-out effect if this
bit is set, otherwise the fade-in/fade-out function is chosen. This function roughly takes about 0.5
second to fully display the whole menu or to disappear completely.
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
power up.
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is
set to "1". The initial value is 0 after power up.
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during
the displaying of characters or windows, otherwise, it outputs high only during the displaying of
character.
Column 18
Rev 0.9
b7
TRIC
b6
FSS
b5
-
b4
SELVCL/DWE
- 12 -
b3
HSP
b2
VSP
b1
VCO1/-
b0
VCO0/2001/03/15
MTV048
(Rev 0.9)
MYSON
TECHNOLOGY
(SELVCL, VCO1, VCO0 bits are used for CRT monitor applications only.)
(DWE bit is used only for LCD monitor applications.)
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That
is, while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins
are in high impedance state. The initial value is 0 after power up.
FSS - Font size selection.
= 1 ⇒ 12x18 font size is selected.
= 0 ⇒ 12x16 font size is selected.
Fonts designed to be 12x18 display
12x16 display if FSS=0; first and last lines omitted
FIGURE 8. 12x18 and 12x16 Fonts
SELVCL - Enable auto detection for horizontal and vertical syncs input edge distortion to avoid unstable
Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after
power up.
HSP - = 1 ⇒ Accept positive polarity Hsync input.
= 0 ⇒ Accept negative polarity Hsync input.
VSP - = 1 ⇒ Accept positive polarity Vsync input.
= 0 ⇒ Accept negative polarity Vsync input.
VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input
and horizontal resolution register (HORR). And there are different curve partitions based on
different application resister value on pin 3 (pin RP) as below:
(i) 5.6K ohm:
= (0, 0) ⇒ 6MHz < Pixel rate < 24MHz
= (0, 1) ⇒ 24MHz < Pixel rate < 48MHz
= (1, 0) ⇒ 48MHz < Pixel rate < 96MHz
= (1, 1) ⇒ 96MHz < Pixel rate < 128MHz
(ii) 3.3K ohm:
= (0, 0) ⇒ 6MHz < Pixel rate < 28MHz
= (0, 1) ⇒ 28MHz < Pixel rate < 56MHz
= (1, 0) ⇒ 56MHz < Pixel rate < 112MHz
= (1, 1) ⇒ 112MHz < Pixel rate < 150MHz
Where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12
The initial value is (0, 0) after power up.
Notes:
1. That is, if HORR is specified and RP resister = 3.3K ohm, then (VCO1, VCO0)
= (0, 0), if 6000/(HORR * 12) < HFLB Freq (KHz) < 28000/(HORR * 12)
= (0, 1), if 28000/(HORR * 12) < HFLB Freq (KHZ) < 56000/(HORR * 12)
= (1, 0), if 56000/(HORR * 12) < HFLB Freq (KHZ) < 112000/(HORR * 12)
= (1, 1), if 112000/(HORR * 12) < HFLB Freq (KHZ) < 150000/(HORR * 12)
2. It is necessary to wait for the PLL to become stable while (i) the HORR register is changed; (ii) the (VCO1, VCO0)
bits is changed; (iii) the horizontal signal (HFLB) is changed.
3. When PLL is unstable, do not write data in any address except Column 15,17,18 of Row 15. If data is written in
any other address, a malfunction may occur.
Rev 0.9
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(Rev 0.9)
MYSON
TECHNOLOGY
Column 19
b7
-
b6
-
b5
-
b4
-
b3
-
b2
CSR
b1
CSG
b0
CSB
CSR, CSG, CSB - Define the color of bordering or shadowing on characters. The initial value is (0, 0, 0) after
power up.
Column 20
b7
FSW
b6
-
b5
-
b4
-
b3
-
b2
FSR
b1
FSG
b0
FSB
FSW - Enable full screen self-test pattern and force the FBKG pin output to high to disable video RGB while
this bit is set to "1". The self-test pattern's color is determined by (FSR, FSG, FSB) bits.
FSR, FSG, FSB - Define the color of full screen self-test pattern.
Column 21
b7
WW41
b6
WW40
b5
WW31
b4
WW30
b3
WW21
b2
WW20
b1
WW11
b0
WW10
WW41, WW40 - Determine the shadow width of window 4 when WSHD bit of window 4 is enabled.
Please refer to the table below for more details.
(WW41, WW40)
Shadow Width (unit in Pixel)
(0, 0)
2
(0, 1)
4
(1, 0)
6
(1, 1)
8
WW31, WW30 - Determine the shadow width of window 3 when WSHD bit of window 3 is enabled.
WW21, WW20 - Determine the shadow width of window 2 when WSHD bit of window 2 is enabled.
WW11, WW10 - Determine the shadow width of window 1 when WSHD bit of window 1 is enabled.
Column 22
b7
WH41
b6
WH40
b5
WH31
b4
WH30
b3
WH21
b2
WH20
b1
WH11
b0
WH10
WH41, WH40 - Determine the shadow height of window 4 when WSHD bit of window 4 is enabled.
Please refer to the table below for more details.
(WH41, WH40)
Shadow Height (unit in Line)
(0, 0)
2
(0, 1)
4
(1, 0)
6
(1, 1)
8
WH31, WH30 - Determine the shadow height of window 3 when WSHD bit of window 3 is enabled.
WH21, WH20 - Determine the shadow height of window 2 when WSHD bit of window 2 is enabled.
WH11, WH10 - Determine the shadow height of window 1 when WSHD bit of window 1 is enabled.
M Pixels
N Horizontal lines
N Horizontal lines
Bordering
Shadowing
Note:
M and N are defined
by the registers of
WINSW and WINSH.
M Pixels
FIGURE 9. Character Bordering and Shadowing and Shadowing on Window
Rev 0.9
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2001/03/15
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(Rev 0.9)
MYSON
TECHNOLOGY
3.13 Color Encoder
The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border
blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
Column 23 ~ column 31 : Reserved.
Note : The register located at column 31 of row 15 is reserved for the testing. Do not program this
byte anytime in normal operation.
ROW 16
Column 0
b7
-
b6
R1
b5
G1
b4
B1
b3
-
b2
R2
b1
G2
b0
B2
R1, G1, B1 - Define the shadow color of window 1. The initial value is (0, 0, 0) after power up.
R2, G2, B2 - Define the shadow color of window 2. The initial value is (0, 0, 0) after power up.
Column 1
b7
-
b6
R3
b5
G3
b4
B3
b3
-
b2
R4
b1
G4
b0
B4
R3, G3, B3 - Define the shadow color of window 3. The initial value is (0, 0, 0) after power up.
R4, G4, B4 - Define the shadow color of window 4. The initial value is (0, 0, 0) after power up.
b7
b6
b5
b4
(This byte is used only for LCD monitor application.)
Column 2
b3
-
b2
D2
b1
D1
b0
D0
D3-D0 - These 4 bits define the propagation delay of Rout, Gout, Bout, FBKG and INT outputs to pin XIN
input falling edge control registers. Please refer to Figure 12 and Table 8.
XIN
Internal CLK
OSD output
tPD
tPD
HFLB
tSETUP
tHOLD
FIGURE 12. Output and HFLB Timing to Pixel Clock
Rev 0.9
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(Rev 0.9)
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TECHNOLOGY
TABLE 7. Output Timing to Pixel Clock
Symbol
(D2, D1, D0)
Min.
0
1
2
3
tpd
4
5
6
7
-
Typ.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max.
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Column 3 : Reserved.
Column 4
b7
LCD
b6
-
b5
ID5
b4
ID4
b3
ID3
b2
ID2
b1
ID1
b0
ID0
LCD - OSD application selection.
= 1 ⇒ LCD monitor application selected. The 2nd and 3rd pins are XIN, NC.
= 0 ⇒ CRT monitor application selected. The 2nd and 3rd pins are VCO, RP.
After this bit is changed, the whole chip circuit will be reset to default value except this byte. So this bit
also can work as software reset bit. The initial value is 0 after power up.
ID5-ID0 - LCD bit identify bits. LCD bit can be updated to "1" only when ID5-ID0 = (0, 1, 0, 1, 0, 1). And LCD
bit can be updated to "0" only when ID5-ID0 = (1, 0, 1, 0, 1, 0).
Column 6 ~ column 31 : Reserved.
Rev 0.9
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(Rev 0.9)
MYSON
TECHNOLOGY
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage (VDD,VDDA)
Voltage with respect to Ground
Storage Temperature
Ambient Operating Temperature
-0.3 to +7 V
-0.3 to VDD+0.3 V
-65 to +150 oC
0 to +70 oC
5.0 OPERATING CONDITIONS
DC Supply Voltage (VDD,VDDA)
Operating Temperature
+4.75 to +5.25 V
0 to +70 oC
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
SYMBOL
VODL
PARAMETER
Input High Voltage
(pin hflb, vflb, sda, sck)
Input High Voltage
(pin ssb)
Input Low Voltage
(pin hflb, vflb, sda, sck)
Input Low Voltage
(pin ssb)
Output High Voltage
Output Low Voltage
Open Drain Output Low
Voltage
ICC
Operating Current
ISB
Standby Current
VIH
VIL
VOH
VOL
CONDITIONS (NOTES)
MIN.
MAX.
UNITS
-
0.6 * VDD
VDD+0.3
V
0.7 * VDD
VDD+0.3
V
VSS-0.3
0.25 * VDD
V
VSS-0.3
0.2 * VDD
V
IOH ≥ -5 mA
IOL ≤ 5 mA
VDD-0.8
-
0.5
V
V
5 mA ≥ IODL
-
0.5
V
-
25
mA
-
12
mA
MAX.
150
5
5
-
UNITS
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
Pixel rate=96MHz
Iload = 0uA
Vin = VDD,
Iload = 0uA
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
SYMBOL
fHFLB
Tr
Tf
tBCSU
tBCH
tDCSU
tDCH
tSCKH
tSCKL
tSU:STA
tHD:STA
tSU:STO
tHD:STO
Rev 0.9
PARAMETER
HFLB input frequency
Output rise time
Output fall time
SSB to SCK set up time
SSB to SCK hold time
SDA to SCK set up time
SDA to SCK hold time
SCK high time
SCK low time
START condition setup time
START condition hold time
STOP condition setup time
STOP condition hold time
MIN.
15
200
100
200
100
500
500
500
500
500
500
- 17 -
TYP.
-
2001/03/15
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(Rev 0.9)
MYSON
TECHNOLOGY
8.0 TIMING DIAGRAMS
tSCKH
SCK
tSCKL
SSB
tBCSU
tBCH
SDA
tDCSU
tDCH
FIGURE 11. Data Interface Timing (SPI)
tSCKH
SCK
tSCKL
tSU:STA
tHD:STO
SDA
tHD:STA
tDCSU
tDCH
tSU:STO
FIGURE 12. Data Interface Timing (I2C)
Rev 0.9
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2001/03/15
MTV048
(Rev 0.9)
MYSON
TECHNOLOGY
9.0 PACKAGE DIMENSION
9.1 16 Pin PDIP 300mil
9.2 16 Pin SOP 300mil
0.406 +/-0.013
0.295 +/-0.004
0.015x45°
7°(4x)
0.406 +/-0.008
(4x)
0.091
0.016 +/-0.004
Rev 0.9
0.098 +/-0.006
0.028 +0.022 /-0.013
0.0501
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2001/03/15