TDA18218HN DVB-T Silicon Tuner IC Rev. 01 — 8 July 2009 Product data sheet 1. General description The TDA18218HN is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV reception. The TDA18218HN integrates the overall tuning function, including selectivity and provides a low-IF output signal. The TDA18218HN uses integrated IF filters to support 6 MHz, 7 MHz or 8 MHz channel bandwidths. The TDA18218HN requires only one single 16 MHz crystal for clock generation. A clock signal is available on crystal oscillator output pins (XTO_P / XTO_N) to synchronize the channel decoder. The TDA18218HN is a low cost Silicon Tuner targeting digital terrestrial applications. The TDA18218HN matches the performance of the conventional can tuners. Additionally, the following benefits can be stated: • Easy on-board integration • Drastically reduces: – the size of the tuner function – the power consumption 2. Features n n n n n n n n n n n n Fully integrated IF selectivity; eliminating the need for external SAW filters Fully integrated oscillators with no external components Integrated wideband gain control Alignment free RF loop-through for easy implementation in the Set-Top Box (STB) Integrated die thermal sensor Single 3.3 V power supply Low power consumption (750 mW) Crystal oscillator output buffer (16 MHz) for single crystal applications I2C-bus interface compatible with 3.3 V and 5 V microcontrollers Three Standby modes RoHS packaging 3. Applications n DVB-T Set-Top Box (STB) and TV receiver n System application optimization is described in the application note AN0814 n Driver application is described in the application note AN0822 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 4. Quick reference data Table 1. Quick reference data Tamb = 25 °C; VCC = 3.3 V; IF output level option = 2 V (p - p); IF output load = 1 kΩ on each terminal Symbol Parameter Conditions Min Typ Max Unit fRF RF frequency center of channel 174 - 864 MHz NFtun tuner noise figure normal mode; maximum gain - 5 7 dB ϕn phase noise worst case in the RF frequency range 10 kHz - −85 - dBc/Hz 100 kHz - −105 - dBc/Hz - 775 - mW - 108 - dBµV - 65 - dB - −82 - dBm P power dissipation Vi(max) maximum input voltage 1 dB gain compression, one analog TV signal αimage image rejection normal mode [1] DVB-T (64 QAM 2/3); BER = 2 × digital sensitivity Sdig 10−4 [1] Measured with TDA10048 channel decoder. 5. Ordering information Table 2. Ordering information Type number TDA18218HN Package Name Description Version HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 × 7 × 0.85 mm SOT619-1 6. Block diagram AGC2 AGC1 RF_IN mixer IF SELECTIVITY LPFc IF AGC 31 1 30 LEVEL CONTROL LT BP FILTER 46 32 LEVEL CONTROL IFO_N VIFAGC TDA18218HN ATTENUATOR 19 I2C INTERFACE 22 AS Fig 1. IFO_P 35 SCL SYNTHESIZER 36 SDA 14 15 VTLO CPLO CRYSTAL OSCILATOR 16 XTAL_P 20 XTO_P XTO_N 17 XTAL_N 001aaj012 Block diagram TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 2 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 7. Pinning information 37 CAPRFAGC 38 GND(RF) 39 i.c. 40 GND(RF) 41 GND(RF) 42 GND(RF) 43 i.c. 44 GND(RF) 45 VCC(RF) 46 LT 48 i.c. terminal 1 index area 47 VCC(RF) 7.1 Pinning RF_IN 1 36 SDA i.c. 2 35 SCL i.c. 3 34 GND(DIG) GND(RF) 4 33 i.c. i.c. 5 32 VIFAGC i.c. 6 GND(IF) 7 VCC(IF) 8 i.c. 9 31 IFO_P TDA18218HN 30 IFO_N 29 VCC(IF) 28 GND(IF) CAPREG_VCO 10 27 REG28 GND(VCO) 11 26 REG18 CP_K 24 GND(IF) 23 AS 22 XTAL_MS 21 XTO_N 20 XTO_P 19 i.c. 18 XTAL_N 17 XTAL_P 16 CPLO 15 VTLO 14 25 VT_K GND(PLL) 13 VCC(PLL) 12 001aaj013 Transparent top view Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description RF_IN 1 unbalanced RF input i.c. 2 internally connected; leave open i.c. 3 internally connected; leave open GND(RF) 4 RF ground i.c. 5 internally connected; leave open i.c 6 internally connected; leave open GND(IF) 7 IF ground VCC(IF) 8 IF supply voltage (3.3 V) i.c. 9 internally connected; leave open CAPREG_VCO 10 VCO supply decoupling GND(VCO) 11 VCO ground VCC(PLL) 12 PLL supply voltage GND(PLL) 13 PLL ground VTLO 14 local oscillator (LO) tuning voltage input TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 3 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 3. Pin description …continued Symbol Pin Description CPLO 15 charge pump of the LO synthesizer XTAL_P 16 crystal oscillator input positive XTAL_N 17 crystal oscillator input negative i.c. 18 internally connected; leave open XTO_P 19 crystal oscillator output buffer positive XTO_N 20 crystal oscillator output buffer negative XTAL_MS 21 XTAL out mode AS 22 I2C-bus address selection input GND(IF) 23 IF ground CP_K 24 charge pump of the calibration synthesizer VT_K 25 tuning voltage of the calibration synthesizer REG18 26 internal regulator decoupling REG28 27 internal regulator decoupling GND(IF) 28 IF ground VCC(IF) 29 IF supply voltage (3.3 V) IFO_N 30 IF output negative IFO_P 31 IF output positive VIFAGC 32 IF gain control input i.c. 33 internally connected; leave open GND(DIG) 34 digital ground SCL 35 I2C-bus clock input SDA 36 I2C-bus data input and output CAPRFAGC 37 RF AGC filtering GND(RF) 38 RF ground i.c. 39 internally connected; leave open GND(RF) 40 RF ground GND(RF) 41 RF ground GND(RF) 42 RF ground i.c. 43 internally connected; leave open GND(RF) 44 RF ground VCC(RF) 45 RF supply voltage LT 46 loop-through VCC(RF) 47 RF supply voltage i.c. 48 internally connected; leave open 8. Functional description The RF input signal is driven to a low-noise amplifier. It is then amplified and fed to the image rejection mixer. The mixer down-converts the RF signal to a low IF frequency, which depends on channel bandwidth (standard IF filters are implemented for 6 MHz, 7 MHz TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 4 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC and 8 MHz channel bandwidths). The TDA18218HN requires a single 16 MHz crystal for clock generation, a 16 MHz differential sine wave clock reference is available to drive a channel decoder. 8.1 AGC1 stage The TDA18218HN embeds 2 different RF amplifiers with internal gain control. The first stage, AGC1, behaves like a LNA (Low noise amplifier); its gain can take 4 different values (15 dB, 12 dB, 9 dB and 6 dB). Purpose of this amplifier is to ensure a low noise figure for the tuner. In order to optimize noise and linearity performances an internal level detector selects the appropriate gain: • If the signal level at the tuner is low, the gain is set to the maximum value (15 dB). • If the signal level at the tuner input is high, the gain is set to the minimum value (6 dB). • In between the gain is set to an intermediate value 12 dB or 9 dB. The strategy of the level detection is a proprietary algorithm from NXP, managed by the driver. It should be noted that: 1. The level detector measures the signal level within the complete RF frequency range, i.e. from 50 MHz to 870 MHz. Consequently, AGC1 gain is adapted to the complete RF power. If a strong signal is present at the tuner input, it will determine AGC1 gain (even if it is not the wanted signal). This concept prevents the tuner from overloading. 2. The level control is always operating. 8.2 AGC2 stage The second stage, AGC2, is also an amplifier with a gain controlled thanks to a level detector. The gain is controlled between −12 dB and +16.4 dB, it is adapted by steps of 0.2 dB. It should be noted that: 1. The level control is always operating. Consequently, this amplifier is responsible for adapting the daily level changes. 2. The level detector measures the signal level within the complete RF frequency range (same as AGC1) The strategy of the level detection is a proprietary algorithm from NXP, managed by the driver. 8.3 IF AGC Finally, in order to adapt the tuner output level, a last amplifier is used (IF AGC). This amplifier delivers the appropriate level to the DVB-T channel decoder. The output level is therefore controlled thanks to the DC voltage applied on VIFAGC pin. This voltage is commonly delivered by the channel decoder. TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 5 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC It should be noted that the level control is always operating. The strategy of the level detection has to be adapted for each type of channel decoder. It must be defined to satisfy ADC sampling (minimum level, ADC headroom). All AGC amplifiers are controlled independently. 8.4 Power-down mode The TDA18218HN can be programmed in Standby mode. The following blocks are turned off when programming a power-down: • • • • • AGC2 and its level detector BP filter Mixer and VCO IF selectivity LPFc IF AGC Remaining functions are: • Loop-Through • 16 MHz clock output (to drive a channel decoder) • I2C-bus Core (to wake-up the IC later on) 9. Control interface 9.1 I2C-bus format, write and read mode I2C-bus uses two pins (SDA and SCL) to transfer information between devices connected to the bus. The SDA pin provides bidirectional data transfer. While the SCL pin provides the timing sequences. Data can be read and written as follows: Write mode: • Any register can be written to using its subaddress • Any following (contiguous) registers can be written using the subaddress of the first register Read mode: • The read after Restart mode is not allowed. In addition, registers cannot be read using the subaddress of the register. However, registers can be read as follows: – from 00h to 16h – from 00h to 27h – from 00h to 3Ah – from 00h to any register subaddress, if MSB = 1 for the next register TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 6 of 25 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TDA18218HN_1 Product data sheet Table 4. I2C-bus register map Sub Register address Bit 7 (MSB) 6 5 4 3 Address byte 1 1 1 0 0 0 Address byte 2 0 0 2 1 MA[1:0] 0 (LSB) R/W AD[5:0] ID[6:0] Initial POR value (Hex) (Hex) - - - - C0[1] C0 88 80 Rev. 01 — 8 July 2009 1 Read byte 1 - 02h Read byte 2 - 00 00 03h Read byte 3 AGC2[7:0] 8E 3C 04h Read byte 4 03 00 05h Read byte 5 - 00 00 06h Read byte 6 - 00 00 07h Main divider byte 1 - D0 F0 08h PSM byte 1 - 00 00 09h Main divider byte 2 - 40 40 0Ah Main divider byte 3 LO_Frac_0[31:24] 00 00 0Bh Main divider byte 4 LO_Frac_1[23:16] 00 00 0Ch Main divider byte 5 07 00 0Dh Main divider byte 6 - FF 01 0Eh Main divider byte 7 - 84 84 0Fh Main divider byte 8 09 08 10h Call divider byte 1 - 00 00 11h Call divider byte 2 - 13 13 12h Call divider byte 3 - 00 00 LO_Lock AGC1[2] CAL_Lock - TM_D[3:0] - LT[1:0] LO_Frac_2[15:12] - AGC1[1:0] - Freq_prog_ Start - TDA18218HN ID byte 01h DVB-T Silicon Tuner IC 7 of 25 © NXP B.V. 2009. All rights reserved. 00h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus register map …continued Sub Register address Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) Initial POR value (Hex) (Hex) 13h Call divider byte 4 - 00 00 14h Call divider byte 5 - 01 01 15h Call divider byte 6 - 84 84 16h Call divider byte 7 - 09 09 17h Power-down byte 1 - F0[2] B5 Power-down byte 2 - 18h pdLT - RFSW_MTO _LT_RFin pdAGC1b - PD_RFAGC _Ifout PD_LO_ Synthe SM pdDETECT1 pdAGC2b - NXP Semiconductors TDA18218HN_1 Product data sheet Table 4. B0[3] 19[2] 59 Rev. 01 — 8 July 2009 59[3] - 1Ah IF byte 1 1Bh IF byte 2 1Ch AGC2b byte pulse_up_ auto 1Dh PSM byte 2 TM_ Range 1Eh PSM byte 3 1Fh PSM byte 4 AGC1_Speed[1:0] 20h AGC1 byte 1 AGC2_RAM_sel[1:0] AGC2_ Gup_sel 21h AGC1 byte 2 AGC2_Speed[1:0] - 22h AGC1 byte 3 23h AGC2 byte 1 24h AGC2 byte 2 25h Analog AGC byte 26h RC byte - 85 80 27h RSSI byte - C9 8E - XtOut[3:0] IF_level[2:0] - BP_Filter[2:0] pulse_up_ width[1:0] LP_Fc[1:0] AGC_On - TM_ON - AGC1_au_ptr[1:0] AGC1_ aud_sel AGC1_ Gup_sel Manual_LT AGC1_aud[2:0] AGC1_Gud[4:0] - AGC2_Gud[4:0] - IFAGC_Top[3:0] 0A 0A 8E 86 69 6A 98 98 01 C3 00 00 58 58 10 00 40 40 8C 80 00 00 0C 0C 48 48 TDA18218HN XTOUT byte DVB-T Silicon Tuner IC 8 of 25 © NXP B.V. 2009. All rights reserved. 19h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus register map …continued Sub Register address Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) Initial POR value (Hex) (Hex) Rev. 01 — 8 July 2009 28h IR CAL byte 1 - A7 F5 29h IR CAL byte 2 - 00 30 2Ah IR CAL byte 3 - 00 30 2Bh IR CAL byte 4 - 00 00 2Ch RF CAL byte 1 - 30 30 2Dh RF CAL byte 2 - 81 80 2Eh RF CAL byte 3 - 80 00 2Fh RF CAL byte 4 - 00 00 30h RF CAL byte 5 - 39 36 31h RF CAL byte 6 - 00 00 32h RF CAL byte 7 - 8A 8A 33h RF CAL byte 8 - 00 00 34h RF CAL byte 9 - 00 00 35h RF CAL byte 10 - 00 00 36h RF CAL RAM byte 1 - 00 00 37h RF CAL RAM byte 2 - 00 00 38h Margin byte - 00 00 39h Fmax byte 1 - F6 F6 3Ah Fmax byte 2 - F6 F6 Case TDA18218HN is a device without LT. [3] Case TDA18218HN is a device with LT. 9 of 25 © NXP B.V. 2009. All rights reserved. TDA18218HN See Section 9.2.1 “Device type address ID”. [2] DVB-T Silicon Tuner IC [1] NXP Semiconductors TDA18218HN_1 Product data sheet Table 4. TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 9.2 I2C-bus address selection The programmable module address bits MA[1:0] allow up to four tuners to be addressed in one system. Bits MA[1:0] are programmed by applying a specific voltage (VAS) to pin AS. The relationship between the status of bits MA[1:0] and the voltage applied to pin AS is shown in Table 5. Table 5. Address byte 1 bit descriptions Legend: * power-on reset value. Bit Symbol 7 to 3 2 to 1 0 Access Value Description - R/W 1 1000* must be set to 1 1000 MA[1:0] R/W R/W programmable address bit value set with VAS R/W 00 VAS = 0 V to 0.1 × VCC 01 VAS = 0.2 × VCC to 0.3 × VCC 10 VAS = 0.4 × VCC to 0.6 × VCC 11 VAS = 0.9 × VCC to VCC 0 write mode 1 read mode Example: MA[1:0] = 00, R/W = 0, full module address = 1100 0000 (C0h). Table 6. Address byte 2 bit descriptions Legend: * power-on reset value. Bit Symbol Access Value Description 7 to 6 - R/W 00* must be set to 00 5 to 0 AD[5:0] R/W - programmable address bits of the first programming byte 9.2.1 Device type address ID Table 7. ID byte bit descriptions Legend: * power-on reset value. Address Register Bit Symbol Access Value Description 00h ID byte 7 - R 1* must be 1 6 to 0 ID[6:0] R 100 0000* TDA18218HN device type address 9.3 Crystal buffer output TDA18218HN embeds a Xtal oscillator and a buffer to drive another IC. The buffer can be configured through register XTOUT (I2C-bus sub address 19h). This buffer has been designed to be AC coupled. This output can be used in differential or sinusoidal mode (using XTO_N and XTO_P pins) or in asymmetrical or square mode (just leaving one pin open). It should be noted that TDA18218HN specification refers to differential output with no load. TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 10 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 8. Crystal buffer output register bit descriptions Address Register Bit Symbol Access 19h XTOUT byte 3 to 0 XtOut[3:0] R/W Value Description crystal buffer output 0 XTAL off 1 XTOUT off 2 square wave 16 MHz 7 sine wave 200 mV 8 sine wave 400 mV 9 sine wave 800 mV 10 sine wave 1200 mV other not applicable 9.4 Temperature sensor Table 9. Temperature sensor bit descriptions Address Register Bit Symbol Access Value Description 1Dh 6 TM_ON W PSM byte 2 temperature sensor on or off 0 1 7 01h [1] TM_Range R/W Read byte 1 3 to 0 TM_D[3:0] R temperature sensor switched on temperature range selection 0 60 °C to 90 °C 1 92 °C to 122 °C - die temperature[1] The die temperature can be read as shown in Table 10. Table 10. TM_D[3:0] Die temperature values Temperature range selection (die temperature) TM_RANGE = 0 TM_RANGE = 1 0000 60 °C 92 °C 0001 62 °C 94 °C 0010 66 °C 98 °C 0011 64 °C 96 °C 0100 74 °C 106 °C 0101 72 °C 104 °C 0110 68 °C 100 °C 0111 70 °C 102 °C 1000 90 °C 122 °C 1001 88 °C 120 °C 1010 84 °C 116 °C 1011 86 °C 118 °C 1100 76 °C 108 °C TDA18218HN_1 Product data sheet temperature sensor switched off © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 11 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 10. Die temperature values …continued TM_D[3:0] Temperature range selection (die temperature) TM_RANGE = 0 TM_RANGE = 1 1101 78 °C 110 °C 1110 82 °C 114 °C 1111 80 °C 112 °C 9.5 Standby mode selection Table 11. Standby mode selection Mode Power down byte 1 (address 17h) SM (bit 0) pdAGC1b (bit 3) XTOUT Device-off mode 1 1 see Table 8 Standby mode with loop-through and crystal oscillator on (default at POR), XTOUT 1200 mV 1 0 see Table 8 Standby mode with only crystal oscillator on 1 1 see Table 8 9.6 IF level Refer to Table 21 “General characteristics for TV reception (RF input to IF output)”. 9.7 AGC and band-pass filters Table 12. AGC and band-pass filter bit descriptions Address Register Bit 03h Read byte 3 7 to 0 AGC2[7:0] R/W 04h Read byte 4 7 and AGC1[2:0] 1 to 0 R/W 1Ah 1Bh 1Ch IF byte 1 IF byte 2 AGC2b byte Symbol 2 to 0 BP_Filter[2:0] 1 to 0 LP_Fc[1:0] 4 AGC_On Access Value Description - AGC1 gain range = 6 dB to 15 dB 0 6 dB 1 9 dB 2 12 dB 3 15 dB W band-pass filters 3 filter 3 (174 MHz to 188 MHz) 4 filter 4 (188 MHz to 253 MHz) 5 filter 5 (253 MHz to 343 MHz) 6 filter 6 (343 MHz to 870 MHz; bypass) W low-pass filter cut-off frequency 0 6 MHz 1 7 MHz 2 8 MHz W AGC1 and AGC2 clock on or off 0 off 1 on TDA18218HN_1 Product data sheet AGC2 gain = 0.2 × (AGC2[7:0]) − 12 (dB) range = −12 dB to 16.4 dB © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 12 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 9.8 RFin to LT path Table 13. RFin to LT path bit descriptions Address Register Bit Symbol Access 20h AGC1 byte 1 3 Manual_LT W 04h Read byte 4 3 to 2 Table 14. LT[1:0] Value Description loop-through command R/W 0 sets LT attenuation depending on state of pin XTAL_MS; see Table 14 1 sets LT attenuation manually; see Table 15 - sets LT gain in range: −6 dB to −15 dB; see Table 15 RFin to LT gain control modes Bit Manual_LT Pin XTAL_MS AGC1 and LT attenuator gain modes 0 LOW AGC1 gain fixed at 6 dB; LT gain set by LT[1:0]; see Table 15 0 HIGH LT gain set automatically function of AGC1 gain; see Table 15 1 LOW AGC1 gain fixed at gain set by AGC1[2:0]; LT gain set by LT[1:0]; see Table 15 1 HIGH AGC1 gain set automatically; LT gain set by LT[1:0]; see Table 15 Table 15. Loop-through attenuator gain settings LT[1] LT[0] Loop-through gain 0 0 −6 dB 0 1 −9 dB 1 0 −12 dB 1 1 −15 dB 9.9 PLL settings Table 16. PLL bit descriptions Address Register Bit Symbol Access Value Description 0Ah Main divider byte 3 7 to 0 LO_Frac_0[31:24] R 0Bh Main divider byte 4 7 to 0 LO_Frac_1[23:16] 0Ch Main divider byte 5 7 to 4 LO_Frac_2[15:12] 01h Read byte 1 6 LO_Lock - R LO lock flag 0 1 5 0Fh Main divider byte 8 6 CAL_Lock R Freq_prog_Start W PLL unlocked PLL locked calibration oscillator lock flag 0 PLL unlocked 1 PLL locked 1 TDA18218HN_1 Product data sheet LO frequency setting (kHz); in automatic mode launch automatic mode of PLL calculation (LO and calibration synthesizer); automatically reset to logic 0 (internally) when LO and calibration are completed © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 13 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 9.10 Power-down and switches Table 17. Power-down and switches bit descriptions Address Register Bit Symbol Acces s 17h 6 R/W Power-down byte 1 3 pdLT Value Description loop-through output switch 0 closed 1 open AGC1 power-down[1] pdAGC1b 0 LNA on 1 2 1 0 18h Power-down byte 2 6 2 1 PD_RFAGC_Ifout LNA off mixer and IF stages power-down 0 blocks on 1 blocks off PD_LO_Synthe LO synthesizer power-down 0 PLL on 1 PLL off Standby mode; I2C-bus interface, crystal oscillator and AGC1 are turned on SM RFSW_MTO_LT_RFin 0 normal 1 standby R/W provides the RF signal to the loop-through[2] 0 switch is open 1 switch is closed pdDETECT1 AGC1 detector power-down 0 detector on 1 detector off AGC2 power-down[1] pdAGC2b [1] This setting controls the status of the Low Noise Amplifier (LNA). [2] RFSW_MTO_LT_RFin = 0 in tuner applications with loop-through disabled. RFSW_MTO_LT_RFin = 1 in tuner applications with loop-through enabled. 0 LNA on 1 LNA off 10. Limiting values Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions TDA18218HN_1 Product data sheet Min Max Unit −0.3 +3.60 V © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 14 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 18. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VI input voltage pins SDA and SCL −0.3 +5.5 V VCC < 3.3 V −0.3 VCC + 0.3 V VCC > 3.3 V −0.3 +3.6 V all other pins Tstg storage temperature −40 +150 °C Tj junction temperature - +95 °C VESD electrostatic discharge voltage EIA/JESD22-A114 (human body model) ±2000 - V EIA/JESD22-C101-C (FCDM) class III[1] ±200 - V [1] Class III: 200 V to 1000 V. 11. Thermal characteristics Table 19. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from according to JEDEC specijunction to ambient fication 4L board with 16 thermal vias - 29.9 - K/W Tamb ambient temperature 0 - +70 °C - 12. Characteristics Table 20. Loop-through characteristics (RF input to loop-through output) Tamb = 25 °C, VCC = 3.3 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fRF(lt) loop-through RF frequency center of channel 54 - 864 MHz |s11|2 input return loss 75 Ω nominal impedance - −8 - dB |s22|2 output return loss 75 Ω nominal impedance - −8 - dB Gv(lt) loop-through voltage gain 75 Ω load - −0.5 - dB ∆Glt loop-through gain variation in the RF frequency range; 75 Ω load - 2 4 dB NFlt loop-through noise figure maximum gain CSOlt loop-through composite second-order distortion [1] CTBlt loop-through composite triple beat [1] αisol(bp) bypass isolation [1] from loop-through output to RF input - 6 - dB - −51 - dBc - −55 - dBc - 40 - dB Channel loading assumptions: 129 channels at 75 dBµV. TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 15 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 21. General characteristics for TV reception (RF input to IF output) Tamb = 25 °C, VCC = 3.3 V, IF output level option 2 V (p - p), IF output load = 1 kΩ on each pin; unless otherwise specified. Symbol Parameter VCC supply voltage ICC supply current Conditions Min Typ Max Unit 3.13 3.30 3.47 V - 235[2] 270[3] mA device-off mode - 3 - mA Standby mode with loop-through and crystal oscillator on (default at POR), XTOUT 1200 mV - 60 - mA Standby mode with only oscillator on - 22 - mA - 775 - mW 174 - 864 MHz 6 MHz - 3 - MHz 7 MHz - 3.5 - MHz 8 MHz - 4 - MHz normal mode P power dissipation fRF RF frequency center of channel fIF(nom) nominal IF frequency center of channel; for channel bandwidth [1] Gv voltage gain normal mode 70 76 - dB ∆GAGC(tun) tuner AGC gain range normal mode - 63 - dB NFtun tuner noise figure normal mode; maximum gain - 5 7 dB Vo(IF)dif(p-p) peak-to-peak differential IF output IF_level[2:0] = 000 voltage IF_level[2:0] = 010 - 2 - V - 1 - V IF_level[2:0] = 111 - 0.5 - V Zo(IF) IF output impedance differential mode; magnitude value - 100 - Ω ∆GAGC(IF) IF AGC GAIN range 2 V (peak-to-peak) IF output voltage selection - 30 - dB Gtlt tilt gain RF frequency range fIF(stpb)lp low-pass stop-band IF frequency 6 MHz IF filter (1 MHz to 5.5 MHz) - - 4 dB 7 MHz IF filter (1 MHz to 6.5 MHz) - - 4 dB 8 MHz IF filter (1 MHz to 7.5 MHz) - - 4 dB 60 dB attenuation 6 MHz IF filter (1 MHz to 5.5 MHz) - 12 - MHz 7 MHz IF filter (1 MHz to 6.5 MHz) - 14 - MHz 8 MHz IF filter (1 MHz to 7.5 MHz) - 16 - MHz - 65 - dB 6 MHz IF filter (1 MHz to 5.5 MHz) - 155 - ns 7 MHz IF filter (1 MHz to 6.5 MHz) - 165 - ns 8 MHz IF filter (1 MHz to 7.5 MHz) - 175 - ns 10 kHz - −85 - dBc/Hz 100 kHz - −105 - dBc/Hz at power-up - - 1 s αimage image rejection normal mode td(grp) group delay time normal mode ϕn tstartup(tun) phase noise tuner start-up time worst case in the RF frequency range TDA18218HN_1 Product data sheet [4] © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 16 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 21. General characteristics for TV reception (RF input to IF output) …continued Tamb = 25 °C, VCC = 3.3 V, IF output level option 2 V (p - p), IF output load = 1 kΩ on each pin; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tset setting time channel change - - 60 ms ftun(step) tuner frequency (step size) - 1 - kHz Vi(max) maximum input voltage 1 dB gain compression, one analog TV signal - 108 - dBµV Sdig digital sensitivity DVB-T (64 QAM 2/3); BER = 2 × 10−4 - −82 - dBm [1] XTAL buffer off. [2] Measured at 3.3 V. [3] Measured at 3.47 V. [4] Difference defined between maximum and minimum over the IF bandwidth. [5] Measured with TDA10048 channel decoder. [5] Table 22. Pin characteristics Tamb = 25 °C, VCC = 3.3 V; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit 0 - VCC V - - - MΩ - 30 55 dB/V - 16 - MHz - 500 - Ω IF AGC input: pin VIFAGC VAGC AGC voltage Zi input impedance dGAGC/dV rate of change of AGC gain with voltage [1] Crystal oscillator fxtal crystal frequency Zi input impedance magnitude value; crystal specification: Rs = 150 Ω max; drive level < 100 µW Crystal oscillator output buffer Square mode: only on XTO_N (XtOut[3:0] = 2) Ro output resistance 16 MHz output frequency - 90 - Ω Vo(p-p) peak-to-peak output voltage 10 kΩ; 10 pF AC load; same load on XTO_P and XTO_N - 0.6 - V SRr slew rate of rising signal 10 kΩ; 10 pF AC load - 150 - V/µs SRf slew rate of falling signal 10 kΩ; 10 pF AC load - 80 - V/µs Sinusoidal mode: on XTO_P and XTO_N (XtOut[3:0] = 8) Ro output resistance 16 MHz output frequency - 480 - Ω Vo(p-p) peak-to-peak output voltage 10 kΩ; 10 pF AC load; same load on XTO_P and XTO_N - 0.4 - V fixed input levels - - 1.5 V VDD related input levels - - 0.3 × VCC V fixed input levels 3 - - V VDD related input levels 0.7 × VCC - - V Digital levels I2C-bus[2] Pin SCL VIL VIH LOW-level input voltage HIGH-level input voltage TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 17 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC Table 22. Pin characteristics …continued Tamb = 25 °C, VCC = 3.3 V; unless otherwise specified Symbol Parameter fSCL SCL clock frequency Conditions Min Typ Max Unit - - 400 kHz pin SDA VOH HIGH-level output voltage ISDA = 3 mA (sink current) - - 0.4 V VIL LOW-level input voltage fixed input levels - - 1.5 V VDD related input levels - - 0.3 × VCC V fixed input levels 3 - - V VDD related input levels 0.7 × VCC - - V HIGH-level input voltage VIH [1] Typical value is HIGH impedance input. [2] Devices that use non-standard supply voltages, which do not conform to the intended I2C-bus system levels, must relate their input levels to the supply voltage to which the pull-up resistors are connected. TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 18 of 25 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 150 pF 1 nF 1 µH BLM18HK102SNI BAV99W K1 +3V3_TUN +3V3_TUN 47 nF 47 nF 470 pF 470 pF 1 1 nF 150 pF RF_IN_OUT RF_IN 1 µH BLM18HK102SNI BAV99W i.c. i.c. Rev. 01 — 8 July 2009 GND(RF) i.c. 47 nF 470 pF 100 nF 4.7 kΩ 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 i.c. +3V3_TUN +3V3_TUN CAPRFAGC GND(RF) i.c. GND(RF) GND(RF) GND(RF) i.c. GND(RF) 2 LT VCC(RF) 220 nF i.c. VCC(RF) 3 4 5 6 7 8 9 10 11 NXP Semiconductors TDA18218HN_1 Product data sheet 13. Application information 6 GND(IF) 7 VCC(IF) 8 i.c. 9 CAPREG_VCO 10 GND(VCO) 11 VCC(PLL) 12 31 TDA18218HN SDA SCL GND(DIG) V_IF_AGC i.c. 100 nF VIFAGC IF OUT P IFO_P IFO_N 30 VCC(IF) 29 GND(IF) 28 REG28 27 REG18 26 VT_K 25 GND 4.7 kΩ 100 nF 100 nF IF OUT N +3V3_TUN 470 pF 47 nF 100 nF 10 nF U14 CP_K GND(IF) AS XTO_N XTO_P i.c. XTAL_N CPLO XTAL_P VTLO XTAL_MS 470 pF GND(PLL) 13 14 15 16 17 18 19 20 21 22 23 24 220 nF 120 Ω 3.9 nF 6.8 nF 220 nF 0.75 pF 4.7 nF XTOUT 1 nF 19 of 25 © NXP B.V. 2009. All rights reserved. 18 pF 6.8 nF 390 Ω Cxtal(1) 18 pF QZ3 16 MHz 001aaj014 (1) Cxtal not connected for NDK; Cxtal = 1.5 pF for Siward. Fig 3. Application diagram DVB-T Silicon Tuner IC 390 Ω TDA18218HN 390 Ω 47 nF +3V3_TUN TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 14. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm A B D SOT619-1 terminal 1 index area A E A1 c detail X C e1 1/2 e e 13 24 y y1 C v M C A B w M C b L 25 12 e e2 Eh 1/2 e 1 36 terminal 1 index area 48 37 Dh X 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 5 mm c D (1) Dh E (1) Eh 0.2 7.1 6.9 5.25 4.95 7.1 6.9 5.25 4.95 e e1 5.5 0.5 e2 L v 5.5 0.5 0.3 0.1 w 0.05 y y1 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Fig 4. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT619-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Package outline HVQFN48 - SOT619-1 TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 20 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 15. Abbreviations Table 23. Abbreviations Acronym Description ADC Analog-to-Digital Converter AGC Automatic Gain Control BER Bit Error Rate BP Band-Pass Cxtal crystal Capacitor DVB-T Digital Video Broadcasting – Terrestrial DVR Digital Video Recorder FCDM Flow Control Decision Message IC Integrated Circuit IF Intermediate Frequency LNA Low Noise Amplifier LPFc Low Pass Frequency cut LO Local Oscillator LT Loop-Through MSB Most Significant Bit PCB Printed-Circuit Board PLL Phase-Locked Loop POR Power-On Reset QAM Quadrature Amplitude Modulation RF Radio Frequency RoHS Restriction of Hazardous Substances SAW Surface Acoustic Wave STB Set-Top Box TOP Take-Over Point VCO Voltage Controlled Oscillator XTAL Crystal TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 21 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 16. Revision history Table 24. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA18218HN_1 20090708 Product data sheet - - TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 22 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 17. Legal information 18. Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.2 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 18.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. Silicon Tuner — is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 23 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 20. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3 I2C-bus register map . . . . . . . . . . . . . . . . . . . . .7 Address byte 1 bit descriptions . . . . . . . . . . . .10 Address byte 2 bit descriptions . . . . . . . . . . . .10 ID byte bit descriptions . . . . . . . . . . . . . . . . . .10 Crystal buffer output register bit descriptions .11 Temperature sensor bit descriptions . . . . . . . .11 Die temperature values . . . . . . . . . . . . . . . . . .11 Standby mode selection . . . . . . . . . . . . . . . . .12 AGC and band-pass filter bit descriptions . . . .12 RFin to LT path bit descriptions . . . . . . . . . . . .13 Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. RFin to LT gain control modes . . . . . . . . . . . . 13 Loop-through attenuator gain settings . . . . . . 13 PLL bit descriptions . . . . . . . . . . . . . . . . . . . . . 13 Power-down and switches bit descriptions . . . 14 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal characteristics . . . . . . . . . . . . . . . . . . 15 Loop-through characteristics (RF input to loop-through output) . . . . . . . . . . 15 General characteristics for TV reception (RF input to IF output) . . . . . . . . . . . . . . . . . . . 16 Pin characteristics . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 21. Figures Fig 1. Fig 2. Fig 3. Fig 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .3 Application diagram . . . . . . . . . . . . . . . . . . . . . . .19 Package outline HVQFN48 - SOT619-1 . . . . . . .20 TDA18218HN_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 8 July 2009 24 of 25 TDA18218HN NXP Semiconductors DVB-T Silicon Tuner IC 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.2.1 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 19 20 21 22 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 AGC1 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AGC2 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-down mode . . . . . . . . . . . . . . . . . . . . . . 6 Control interface . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C-bus format, write and read mode . . . . . . . . 6 I2C-bus address selection. . . . . . . . . . . . . . . . 10 Device type address ID. . . . . . . . . . . . . . . . . . 10 Crystal buffer output . . . . . . . . . . . . . . . . . . . . 10 Temperature sensor . . . . . . . . . . . . . . . . . . . . 11 Standby mode selection . . . . . . . . . . . . . . . . . 12 IF level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AGC and band-pass filters . . . . . . . . . . . . . . . 12 RFin to LT path . . . . . . . . . . . . . . . . . . . . . . . . 13 PLL settings . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down and switches . . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal characteristics. . . . . . . . . . . . . . . . . . 15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 July 2009 Document identifier: TDA18218HN_1