FEATURES Maximum output current: 2 A Input voltage range: 1.6 V to 3.6 V Low shutdown current: <1 μA Low dropout voltage: 200 mV @ 2 A load Initial accuracy: ±1% Accuracy over line, load, and temperature: ±2.5% 7 fixed output voltage options with soft start (ADP1740): 0.75 V to 2.5 V Adjustable output voltage options with soft start (ADP1741): 0.75 V to 3.0 V Stable with small 4.7 μF ceramic output capacitor Excellent load/line transient response Current limit and thermal overload protection Power Good indicator Logic-controlled enable TYPICAL APPLICATION CIRCUITS VIN = 1.8V VOUT = 1.5V 4.7µF 4.7µF 16 IN 1 IN 13 14 OUT OUT OUT 12 PIN 1 INDICATOR 2 IN 100kΩ 15 IN ADP1740 OUT 11 TOP VIEW OUT 10 (Not to Scale) 3 IN 4 EN SENSE 9 PG 5 NC 8 GND SS 7 6 10nF 07081-001 Preliminary Technical Data 2 A, Low Dropout, CMOS Linear Regulator ADP1740/ADP1741 NC = NO CONNECT Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V APPLICATIONS VIN = 1.8V VOUT = 0.5V(1 + R1/R2) 4.7µF 4.7µF 16 IN 1 IN 100kΩ 15 IN 13 14 OUT OUT OUT 12 PIN 1 INDICATOR 2 IN ADP1741 R1 OUT 11 TOP VIEW OUT 10 (Not to Scale) 3 IN ADJ 9 4 EN PG 5 GND SS 7 6 NC 8 R2 10nF NC = NO CONNECT 07081-002 Notebook computers Memory components Telecommunications equipment Network equipment DSP/FPGA/microprocessor supplies Instrumentation equipment/data acquisition systems Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.0 V GENERAL DESCRIPTION The ADP1740/ADP1741 are CMOS, low dropout linear regulators that operate from 1.6 V to 3.6 V and provide up to 2 A of output current. Using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient response with a small 4.7 μF ceramic output capacitor. The ADP1740 is available in seven fixed output voltage options. The ADP1741 is an adjustable output voltage version, which allows output voltages that range from 0.75 V to 3.0 V via an external divider. The ADP1740/ADP1741 allow an external soft start capacitor to be connected to program the start-up. The ADP1740/ADP1741 are available in a 16-lead, 4 mm × 4 mm LFCSP, making them very compact solutions while providing excellent thermal performance for applications requiring up to 2 A of output current in a small, low profile footprint. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADP1740/ADP1741 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Applications....................................................................................... 1 Thermal Resistance .......................................................................5 Typical Application Circuits............................................................ 1 ESD Caution...................................................................................5 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................6 Specifications..................................................................................... 3 Rev. PrA | Page 2 of 6 Preliminary Technical Data ADP1740/ADP1741 SPECIFICATIONS VIN = (VOUT + 0.4 V) or 1.8 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 μF, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND SHUTDOWN CURRENT IGND-SD OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy (ADP1740) VOUT Adjustable Output Voltage Accuracy (ADP1741)1 VOUT LINE REGULATION ∆VOUT/∆VIN LOAD REGULATION2 DROPOUT VOLTAGE3 ∆VOUT/∆IOUT VDROPOUT START-UP TIME4 ADP1740 and ADP1741 CURRENT LIMIT THRESHOLD5 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis PG OUTPUT LOGIC LEVEL PG Output Logic High PG Output Logic Low PG Output Delay from EN Transition Low to High PG OUTPUT THRESHOLD PG Threshold, Output Voltage Falling PG Threshold, Output Voltage Rising EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current SOFT START INPUT Soft Start Current ADJ INPUT BIAS CURRENT (ADP1741) SENSE INPUT BIAS CURRENT OUTPUT NOISE Test Conditions TJ = −40°C to +125°C IOUT = 0 mA IOUT = 100 mA IOUT = 100 mA, TJ = −40°C to +125°C IOUT = 2 A IOUT = 2 A, TJ = −40°C to +125°C EN = GND EN = GND, TJ = −40°C to +125°C Min 1.6 IOUT = 10 mA IOUT = 1 mA to 2 A 1 mA < IOUT < 2 A, TJ = −40°C to +125°C IOUT = 10 mA IOUT = 1 mA to 2 A 1 mA < IOUT < 2 A, TJ = −40°C to +125°C VIN = (VOUT + 0.4 V) to 3.6 V, TJ = −40°C to +125°C IOUT = 10 mA to 2 A, TJ = −40°C to +125°C IOUT = 100 mA, VOUT ≥ 1.8 V IOUT = 100 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C IOUT = 2 A, VOUT ≥ 1.8 V IOUT = 2 A, VOUT ≥ 1.8 V, TJ = −40°C to +125°C −1 −1.5 −2.5 0.743 0.739 0.731 −0.1 Typ Max 3.6 1 TBD 3 30 Unit V μA μA μA mA mA μA μA 0.75 +1 +1.5 +2.5 0.758 0.761 0.769 +0.1 % % % V V V %/V TBD 40 %/mA mV mV 350 mV mV TBD ms A 45 500 TBD 1.3 15 200 tSTART-UP CSS = 10 nF, IOUT = 10 mA ILIMIT TBD TSSD TSSD-HYS TJ rising PGHIGH PGLOW 1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 μA 1.6 V ≤ VIN ≤ 3.6 V, IOL <2 mA 1.6 V ≤ VIN ≤ 3.6 V, CSS = 10 nF PGFALL PGRISE 1.6 V ≤ VIN ≤ 3.6 V 1.6 V ≤ VIN ≤ 3.6 V VIH VIL VI-LEAKAGE 1.6 V ≤ VIN ≤ 3.6 V 1.6 V ≤ VIN ≤ 3.6 V EN = IN or GND 1.0 ISS ADJI-BIAS SNSI-BIAS OUTNOISE 1.6 V ≤ VIN ≤ 3.6 V 1.6 V ≤ VIN ≤ 3.6 V 1.6 V ≤ VIN ≤ 3.6 V 10 Hz to 100 kHz, VOUT = 0.75 V 10 Hz to 100 kHz, VOUT = 2.5V TBD Rev. PrA | Page 3 of 6 4.8 3 °C °C 150 15 1.0 0.4 TBD −10 −7 0.1 1 30 10 40 80 V V ms % % 0.4 1 TBD 100 V V μA μA nA μA μV rms μV rms ADP1740/ADP1741 Parameter POWER SUPPLY REJECTION RATIO Preliminary Technical Data Symbol PSRR Test Conditions 1 kHz, VOUT = 0.75 V, IOUT = 10 mA 1 kHz, VOUT = 2.5 V, IOUT = 10 mA 10 kHz, VOUT = 0.75 V, IOUT = 10 mA 10 kHz, VOUT = 2.5 V, IOUT = 10 mA 1 Min Typ 70 60 TBD TBD Max Unit dB dB dB dB Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. Based on an end-point calculation using 10 mA and 2 A loads. 3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 1.6 V. 4 Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value. 5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. 2 Rev. PrA | Page 4 of 6 Preliminary Technical Data ADP1740/ADP1741 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter IN to GND OUT to GND EN to GND SS to GND PG to GND SENSE/ADJ to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating −0.3 V to +3.6 V −0.3 V to IN −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +3.6 V −65°C to +150°C −40°C to +125°C JEDEC J-STD-020 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 16-Lead LFCSP with Exposed Pad ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrA | Page 5 of 6 θJA 38 Unit °C/W ADP1740/ADP1741 Preliminary Technical Data 9 SENSE EN 4 PG 5 NC = NO CONNECT 14 OUT NC = NO CONNECT Figure 3. ADP1740 Pin Configuration 13 OUT TOP VIEW (Not to Scale) 12 OUT 11 OUT 10 OUT 9 ADJ 07081-004 IN 3 SS 7 10 OUT ADP1741 NC 8 IN 2 15 IN 16 IN 11 OUT PIN 1 INDICATOR GND 6 IN 1 07081-003 14 OUT SS 7 12 OUT NC 8 TOP VIEW (Not to Scale) PG 5 EN 4 ADP1740 GND 6 IN 3 13 OUT 16 IN PIN 1 INDICATOR IN 1 IN 2 15 IN PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADP1741 Pin Configuration Table 4. Pin Function Descriptions ADP1740 1, 2, 3, 15, 16 Pin No. ADP1741 1, 2, 3, 15, 16 Mnemonic IN 4 4 EN 5 5 PG 6 7 8 9 6 7 8 N/A GND SS NC SENSE N/A 10, 11, 12, 13, 14 9 10, 11, 12, 13, 14 ADJ OUT EP EP Description Regulator Input Supply. Bypass IN to GND with a 4.7 μF or greater capacitor. Note that all five pins must be connected to source Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to IN. Power Good. This open-drain output requires an external pull-up resistor to IN. If part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output voltage, PG immediately transitions low. Ground. Soft Start. A capacitor connected to this pin determines the soft start time. Not connected. No internal connection Sense. Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. Adjust. A resistor divider from OUT to ADJ sets the output voltage. Regulated Output Voltage. Bypass OUT to GND with a 4.7 μF or greater capacitor. Note that all five pins must be connected to load Exposed pad on the bottom of the LFCSP package. EP enhances thermal performance and is electrically connected to GND inside the package. It is recommended to connect EP to the ground plane on the board. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07081-0-11/07(PrA) Rev. PrA | Page 6 of 6