1CY7C225A CY7C225A 512 x 8 Registered PROM Features • Capable of withstanding greater than 2001V static discharge • CMOS for optimum speed/power • High speed — 25 ns address set-up Functional Description The CY7C225A is a high-performance 512-word by 8-bit electrically programmable read only memory packaged in a slim 300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, and 28-pin PLCC. The memory cells utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms. — 12 ns clock to output • Low power — 495 mW (Commercial) — 660 mW (Military) Synchronous and asynchronous output enables On-chip edge-triggered registers Buffered common PRESET and CLEAR inputs EPROM technology, 100% programmable Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or 28-pin PLCC • 5V ±10% VCC, commercial and military • TTL-compatible I/O • Direct replacement for bipolar PROMs The CY7C225A replaces bipolar devices and offers the advantages of lower power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet AC specification limits. • • • • • Logic Block Diagram Pin Configurations DIP Top View A0 O7 A1 O6 A2 ROW ADDRESS PROGRAMMABLE ARRAY MULTIPLEXER O5 A3 8-BIT EDGETRIGGERED REGISTER A4 A5 ADDRESS DECODER O4 O3 A6 A7 O2 COLUMN ADDRESS A7 1 24 VCC A6 2 23 A8 A5 3 22 PS A4 4 21 E A3 5 20 A2 6 19 CLR ES A1 7 18 CP A0 8 17 O7 O0 9 16 O6 O1 10 15 O5 O2 11 14 O4 GND 12 13 O3 O1 A8 S R LCC/PLCC Top View O0 CP A5 A6 A7 NC VCC A8 PS PS CLR CP A4 A3 A2 A1 A0 NC O0 ES E CLR ES CP NC O7 O6 O1 O2 GND NC O3 O4 O5 E 4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 13 141516 17 18 Selection Guide 7C225A-25 7C225A-30 7C225A-40 Unit Minimum Address Set-Up Time 25 30 40 ns Maximum Clock to Output 12 15 25 90 90 Maximum Operating Current Commercial Military Cypress Semiconductor Corporation Document #: 38-04001 Rev. *B 120 • 3901 North First Street • San Jose ns mA • mA CA 95134 • 408-943-2600 Revised October 8, 2002 CY7C225A Maximum Ratings[1] DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Commercial Military[2] DC Input Voltage .................................................−3.0V to +7.0V Ambient Temperature VCC 0°C to +70°C 5V ± 10% −55°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range[3,4] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VIN = VIH or VIL VOL Output LOW Voltage VCC = Min., IOL = 16 mA VIN = VIH or VIL VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs IIX Input Leakage Current GND < VIN < VCC VCD Input Clamp Diode Voltage Note 4 IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled[5] IOS Output Short Circuit Current VCC = Max., VOUT = ICC Power Supply Current IOUT = 0 mA VCC = Max. VPP Programming Supply Voltage IPP Programming Supply Current VIHP Input HIGH Programming Voltage VILP Input LOW Programming Voltage Min. Max. Unit 2.4 V 0.4 V 2.0 V 0.8 V −10 +10 µA −10 +10 µA −20 −90 mA Commercial 90 mA Military 120 0.0V[6] 12 13 V 50 mA 3.0 V 0.4 V Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC =5.0V Max. Unit 10 pF 10 pF Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing. 5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: 38-04001 Rev. *B Page 2 of 9 CY7C225A AC Test Loads and Waveforms[4] R1 250Ω 5V R1 250Ω 5V OUTPUT ALL INPUT PULSES OUTPUT 50 pF R2 167Ω INCLUDING JIG AND SCOPE 5pF INCLUDING JIG AND SCOPE (a) NormalLoad Equivalent to: 3.0V R2 167Ω GND < 5 ns 90% 10% 90% 10% < 5 ns (b) High Z Load THÉVENIN EQUIVALENT OUTPUT 100Ω 2.0V Operating Modes The CY7C225A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with synchronous (ES) and asynchronous (E) output enables and CLEAR and PRESET inputs. Upon power-up, the synchronous enable (ES) flip-flop will be in the set condition causing the outputs (O0−O7) to be in the OFF or high-impedance state. Data is read by applying the memory location to the address inputs (A0−A8) and a logic LOW to the enable (ES) input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O0−O7) provided the asynchronous enable (E) is also LOW. The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. Regardless of the condition of E, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable (ES) input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, Document #: 38-04001 Rev. *B the subsequent positive clock edge will return the output to the active state if E is LOW. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C225A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market. The CY7C225A has buffered asynchronous CLEAR and PRESET inputs. Applying a LOW to the PRESET input causes an immediate load of all ones into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). Applying a LOW to the CLEAR input, resets the flip-flops to all zeros. The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. When power is applied, the (internal) synchronous enable flip-flop will be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur and the ES input pin must be LOW at least a set-up time prior to the clock LOW-to-HIGH transition. The E input may then be used to enable the outputs. Page 3 of 9 CY7C225A Switching Characteristics Over the Operating Range[3,4] 7C225A-25 Parameter Description Min. Max. 7C225A-30 Min. Max. 7C225A-40 Min. Max. Unit tSA Address Set-Up to Clock HIGH 25 30 40 ns tHA Address Hold from Clock HIGH 0 0 0 ns tCO Clock HIGH to Valid Output tPWC Clock Pulse Width 10 15 20 ns tSES ES Set-Up to Clock HIGH 10 10 10 ns tHES ES Hold from Clock HIGH 0 5 5 ns tDP, tDC Delay from PRESET or CLEAR to Valid Output tRP, tRC PRESET or CLEAR Recovery to Clock HIGH 15 20 20 ns tPWP, tPWC PRESET or CLEAR Pulse Width 15 20 20 ns tCOS Valid Output from Clock HIGH[7] 20 20 30 ns tHZC Inactive Output from Clock HIGH[7] 20 20 30 ns tDOE Valid Output from E LOW 20 20 30 ns tHZE Inactive Output from E HIGH 20 20 30 ns 12 15 20 25 20 20 ns ns Note: 7. Applies only when the synchronous (ES) function is used. Switching Waveforms[4] tHA tSA tHA tHES tSES tHES A0 − A10 tSES ES tSES tHES tPWC CP tPWC tPWC O0 − O7 tCO tHZC tPWC tPWC tCOS tPWC tCO tHZE tDOE E tDP tDC tRP, tRC PS or CLR tPWP tPWC Document #: 38-04001 Rev. *B Page 4 of 9 CY7C225A Programming Information Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Table 1. Mode Selection Pin Function[8] Read or Output Disable A8–A0 CP ES CLR E PS O7−O0 Other A8–A0 PGM VFY VPP E PS D7−D0 Read A8–A0 X VIL VIH VIL VIH O7−O0 Output Disable A8–A0 X VIH VIH X VIH High Z Output Disable A8–A0 X X VIH VIH VIH High Z Clear A8–A0 X VIL VIL VIL VIH Zeros Preset A8–A0 X VIL VIH VIL VIL Ones Program A8–A0 VILP VIHP VPP VIHP VIHP D7−D0 Program Verify A8–A0 VIHP VILP VPP VIHP VIHP O7−O0 Program Inhibit A–A0 VIHP VIHP VPP VIHP VIHP High Z Intelligent Program A8–A0 VILP VIHP VPP VIHP VIHP D7−D0 Blank Check A8–A0 VIHP VILP VPP VIHP VIHP Zeros Mode Note: 8. X = “don’t care” but not to exceed VCC ±5%. 1 24 VCC 2 3 A8 PS A4 A3 A2 4 23 22 21 5 6 20 19 VPP A1 A0 7 8 9 10 11 12 18 PGM 17 16 D7 D6 15 D5 14 D4 D3 A5 D0 D1 D2 GND 13 E VFY A4 A3 A2 A1 A0 NC D0 4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18 E VPP VFY PGM NC D7 D6 D1 D2 GND NC D3 D4 D5 A7 A6 LCC/PLCC Top View A5 A6 A7 NC VCC A8 PS DIP Top View Figure 1. Programming Pinouts Document #: 38-04001 Rev. *B Page 5 of 9 CY7C225A Typical DC and AC Characteristics 1.4 1.2 1.0 TA =25°C f = fMAX 0.8 0.6 4.0 4.5 5.0 5.5 1.1 1.0 0.9 0.8 −55 6.0 1.0 0.8 1.0 0.8 0.6 TA =25°C 0.4 4.0 125 1.02 4.5 5.0 5.5 VCC =5.5V TA =25°C DELTA t AA (ns) 0.94 0.92 20.0 15.0 10.0 TA =25°C VCC =4.5V 5.0 0.90 25 50 75 CLOCK PERIOD (ns) Document #: 38-04001 Rev. *B 100 0.0 0 5.0 5.5 6.0 1.4 1.2 1.0 0.8 200 400 600 800 1000 CAPACITANCE (pF) 125 25 AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 25.0 0.96 4.5 0.6 –55 6.0 30.0 0 TA =25°C 0.6 4.0 SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD 0.98 0.8 1.6 NORMALIZED SET -UP 1.2 1.00 1.0 NORMALIZED SET-UP TIME vs. TEMPERATURE OUTPUT SINK CURRENT (mA) 1.4 25 1.2 SUPPLY VOLTAGE (V) 1.2 1.6 0.6 −55 1.4 NORMALIZED SET-UP TIME vs. SUPPLY VOLTAGE NORMALIZED SET-UP TIME NORMALIZED CLOCK- TO-OUTPUT TIME CLOCK TO OUTPUT TIME vs. TEMPERATURE AMBIENT TEMPERATURE (°C) NORMALIZED ICC 125 1.6 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0.88 25 NORMALIZEDOCK– CL TO–OUTPUT TIME 1.2 NORMALIZED ICC NORMALIZED ICC 1.6 CLOCK TO OUTPUT TIME vs. VCC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 175 150 125 100 75 VCC =5.0V TA =25°C 50 25 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Page 6 of 9 CY7C225A Ordering Information Speed (ns) Ordering Code Package Type Package Type tSA tCO 25 12 CY7C225A-25PC P13 24-Lead (300-Mil) Molded DIP 30 15 CY7C225A-30JC J64 28-Lead Plastic Leaded Chip Carrier 40 25 CY7C225A-40LMB L64 28-Square Leadless Chip Carrier Operating Range Commercial MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups VOH 1, 2, 3 tSA 7, 8, 9, 10, 11 VOL 1, 2, 3 tHA 7, 8, 9, 10, 11 VIH 1, 2, 3 tCO 7, 8, 9, 10, 11 VIL 1, 2, 3 tDP 7, 8, 9, 10, 11 IIX 1, 2, 3 tRP 7, 8, 9, 10, 11 IOZ 1, 2, 3 ICC 1, 2, 3 Package Diagrams 28-Lead Plastic Leaded Chip Carrier J64 51-85001-*A Document #: 38-04001 Rev. *B Page 7 of 9 CY7C225A Package Diagrams (Continued) 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 51-80051-** 24-Lead (300-Mil) Molded DIP P13 51-85013-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-04001 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C225A Document History Page Document Title: CY7C225A 512 x 8 Registered PROM Document Number: 38-04001 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 113858 03/06/02 DSG Change from Spec number: 38-00228 to 38-04001 *A 118892 10/09/02 GBI Update ordering information *B 122242 12/27/02 RBI Add power up requirements to Maximum ratings information Document #: 38-04001 Rev. *B Page 9 of 9