LINER 1469

LT1469
Dual 90MHz, 22V/µs
16-Bit Accurate Operational Amplifier
FEATURES
DESCRIPTION
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The LT®1469 is a dual, precision high speed operational
amplifier with 16-bit accuracy and 900ns settling to 150μV
for 10V steps. This unique blend of precision and AC
performance makes the LT1469 the optimum choice for
high accuracy applications such as DAC current-to-voltage
conversion and ADC buffers. The initial accuracy and drift
characteristics of the input offset voltage and inverting input
bias current are tailored for inverting applications.
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90MHz Gain Bandwidth, f = 100kHz
Maximum Input Offset Voltage: 125μV
Settling Time: 900ns (AV = –1, 150μV, 10V Step)
22V/μs Slew Rate
Low Distortion: –96.5dB for 100kHz, 10VP-P
Maximum Input Offset Voltage Drift: 3μV/°C
Maximum Inverting Input Bias Current: 10nA
Minimum DC Gain: 300V/mV
Minimum Output Swing into 2k: ±12.8V
Unity-Gain Stable
Input Noise Voltage: 5nV/√Hz
Input Noise Current: 0.6pA/√Hz
Total Input Noise Optimized for 1kΩ < RS < 20kΩ
Specified at ±5V and ±15V Supplies
APPLICATIONS
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Precision Instrumentation
High Accuracy Data Acquisition Systems
16-Bit DAC Current-to-Voltage Converter
ADC Buffer
Low Distortion Active Filters
Photodiode Amplifiers
The 90MHz gain bandwidth ensures high open-loop gain
at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and
DC accuracy allow full 16-bit AC and DC performance.
The 22V/μs slew rate of the LT1469 improves large signal
performance compared to other precision op amps in
applications such as active filters and instrumentation
amplifiers.
The LT1469 is available in a space saving 4mm × 4mm
leadless package, as well as in small outline and DIP packages. A single version, the LT1468, is also available.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
16-Bit DAC I-to-V Converter and Reference Inverter for Bipolar Output Swing (VOUT = –10V to 10V)
15V
Bipolar Multiplying Mode (LTC1597)
Signal-to-(Noise + Distortion)
VREF
+
2.4μs SETTLING TIME
TO 1LSB ON 20V STEP
–
15pF
15pF
12k
16 BITS
DAC INPUTS
12k
12k
LTC1597
12k
–
RLPF
1/2 LT1469
+
VOUT
CLPF
SIGNAL/(NOISE + DISTORTION) (dB)
40
1/2 LT1469
DAC INPUT CODE = ALL ZEROS
VREF = 20VP-P
50
60
70
80
500kHz FILTER
90
100
80kHz FILTER
30kHz
FILTER
110
10
–15V
1469 TA01
100
1k
10k
FREQUENCY (Hz)
100k
1469 TA01a
1469fa
1
LT1469
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V + to V–).................................36V
Input Current (Note 2)..........................................±10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4).... –40°C to 85°C
Specified Temperature Range (Note 5) .... –40°C to 85°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
S8 and N8 Package ........................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
12 V+
OUT A
1
–IN A
2
+IN A
3
V–
4
N/C
5
8 N/C
N/C
6
7 N/C
B
13
8
V+
7
OUT B
6
–IN B
4
5
+IN B
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
OUT A 1
11 OUT B
A
10 –IN B
–IN A 2
9 +IN B
+IN A 3
A
V–
DF PACKAGE
12-LEAD (4mm × 4mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) MUST BE CONNECTED TO V–
B
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 150°C, θJA = 190°C/W (S8)
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1469CN8#PBF
NA
LT1469CN8
8-Lead PDIP
0°C to 70°C
LT1469IN8#PBF
NA
LT1469IN8
8-Lead PDIP
–40°C to 85°C
LT1469CS8#PBF
LT1469CS8#TRPBF
1469
8-Lead Plastic Small Outline
0°C to 70°C
LT1469IS8#PBF
LT1469IS8#TRPBF
1469I
8-Lead Plastic Small Outline
–40°C to 85°C
LT1469ACDF#PBF
LT1469ACDF#TRPBF
1469
12-Lead (4mm × 4mm) Plastic DFN
0°C to 70°C
LT1469AIDF#PBF
LT1469AIDF#TRPBF
1469
12-Lead (4mm × 4mm) Plastic DFN
–40°C to 85°C
LT1469CDF#PBF
LT1469CDF#TRPBF
1469
12-Lead (4mm × 4mm) Plastic DFN
0°C to 70°C
LT1469IDF#PBF
LT1469IDF#TRPBF
1469
12-Lead (4mm × 4mm) Plastic DFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1469CN8
NA
LT1469CN8
8-Lead PDIP
0°C to 70°C
LT1469IN8
NA
LT1469IN8
8-Lead PDIP
–40°C to 85°C
LT1469CS8
LT1469CS8#TR
1469
8-Lead Plastic Small Outline
0°C to 70°C
LT1469IS8
LT1469IS8#TR
1469I
8-Lead Plastic Small Outline
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1469fa
2
LT1469
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
N8, S8 Packages
VSUPPLY
MIN
TYP
MAX
UNITS
±15V
±5V
50
50
125
200
μV
μV
LT1469A, DF Package
±15V
±5V
50
50
125
200
μV
μV
LT1469, DF Package
±15V
±5V
100
150
225
300
μV
μV
IOS
Input Offset Current
±5V to ±15V
13
±50
nA
IB –
Inverting Input Bias Current
±5V to ±15V
3
±10
nA
IB +
Noninverting Input Bias Current
±40
±5V to ±15V
–10
Input Noise Voltage
0.1Hz to 10Hz
±5V to ±15V
0.3
nA
μVP-P
en
Input Noise Voltage Density
f = 10kHz
±5V to ±15V
5
nV/√Hz
in
Input Noise Current Density
f = 10kHz
±5V to ±15V
0.6
pA/√Hz
RIN
Input Resistance
Common Mode, VCM = ±12.5V
Differential
240
150
MΩ
kΩ
CIN
Input Capacitance
4
pF
VCM
Input Voltage Range (Positive)
Guaranteed by CMRR
±15V
±5V
13.5
3.6
V
V
Input Voltage Range (Negative)
Guaranteed by CMRR
±15V
±5V
Common Mode Rejection Ratio
VCM = ±12.5V
VCM = ±2.5V
±15V
±5V
Minimum Supply Voltage
Guaranteed by PSRR
CMRR
±15V
±15V
100
50
±15V
12.5
2.5
–14.3
–4.4
96
96
–12.5
–2.5
110
112
±2.5
V
V
dB
dB
±4.5
V
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±15V
100
112
dB
AVOL
Large-Signal Voltage Gain
VOUT = ±12.5V, RL = 10k
VOUT = ±12.5V, RL = 2k
VOUT = ±2.5V, RL = 10k
VOUT = ±2.5V, RL = 2k
±15V
±15V
±5V
±5V
300
300
200
200
2000
2000
8000
8000
V/mV
V/mV
V/mV
V/mV
VOUT
Maximum Output Swing
RL = 10k, 1mV Overdrive
RL = 2k, 1mV Overdrive
RL = 10k, 1mV Overdrive
RL = 2k, 1mV Overdrive
±15V
±15V
±5V
±5V
±13.0
±12.8
±3.0
±2.8
±13.6
±13.5
±3.7
±3.6
V
V
V
V
IOUT
Maximum Output Current
VOUT = ±12.5V, 1mV Overdrive
VOUT = ±2.5V, 1mV Overdrive
±15V
±5V
±15
±15
±22
±22
mA
mA
ISC
Output Short-Circuit Current
VOUT = 0V, 0.2V Overdrive (Note 3)
±15V
±25
±40
mA
SR
Slew Rate
AV = –10, RL = 2k (Note 6)
±15V
±5V
15
11
22
17
V/μs
V/μs
FPBW
Full-Power Bandwidth
10V Peak, (Note 7)
3V Peak, (Note 7)
±15V
±5V
350
900
kHz
kHz
GBW
Gain Bandwidth Product
f = 100kHz, RL = 2k
±15V
±5V
90
88
MHz
MHz
tr, tf
Rise Time, Fall Time
AV = 1, 10% to 90%, 0.1V Step
±15V
±5V
11
12
ns
ns
OS
Overshoot
AV = 1, 0.1V Step
±15V
±5V
30
35
%
%
tPD
Propagation Delay
AV = 1, 50% VIN to 50% VOUT, 0.1V Step
±15V
±5V
9
10
ns
ns
60
55
1469fa
3
LT1469
ELECTRICAL CHARACTERISTICS
TA = 25°C. VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VSUPPLY
MIN
TYP
MAX
UNITS
tS
Settling Time
10V Step, 0.01%, AV = –1
10V Step, 150μV, AV = –1
5V Step, 0.01%, AV = –1
±15V
±15V
±5V
760
900
770
ns
ns
ns
THD
Total Harmonic Distortion
AV = –1, VOUT = 10VP-P, f = 100kHz
AV = 1, VOUT = 20VP-P, f = 1kHz
±15V
±15V
–96.5
–125
dB
dB
Output Resistance
AV = 1, f = 100kHz
±15V
Channel Separation
VOUT = ±12.5V, RL = 2k
VOUT = ±2.5V, RL = 2k
±15V
±5V
IS
Supply Current
Per Amplifier
±15V
±5V
4.1
3.8
5.2
5
mA
mA
ΔVOS
Input Offset Voltage Match
S8, DF A-Grade
±15V
±5V
30
50
225
350
μV
μV
ΔIB–
Inverting Input Bias Current Match
±5V to ±15V
2
18
nA
ΔIB+
Noninverting Input Bias Current Match
±5V to ±15V
5
78
nA
ΔCMRR
Common Mode Rejection Match
VCM = ±12.5V (Note 9)
VCM = ±2.5V (Note 9)
ΔPSRR
Power Supply Rejection Match
VS = ±4.5V to ±15V (Note 9)
ROUT
±15V
±5V
100
100
0.02
Ω
130
130
dB
dB
93
93
113
115
dB
dB
97
115
dB
The l denotes the specifications which apply over the full operating temperature range, 0°C ≤ TA ≤ 70°C. VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
N8, S8 Packages
±15V
±5V
LT1469A, DF Package
ΔVOS/ΔT
Input Offset Voltage Drift
IOS
Input Offset Current
ΔIOS/ΔT
Input Offset Current Drift
IB –
Inverting Input Bias Current
ΔIB–/ΔT
Inverting Input Bias Current Drift
MAX
UNITS
●
●
350
350
μV
μV
±15V
±5V
●
●
225
275
μV
μV
LT1469, DF Package
±15V
±5V
●
●
450
450
μV
μV
(Note 8)
±15V
±5V
●
●
±5V to ±15V
●
±5V to ±15V
●
±5V to ±15V
●
±5V to ±15V
●
(Note 8)
(Note 8)
VSUPPLY
MIN
TYP
1
1
5
3
±80
60
μV/°C
μV/°C
nA
pA/°C
±20
40
nA
pA/°C
IB +
Noninverting Input Bias Current
±5V to ±15V
●
VCM
Input Voltage Range (Positive)
Guaranteed by CMRR
±15V
±5V
●
●
Input Voltage Range (Negative)
Guaranteed by CMRR
±15V
±5V
●
●
VCM = ±12.5V
±15V
●
94
dB
VCM = ±2.5V
±5V
●
94
dB
CMRR
Common Mode Rejection Ratio
Minimum Supply Voltage
Power Supply Rejection Ratio
VS = ±4.5V to ±15V
AVOL
Large-Signal Voltage Gain
VOUT = ±12.5V, RL = 10k
VOUT = ±12.5V, RL = 2k
VOUT = ±2.5V, RL = 10k
VOUT = ±2.5V, RL = 2k
±15V
±15V
±5V
±5V
nA
V
V
–12.5
–2.5
●
Guaranteed by PSRR
PSRR
±60
12.5
2.5
± 4.5
V
V
V
●
95
dB
●
●
●
●
100
100
100
100
V/mV
V/mV
V/mV
V/mV
1469fa
4
LT1469
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, 0°C ≤ TA ≤ 70°C. VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOUT
Maximum Output Swing
RL = 10k, 1mV Overdrive
RL = 2k, 1mV Overdrive
RL = 10k, 1mV Overdrive
RL = 2k, 1mV Overdrive
VSUPPLY
±15V
±15V
±5V
±5V
●
●
●
●
±12.9
±12.7
±2.9
±2.7
MIN
TYP
MAX
UNITS
V
V
V
V
IOUT
Maximum Output Current
VOUT = ±12.5V, 1mV Overdrive
VOUT = ±2.5V, 1mV Overdrive
±15V
±5V
●
●
±12.5
±12.5
mA
mA
ISC
Output Short-Circuit Current
VOUT = 0V, 0.2V Overdrive
(Note 3)
±15V
●
±17
mA
SR
Slew Rate
AV = –10, RL = 2k (Note 6)
±15V
±5V
●
●
13
9
V/μs
V/μs
GBW
Gain Bandwidth Product
f = 100kHz, RL = 2k
±15V
±5V
●
●
55
50
MHz
MHz
Channel Separation
VOUT = ±12.5V, RL = 2k
VOUT = ±2.5V, RL = 2k
±15V
±5V
●
●
98
98
dB
dB
IS
Supply Current
Per Amplifier
±15V
±5V
●
ΔVOS
Input Offset Voltage Match
S8, DF A-Grade
±15V
±5V
ΔIB –
Inverting Input Bias Current Match
ΔIB +
Noninverting Input Bias Current Match
ΔCMRR
Common Mode Rejection Match
VCM = ±12.5V (Note 9)
VCM = ±2.5V (Note 9)
ΔPSRR
Power Supply Rejection Match
VS = ±4.5V to ±15V (Note 9)
6.5
6.3
mA
mA
●
●
600
600
μV
μV
±5V to ±15V
●
38
nA
±5V to ±15V
●
118
nA
±15V
±5V
●
●
91
91
dB
dB
●
92
dB
●
The l denotes the specifications which apply over the full operating temperature range, –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise
noted. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
N8, S8 Packages
±15V
±5V
LT1469A, DF Package
ΔVOS/ΔT
Input Offset Voltage Drift
IOS
Input Offset Current
ΔIOS/ΔT
Input Offset Current Drift
IB –
Inverting Input Bias Current
ΔIB–/ΔT
Inverting Input Bias Current Drift
MAX
UNITS
●
●
500
500
μV
μV
±15V
±5V
●
●
300
350
μV
μV
LT1469, DF Package
±15V
±5V
●
●
600
600
μV
μV
(Note 8)
±15V
±5V
●
●
±5V to ±15V
●
(Note 8)
(Note 8)
VSUPPLY
MIN
±5V to ±15V
●
±5V to ±15V
●
±5V to ±15V
●
IB +
Noninverting Input Bias Current
±5V to ±15V
●
VCM
Input Voltage Range (Positive)
Guaranteed by CMRR
±15V
±5V
●
●
Input Voltage Range (Negative)
Guaranteed by CMRR
±15V
±5V
●
●
TYP
1
1
6
5
±120
120
μV/°C
μV/°C
nA
pA/°C
±40
80
nA
pA/°C
±80
12.5
2.5
nA
V
V
–12.5
–2.5
V
V
1469fa
5
LT1469
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VSUPPLY
CMRR
Common Mode Rejection Ratio
VCM = ±12.5V
VCM = ±2.5V
±15V
±5V
MIN
●
●
92
92
TYP
MAX
UNITS
±4.5
dB
dB
Minimum Supply Voltage
Guaranteed by PSRR
●
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±15V
●
93
dB
AVOL
Large-Signal Voltage Gain
VOUT = ±12,5V, RL = 10k
VOUT = ±12.5V, RL = 2k
VOUT = ±2.5V, RL = 10k
VOUT = ±2.5V, RL = 2k
±15V
±15V
±5V
±5V
●
●
●
●
75
75
75
75
V/mV
V/mV
V/mV
V/mV
VOUT
Maximum Output Swing
RL = 10k, 1mV Overdrive
RL = 2k, 1mV Overdrive
RL = 10k, 1mV Overdrive
RL = 2k, 1mV Overdrive
±15V
±15V
±5V
±5V
●
●
●
●
±12.8
±12.6
±2.8
±2.6
IOUT
Maximum Output Current
VOUT = ±12.5V, 1mV Overdrive
VOUT = ±2.5V, 1mV Overdrive
±15V
±5V
●
●
±7
±7
mA
mA
ISC
Output Short-Circuit Current
VOUT = 0V, 0.2V Overdrive (Note 3)
±15V
●
±12
mA
SR
Slew Rate
AV = –10, RL = 2k (Note 6)
±15V
±5V
●
●
9
6
V/μs
V/μs
GBW
Gain Bandwidth Product
f = 100kHz, RL = 2k
±15V
±5V
●
●
45
40
MHz
MHz
Channel Separation
VOUT = ±12.5V, RL = 2k
VOUT = ±2.5V, RL = 2k
±15V
±5V
●
●
96
96
dB
dB
IS
Supply Current
Per Amplifier
±15V
±5V
●
●
7
6.8
mA
mA
ΔVOS
Input Offset Voltage Match
S8, DF A-Grade
±15V
±5V
●
●
800
800
μV
μV
ΔIB –
Inverting Input Bias Current Match
±5V to ±15V
●
78
nA
ΔIB +
Noninverting Input Bias Current
Match
±5V to ±15V
●
158
nA
ΔCMRR
Common Mode Rejection Match
VCM = ±12.5V (Note 9)
VCM = ±2.5V (Note 9)
±15V
±5V
●
●
89
89
dB
dB
ΔPSRR
Power Supply Rejection Match
VS = ±4.5V to ±15V (Note 9)
●
90
dB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by back-to-back diodes and two 100Ω
series resistors. If the differential input voltage exceeds 0.7V, the input
current should be limited to less than 10mA. Input voltages outside the
supplies will be clamped by ESD protection devices and input currents
should also be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Note 4: The LT1469C and LT1469I are guaranteed functional over the
operating temperature range of – 40°C to 85°C.
V
V
V
V
V
Note 5: The LT1469C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet specified
performance from –40°C to 85°C but is not tested or QA sampled at these
temperatures. The LT1469I is guaranteed to meet specified performance
from –40°C to 85°C.
Note 6: Slew rate is measured between ±8V on the output with ±12V
swing for ±15V supplies and ±2V on the output with ±3V swing for ±5V
supplies.
Note 7: Full-power bandwidth is calculated from the slew rate. FPBW =
SR/2πVP.
Note 8: This parameter is not 100% tested.
Note 9: ΔCMRR and ΔPSRR are defined as follows: 1) CMRR and PSRR
are measured in μV/V on each amplifier; 2) the difference between the two
sides is calculated in μV/V; 3) the result is converted to dB.
1469fa
6
LT1469
TYPICAL PERFORMANCE CHARACTERISTICS
Distribution of Input Offset
Voltage
Distribution of Inverting Input
Bias Current
40
50
6
VS = ±15V
TA = 25°C
30
20
10
0
–175 –125 –75 –25 25
75 125
INPUT OFFSET VOLTAGE (μV)
85°C
5
30
SUPPLY CURRENT (mA)
40
PERCENTAGE OF UNITS (%)
PERCENTAGE OF UNITS (%)
VS = ±15V
TA = 25°C
20
10
0
–10 –7.5 –5 –2.5 0 2.5 5 7.5
INVERTING INPUT BIAS CURRENT (nA)
175
10
0.1
100
1k
FREQUENCY (Hz)
100
VS = ±15V
TA = 25°C
f = 10kHz
TOTAL
NOISE
10
RESISTOR
NOISE ONLY
1
RS
+
–
0.1
0.01
100k
10k
TIME (1s/DIV)
10
1469 G05
100
1k
10k
SOURCE RESISTANCE, RS (Ω)
Input Bias Current
vs Temperature
Input Bias Current
vs Input Common Mode Voltage
30
INPUT BIAS CURRENT (nA)
INPUT BIAS CURRENT (nA)
IB–
–10
IB+
–30
–40
–50 –25
V+
VS = ±15V
TA = 25°C
40
20
IB–
0
IB+
–20
–40
–60
50
25
75
0
TEMPERATURE (°C)
100
125
1469 G07
–80
–15
TA = 25°C
ΔVOS < 100μV
–0.5
COMMON MODE RANGE (V)
60
20
–20
Input Common Mode Range
vs Supply Voltage
80
VS = ±15V
10
100k
1469 G06
1469 G04
0
20
1469 G03
TOTAL NOISE VOLTAGE (nV/√Hz)
en
1
5
10
15
SUPPLY VOLTAGE (±V)
0
Total Noise vs Unmatched
Source Resistance
VOLTAGE NOISE (100nV/DIV)
1
10
1
10
VS = ±15V
TA = 25°C
INPUT CURRENT NOISE (pA/√Hz)
VS = ±15V
TA = 25°C
AV = 101
RS = 100k FOR in
10
1
–40°C
0.1Hz to 10Hz Voltage Noise
1000
in
3
1469 G02
Input Noise Spectral Density
100
25°C
4
2
1469 G01
INPUT VOLTAGE NOISE (nV/√Hz)
Supply Current vs Supply Voltage
and Temperature
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
V–
–10
–5
5
10
0
INPUT COMMON MODE VOLTAGE (V)
15
1469 G08
0
3
9
12
6
SUPPLY VOLTAGE (±V)
15
18
1469 G09
1469fa
7
LT1469
TYPICAL PERFORMANCE CHARACTERISTICS
V+
V+ –0.5
RL = 10k
–1
–1.0
RL = 2k
OUTPUT VOLTAGE SWING (V)
OUTPUT VOLTAGE SWING (V)
Output Voltage Swing
vs Load Current
–2
–3
–4
4
3
2
RL = 2k
1
RL = 10k
TA = 25°C
V–
20
60
VS = ±15V
85°C
25°C
–40°C
–1.5
–2.0
–2.5
2.5
–40°C
2.0
1.5
25°C
85°C
1.0
10
15
5
SUPPLY VOLTAGE (±V)
0
Output Short-Circuit Current
vs Temperature
V– 0.5
–20 –15 –10 –5 0
10
5
OUTPUT CURRENT (mA)
15
1469 G10
6
4
AV = 1
3
OUTPUT STEP (V)
2
0
–2
–4
–6
AV = 1
–8
–10
200
0
VS = ±5V
TA = 25°C
RL = 1k
20
15
0
–1
–2
AV = –1
AV = 1
4
0
–2
–4
–6
400
600
700
500
SETTLING TIME (ns)
–10
800
160
OPEN-LOOP GAIN (dB)
120
115
100
1k
LOAD RESISTANCE (Ω)
10k
1469 G16
TA = 25°C
AV = –1
RF = RG = 5.1k
CF = 5pF
RL = 2k
120
100
140
130
120
1000
140
RL = 2k
VS = ±15V
80
60
VS = ±5V
VS = ±15V
40
110
20
100
110
600
800
400
SETTLING TIME (ns)
Open-Loop Gain
vs Frequency
VS = ±5V
VS = ±15V
200
1469 G15
150
125
0
1469 G14
TA = 25°C
125
100
2
Open-Loop Gain
vs Temperature
130
50
25
0
75
TEMPERATURE (°C)
–8
–5
300
1000
VS = ±5V
–25
VS = ±15V
TA = 25°C
AV = –1
RF = RG = 2k
CF = 8pF
6
–4
135
OPEN-LOOP GAIN (dB)
25
8
AV = –1
AV = 1
1
Open-Loop Gain
vs Resistive Load
10
30
10
1469 G13
140
35
Settling Time to 150μV
vs Output Step
2
–3
AV = –1
600
800
400
SETTLING TIME (ns)
SINK
40
1469 G12
GAIN (dB)
OUTPUT STEP (V)
4
SOURCE
45
Settling Time to 0.01%
vs Output Step, VS = ± 5V
5
AV = –1
50
10
–50
20
OUTPUT STEP (V)
VS = ±15V
TA = 25°C
RL = 1k
8
VS = ±15V
VIN = ±0.2V
55
1469 G11
Settling Time to 0.01%
vs Output Step, VS = ± 15V
10
OUTPUT SHORT-CIRCUIT CURRENT (mA)
Output Voltage Swing
vs Supply Voltage
90
–50 –25
0
50
25
75
0
TEMPERATURE (°C)
100
125
1469 G17
–20
10
100
1k 10k 100k 1M
FREQUENCY (Hz)
10M 100M
1469 G18
1469fa
8
LT1469
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Bandwidth and Phase
Margin vs Supply Voltage
40
80
60
PHASE
60
40
40
±5V
20
30
GAIN
0
20
±15V
TA = 25°C
AV = –1
RF = RG = 5.1k
CF = 5pF
RL = 2k
–10
10k
100k
–20
±5V
–40
1M
10M
FREQUENCY (Hz)
–60
100M
PHASE MARGIN
36
92
34
90
32
86
84
10
5
15
SUPPLY VOLTAGE (±V)
0
Gain vs Frequency, AV = 1
TA = 25°C
AV = 1
RL = 2k
GAIN (dB)
GAIN (dB)
RF = RG = 5.1k
VS = ±5V
VS = ±15V
2
VS = ±15V
0
–1
1
–3
–3
–4
–4
–5
100k
–5
100k
100M
GAIN (dB)
8
6
4
TA = 25°C
AV = –1
RL = 2k
CF = 5pF
TA = 25°C
28 AV = –1
RL = 2k
2
0
–2
100pF
50pF
–4
–6
100k
1M
10M
FREQUENCY (Hz)
100M
1469 G25
100pF
4
20pF
2
10pF
–2
–4
1M
10M
FREQUENCY (Hz)
–6
100k
100M
1M
10M
FREQUENCY (Hz)
Slew Rate vs Temperature
45
40
–SR
VS = ±15V
AV = –1
RL = 2k
35
24
+SR
22
20
–SR
30
25
15
16
10
0
10
5
15
SUPPLY VOLTAGE (±V)
20
1469 G26
+SR
20
18
14
100M
1469 G24
26
200pF
125
50pF
6
Slew Rate vs Supply Voltage
300pF
100
VS = ±15V
TA = 25°C
AV = 1
NO RL
8
30
SLEW RATE (V/μs)
10
50
25
0
75
TEMPERATURE (°C)
1469 G23
Gain vs Frequency, AV = –1
VS = ±15V
TA = 25°C
AV = –1
RF = RG = 5.1k
CF = 5pF
NO RL
–25
0
1469 G22
12
10
–1
–2
14
84
–55
12
0
–2
1M
10M
FREQUENCY (Hz)
VS = ±5V
86
Gain vs Frequency, AV = 1
RF = RG = 2k
VS = ±5V
VS = ±15V
3
2
VS = ±5V
GAIN BANDWIDTH
88
14
4
30
VS = ±15V
90
Gain vs Frequency, AV = – 1
5
1
32
92
1469 G21
GAIN (dB)
3
20
34
94
1469 G20
5
38
36
GAIN BANDWIDTH
82
40
VS = ±15V
VS = ±5V
88
1469 G19
4
PHASE MARGIN
SLEW RATE (V/μs)
0
GAIN BANDWIDTH (MHz)
±15V
PHASE (DEG)
GAIN (dB)
50
38
42
5
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
1469 G27
1469fa
9
PHASE MARGIN (DEG)
TA = 25°C
AV = –1
RF = RG = 5.1k
CF = 5pF
RL = 2k
PHASE MARGIN (DEG)
100
70
10
Gain Bandwidth and Phase
Margin vs Temperature
GAIN BANDWIDTH (MHz)
Open-Loop Gain and Phase vs
Frequency
LT1469
TYPICAL PERFORMANCE CHARACTERISTICS
120
VS = ±15V
TA = 25°C
RL = 2k
140
COMMON MODE REJECTION RATIO (dB)
+PSRR
100
–PSRR
80
60
40
20
0
100
1k
10k
1M
100k
FREQUENCY (Hz)
10M
100
60
40
20
10k
100k 1M
FREQUENCY (Hz)
1k
10M
OUTPUT VOLTAGE SWING (VP-P)
OUTPUT VOLTAGE SWING (VP-P)
AV = 1
6
AV = –1
5
4
3
2
0
10
100
FREQUENCY (kHz)
25
20
AV = –1
15
10
VS = ±15V
TA = 25°C
RL = 2k
THD < 1%
5
10
100
FREQUENCY (kHz)
1
AV = 10
0.1
–70
VS = ±15V
–80
–90
–100
100k
1469 G34
AV = 1
0.001
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1469 G33
Warm-Up Drift vs Time
0
VS = ±5V
THD + NOISE (dB)
TOTAL HARMONIC DISTORTION (dB)
1
10
–60
–120
1k
10k
FREQUENCY (Hz)
1000
–50
–110
–130
100
AV = 100
1469 G32
VS = ±15V
AV = 2
RL = 2k
VOUT = 10VP-P
100M
10
Total Harmonic Distortion + Noise
vs Amplitude
–100
10M
VS = ±15V
TA = 25°C
0.01
0
1000
Total Harmonic Distortion
vs Frequency
–90
10k 100k
1M
FREQUENCY (Hz)
Output Impedance vs Frequency
AV = 1
1469 G31
–80
1k
1469 G30
100
1
1
40
0
100
100M
30
7
60
Undistorted Output Swing
vs Frequency, VS = ± 15V
VS = ±5V
TA = 25°C
RL = 2k
THD < 1%
8
80
1469 G29
Undistorted Output Swing
vs Frequency, VS = ± 5V
9
100
20
0
100
100M
VS = ±15V
TA = 25°C
RL = 2k
120
80
1469 G28
10
140
VS = ±15V
TA = 25°C
RL = 2k
OUTPUT IMPEDANCE (Ω)
120
Channel Separation
vs Frequency
OFFSET VOLTAGE DRIFT (μV)
POWER SUPPLY REJECTION RATIO (dB)
160
Common Mode Rejection Ratio
vs Frequency
CHANNEL SEPARATION (dB)
Power Supply Rejection Ratio
vs Frequency
TA = 25°C
AV = 1
RL = 600Ω
f = 10kHz
NOISE BW = 80kHz
–110
0.01
0.1
1
OUTPUT SIGNAL (VRMS)
N8 ±5V
–10
S0-8 ±5V
–20
–30
N8 ±15V
–40
–50
S0-8 ±15V
–60
–70
10
1469 G35
–80
0
20
40
60
80 100 120
TIME AFTER POWER UP (s)
140
1469 G36
1469fa
10
LT1469
TYPICAL PERFORMANCE CHARACTERISTICS
Small-Signal Transient, AV = 1
VS = ±15V
Small-Signal Transient, AV = – 1
1469 G37
Large-Signal Transient, AV = 1
VS = ±15V
VS = ±15V
1469 G38
Large-Signal Transient, AV = – 1
1469 G39
VS = ±15V
1469 G40
APPLICATIONS INFORMATION
Layout and Passive Components
The LT1469 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example, fast settling time) use a ground
plane, short lead lengths and RF quality bypass capacitors
(0.01μF to 0.1μF) in parallel with low ESR bypass capacitors (1μF to 10μF tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (e.g., 1.5GΩ of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum IB – specification).
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs: for inverting configurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below).
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
1469fa
11
LT1469
APPLICATIONS INFORMATION
the amplifier. Air currents over device leads should be
minimized, package leads should be short and the two
input leads should be as close together as possible and
maintained at the same temperature.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole which can cause peaking
or even oscillations. For feedback resistors greater than
2k, a feedback capacitor of value CF > RG • CIN/RF should
be used to cancel the input pole and optimize dynamic
performance. For applications where the DC noise gain is
one, and a large feedback resistor is used, CF should be
greater than or equal to CIN. An example would be a DAC
I-to-V converter as shown on the front page of the data
sheet where the DAC can have many tens of picofarads
of output capacitance. Another example would be a gain
of –1 with 5k resistors; a 5pF to 10pF capacitor should
be added across the feedback resistor.
The LT1469 employs bias current cancellation at the inputs.
The inverting input current is trimmed at zero common
mode voltage to minimize errors in inverting applications
such as I-to-V converters. The noninverting input current
is not trimmed and has a wider variation and therefore a
larger maximum value. As the input offset current can be
greater than either input current, the use of balanced source
resistance is NOT recommended as it actually degrades
DC accuracy and also increases noise.
The input bias currents vary with common mode voltage.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
The LT1469 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the positive supply, the output reverses phase.
Total Input Noise
Input Considerations
Each input of the LT1469 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of
the input devices. If large differential input voltages are
anticipated, limit the input current to less than 10mA with
an external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
beyond the supply, limit the current with an external resistor to less than 10mA.
The total input noise of the LT1469 is optimized for a source
resistance between 1k and 20k. Within this range, the
total input noise is dominated by the noise of the source
resistance itself. When the source resistance is below
1k, voltage noise of the amplifier dominates. When the
source resistance is above 20k, the input noise current is
the dominant contributor.
V+
CF
RF
RG
–
CIN
VIN
1/2 LT1469
+IN
R1
100Ω Q1
R1
Q2 100Ω
–IN
VOUT
+
1469 F01
Figure 1. Nulling Input Capacitance
V–
1469 F02
Figure 2. Input Stage Protection
1469fa
12
LT1469
APPLICATIONS INFORMATION
Capacitive Loading
measurements—Application Notes 47 and 74. Appendix B
of AN47 is a vital primer on 12-bit settling measurements
and AN74 extends the state-of-the-art while concentrating
on settling time with a 16-bit current output DAC input.
The LT1469 drives capacitive loads of up to 100pF in unitygain and 300pF in a gain of –1. When there is a need to
drive a larger capacitive load, a small series resistor should
be inserted between the output and the load. In addition,
a capacitor should be added between the output and the
inverting input as shown in Figure 3.
The settling of the DAC I-to-V converter on the front page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
15pF across the 12k feedback resistor. The theoretical limit
for 16-bit settling is 11.1 times this RC time constant or
2μs. The actual settling time is 2.4μs at the output of the
LT1469.
Settling Time
The LT1469 is a single stage amplifier with an optimal
thermal layout that leads to outstanding settling performance. Measuring settling even at the 12-bit level is
very challenging, and at the 16-bit level requires a great
deal of subtlety and expertise. Fortunately, there are two
excellent Linear Technology reference sources for settling
The RC output noise filter adds a slight settling time delay
but reduces the noise bandwidth to 1.6MHz which increases
the output resolution for 16-bit accuracy.
RF
RO ≥ (1 + RF/RG)/(2 • CL • 5MHz)
RF ≥ 10RO
CF = (2RO/RF)CL
CF
RG
–
RO
1/2 LT1469
VIN
+
VOUT
CL
1469 F03
Figure 3. Driving Capacitive Loads
1469fa
13
LT1469
TYPICAL APPLICATIONS
Ultralow Distortion Balanced Audio Line Driver
+
10k
1/2 LT1364
–
2.1k
22pF
33.2Ω
+
30.1Ω
10k
820pF
1/2 LT1469
–
50 FEET SHIELDED
TWISTED PAIR CABLE
1k
INPUT
22pF
ZIN = 10kΩ
600Ω
+
30.1Ω
20k
820pF
1/2 LT1469
THD + N
MEASURED HERE
–
22.1k
22pF
33.2Ω
VS = ±15V
GAIN = 6dB
PARALLEL COMPOSITE TOPOLOGY:
LT1364 PROVIDES OUTPUT CURRENT;
LT1469 PRESERVES LINEARITY
+
20k
1/2 LT1364
–
24.3k
22pF
TOTAL HARMONIC DISTORTION + NOISE
VOUT
FREQUENCY
0.00025%
10VRMS
1kHz
MEASUREMENT BANDWIDTH
22kHz
0.0008%
10VRMS
20Hz TO 20kHz
80kHz
0.0006%
26dBu
1kHz
22kHz
1469 TA02
*1dBu = 1 milliwatt into 600Ω
1469fa
14
LT1469
TYPICAL APPLICATIONS
Extending 16-Bit DAC Performance to 200V Output Swing
125V
1μF
510Ω
VOUT = 200VP-P
IOUT = 25mA
THD + N = –90dB at 100Hz
330Ω
Q1
2N5415
15V
10k
330pF
Q3
2N3440*
VREF
50k
100pF
16 BITS
LTC1597
Q5
2N2222
1M
–
RFB
–
RSELECT***
TYPICAL
19.994k**
6Ω
1/2 LT1469
1k
27Ω
1N4148
1/2 LT1469
OUTPUT
+
1N4148
+
50k
Q6
2N2907
1M
27Ω
1k
–15V
Q3
2N5415*
Q2
2N3440
*HEAT SINK
**VISHAY S102 RESISTOR 0.01%
***1% METAL FILM RESISTOR
NOTE: FOR FURTHER EXPLANATION,
REFER TO APPLICATION NOTE 74, APPENDIX H
510Ω
1μF
330Ω
–125V
50k** 50k** 50k** 50k**
15pF
1469 TA03
1469fa
15
LT1469
SIMPLIFIED SCHEMATIC
V+
I1
I5
I2
Q10
Q8
+IN
Q1
Q2
–IN Q5
Q6
Q7
Q3
I3
I4
OUT
Q9
Q4
BIAS
Q11
C
I6
V–
1469 SS
1469fa
16
LT1469
PACKAGE DESCRIPTION
DF Package
12-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1773 Rev Ø)
2.50 REF
0.70 ±0.05
3.38 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(4 SIDES)
2.50 REF
7
12
0.40 ± 0.10
3.38 ±0.10
2.65 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
(DF12) DFN 0806 REV Ø
0.200 REF
6
R = 0.115
TYP
0.75 ± 0.05
1
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
1469fa
17
LT1469
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow 0.300)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
(
8.255
+0.889
–0.381
)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.100
(2.54)
BSC
.120
(3.048) .020
MIN
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1469fa
18
LT1469
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(Reference LTC DWG # 05-08-1610)
.050 BSC
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
3
4
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
2
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.050
(1.270)
BSC
SO8 0303
1469fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1469
TYPICAL APPLICATION
16-Bit Accurate Single Ended to Differential ADC Buffer
5V
RS
VIN
4096 Point FFT of ADC Output
+
0
100Ω
1/2 LT1469
5V
3000pF
+IN
10pF
2k
16 BITS
333ksps
ADC OUTPUTS
LTC1604
–IN
2k
3000pF
100Ω
–40
–60
–80
–100
1469 TA04
–
AMPLITUDE (dB)
–
fSAMPLE = 333ksps
VIN = ±1.25V
fIN = 100kHz
VS = ±5V
–20
–5V
–120
1/2 LT1469
+
–140
20
0
40
–5V
60 80 100 120 140 160
FREQUENCY (kHz)
1469 TA04a
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1469fa
20 Linear Technology Corporation
LT 0808 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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