LINER LT1224CN8

LT1224
Very High Speed
Operational Amplifier
U
DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
■
Unity-Gain Stable
45MHz Gain-Bandwidth
400V/µs Slew Rate
7V/mV DC Gain: RL = 500Ω
Maximum Input Offset Voltage: 2mV
±12V Minimum Output Swing into 500Ω
Wide Supply Range: ±2.5V to ±15V
7mA Supply Current
90ns Settling Time to 0.1%, 10V Step
Drives All Capacitive Loads
The LT1224 is a very high speed operational amplifier with
excellent DC performance. The LT1224 features reduced
input offset voltage and higher DC gain than devices with
comparable bandwidth and slew rate. The circuit is a
single gain stage with outstanding settling characteristics.
The fast settling time makes the circuit an ideal choice for
data acquisition systems. The output is capable of driving
a 500Ω load to ±12V with ±15V supplies and a 150Ω load
to ±3V on ±5V supplies. The circuit is also capable of
driving large capacitive loads which makes it useful in
buffer or cable driver applications.
UO
APPLICATI
■
■
■
■
■
The LT1224 is a member of a family of fast, high performance amplifiers that employ Linear Technology
Corporation’s advanced bipolar complementary
processing.
Wideband Amplifiers
Buffers
Active Filters
Video and RF Amplification
Cable Drivers
Data Acquisition Systems
UO
■
S
TYPICAL APPLICATI
DAC Current-to-Voltage Converter
Inverter Pulse Response
7pF
5k
DAC-08
TYPE
–
LT1224
VOUT
+
0.1µF
5k
1 LSB SETTLING = 140ns
LT1224 • TA01
LT1224 • TA02
1
LT1224
PACKAGE/ORDER I FOR ATIO
U
W W
W
Total Supply Voltage (V+ to V–) ............................... 36V
Differential Input Voltage ......................................... ±6V
Input Voltage ............................................................±VS
Output Short Circuit Duration (Note 1) ............ Indefinite
Operating Temperature Range
LT1224C ................................................ 0°C to 70°C
Maximum Junction Temperature
Plastic Package .............................................. 150°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
ELECTRICAL CHARACTERISTICS
U
RATI GS
W
AXI U
U
ABSOLUTE
ORDER PART
NUMBER
TOP VIEW
NULL
1
8
NULL
–IN
2
7
V+
+IN
3
6
OUT
V–
4
5
NC
N8 PACKAGE
8-LEAD PLASTIC DIP
LT1224CN8
LT1224CS8
S8 PACKAGE
8-LEAD PLASTIC SOIC
S8 PART MARKING
LT1224 • POI01
1224
TJMAX = 150°C, θJA = 100°C/W (N8)
TJMAX = 150°C, θJA = 150°C/W (S8)
VS = ±15V, TA = 25°C, RL = 1k, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
(Note 2)
IOS
Input Offset Current
IB
Input Bias Current
en
Input Noise Voltage
f = 10kHz
in
Input Noise Current
f = 10kHz
RIN
Input Resistance
VCM = ±12V
Differential
CIN
Input Capacitance
Input Voltage Range +
MIN
TYP
MAX
UNITS
0.5
2.0
mV
100
400
nA
4
8
µA
22
nV/√Hz
1.5
pA/√Hz
24
40
250
MΩ
kΩ
2
pF
12
14
V
Input Voltage Range –
– 13
– 12
V
CMRR
Common-Mode Rejection Ratio
VCM = ±12V
86
100
dB
PSRR
Power Supply Rejection Ratio
VS = ±5V to ±15V
75
84
dB
AVOL
Large-Signal Voltage Gain
VOUT = ±10V, RL = 500Ω
3.3
7
V/mV
VOUT
Output Swing
RL = 500Ω
±12.0
±13.3
IOUT
Output Current
VOUT = ±12V
24
40
mA
SR
Slew Rate
AVCL = –2, (Note 3)
250
400
V/µs
Full Power Bandwidth
10V Peak, (Note 4)
6.4
MHz
GBW
Gain-Bandwidth
f = 1MHz
45
MHz
tr, tf
Rise Time, Fall Time
AVCL = 1, 10% to 90%, 0.1V
5
ns
Overshoot
AVCL = 1, 0.1V
30
%
Propagation Delay
50% VIN to 50% VOUT
5
ns
Settling Time
10V Step, 0.1%
90
ns
Differential Gain
f = 3.58MHz, RL = 150Ω
1
%
Differential Phase
f = 3.58MHz, RL = 150Ω
2.4
RO
Output Resistance
AVCL = 1, f = 1MHz
2.5
IS
Supply Current
ts
2
7
V
Deg
Ω
9
mA
LT1224
ELECTRICAL CHARACTERISTICS VS = ±5V, TA = 25°C, RL = 1k, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
(Note 2)
IOS
Input Offset Current
IB
Input Bias Current
MIN
Input Voltage Range +
TYP
MAX
1
4
mV
100
400
nA
4
8
µA
2.5
UNITS
4
Input Voltage Range –
V
–3
– 2.5
V
CMRR
Common-Mode Rejection Ratio
VCM = ±2.5V
86
98
dB
AVOL
Large-Signal Voltage Gain
VOUT = ±2.5V, RL = 500Ω
VOUT = ±2.5V, RL = 150Ω
2.5
7
3
V/mV
V/mV
VOUT
Output Swing
RL = 500Ω
RL = 150Ω
±3.0
±3.0
±3.7
±3.3
IOUT
Output Current
VOUT = ±3V
20
40
mA
SR
Slew Rate
AVCL = –2, (Note 3)
250
V/µs
Full Power Bandwidth
3V Peak, (Note 4)
13.3
MHz
GBW
Gain-Bandwidth
f = 1MHz
34
MHz
tr, tf
Rise Time, Fall Time
AVCL = 1, 10% to 90%, 0.1V
7
ns
Overshoot
AVCL = 1, 0.1V
20
%
Propagation Delay
50% VIN to 50% VOUT
7
ns
ts
Settling Time
–2.5V to 2.5V, 0.1%
90
IS
Supply Current
V
V
ns
7
ELECTRICAL CHARACTERISTICS
9
mA
0°C ≤ TA ≤ 70°C, RL = 1k, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
VS = ±15V, (Note 2)
VS = ±5V, (Note 2)
MIN
Input VOS Drift
TYP
MAX
1
2
4
5
UNITS
mV
mV
µV/°C
25
IOS
Input Offset Current
VS = ±15V and VS = ±5V
IB
Input Bias Current
VS = ±15V and VS = ±5V
CMRR
Common-Mode Rejection Ratio
VS = ±15V, VCM = ±12V and VS = ±5V, VCM = ±2.5V
83
98
dB
PSRR
Power Supply Rejection Ratio
VS = ±5V to ±15V
73
84
dB
AVOL
Large-Signal Voltage Gain
VS = ±15V, VOUT = ±10V, RL = 500Ω
VS = ±5V, VOUT = ±2.5V, RL = 500Ω
2.5
2.0
7
7
V/mV
V/mV
VOUT
Output Swing
VS = ±15V, RL = 500Ω
VS = ±5V, RL = 500Ω or 150Ω
±12.0
±3.0
±13.3
±3.3
IOUT
Output Current
VS = ±15V, VOUT = ±12V
VS = ±5V, VOUT = ±3V
24
20
40
40
SR
Slew Rate
VS = ±15V, AVCL = –2, (Note 3)
250
400
IS
Supply Current
VS = ±15V and VS = ±5V
Note 1: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Note 2: Input offset voltage is tested with automated test equipment
in <1 second.
100
600
nA
4
9
µA
7
V
V
mA
mA
V/µs
10.5
mA
Note 3: Slew rate is measured in a gain of –2 between ±10V on the output
with ±6V on the input for ±15V supplies and ±2V on the output with
±1.75V on the input for ±5V supplies.
Note 4: Full power bandwidth is calculated from the slew rate
measurement: FPBW = SR/2πVp.
3
LT1224
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Common-Mode Range vs
Supply Voltage
20
8.0
15
10
+VCM
–VCM
5
0
7.5
7.0
6.5
5
10
15
0
20
5
SUPPLY VOLTAGE (±V)
10
15
15
10
VS = ±5V
0
100
1k
4.5
4.0
3.5
–5
–10
5
0
5
125
2
4.5
4.25
4.0
TEMPERATURE (°C)
3.5
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
LT1224 • TPC07
10k
Output Short Circuit Current vs
Temperature
55
3.75
100
1k
LT1224 • TPC06
OUTPUT SHORT-CIRCUIT CURRENT (mA)
INPUT BIAS CURRENT (µA)
6
75
100
10
LOAD RESISTANCE (Ω)
VS = ±15V
I + + IB–
IB = B
4.75
50
VS = ±5V
50
15
Input Bias Current vs Temperature
9
SUPPLY CURRENT (mA)
10
50
25
70
LT1224 • TPC05
VS = ±15V
0
VS = ±15V
80
60
Supply Current vs Temperature
–25
TA = 25°C
INPUT COMMON-MODE VOLTAGE (V)
10
20
90
LT1224 • TPC04
7
15
Open-Loop Gain vs
Resistive Load
100
3.0
–15
10k
8
10
LT1224 • TPC03
VS = ±15V
TA = 25°C
IB+ + IB–
IB =
2
LOAD RESISTANCE (Ω)
4
–50
5
SUPPLY VOLTAGE (±V)
OPEN-LOOP GAIN (dB)
INPUT BIAS CURRENT (µA)
OUTPUT VOLTAGE SWING (Vp-p)
VS = ±15V
10
0
20
5.0
5
5
Input Bias Current vs Input
Common-Mode Voltage
TA = 25°C
∆VOS = 30mV
20
–VSW
LT1224 • TPC02
Output Voltage Swing vs
Resistive Load
25
+VSW
10
SUPPLY VOLTAGE (±V)
LT1224 • TPC01
30
15
0
6.0
0
TA = 25°C
RL = 500Ω
∆VOS = 30mV
TA = 25°C
OUTPUT VOLTAGE SWING (V)
TA = 25°C
∆VOS < 1mV
SUPPLY CURRENT (mA)
MAGNITUDE OF INPUT VOLTAGE (V)
20
4
Output Voltage Swing vs
Supply Voltage
Supply Current vs Supply Voltage
VS = ±5V
50
45
40
SOURCE
SINK
35
30
25
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
LT1224 • TPC08
LT1224 • TPC09
LT1224
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Rejection Ratio vs
Frequency
Input Noise Spectral Density
in
1
100
en
10
10
100
1k
10k
120
VS = ±15V
TA = 25°C
80
+PSRR
60
–PSRR
40
20
0
100
0.1
100k
10k
1k
100k
1M
Voltage Gain and Phase vs
Frequency
100
60
VS = ±5V
20
40
20
0
10M
1M
4
AV = +1
8
AV = –1
0
–2
–4
AV = +1
AV = –1
6
VS = ±15V
TA = 25°C
AV = –1
4
C = 100pF
2
C = 50pF
0
–2
C=0
–4
C = 500pF
–6
C = 1000pF
–8
–10
–10
0
100M
20
0
40
FREQUENCY (Hz)
60
80
100
1M
120
10M
LT1224 • TPC15
LT1224 • TPC13
Gain-Bandwidth vs Temperature
Slew Rate vs Temperature
48
100
VS = ±15V
TA = 25°C
AV = 1
100M
FREQUENCY (Hz)
SETTLING TIME (ns)
LT1224 • TPC14
Closed-Loop Output Impedance vs
Frequency
500
VS = ±15V
1
0.1
–SR
46
45
44
43
1M
10M
100M
42
–50
LT1224 • TPC16
400
+SR
350
300
250
–25
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (Hz)
VS = ±15V
AV = –2
450
SLEW RATE (V/µs)
GAIN BANDWIDTH (MHz)
47
10
100M
10M
LT1224 • TPC12
–8
100k
100k
10k
Frequency Response vs
Capacitive Load
2
–6
TA = 25°C
OUTPUT IMPEDANCE (Ω)
1k
VOLTAGE MAGNITUDE (dB)
VS = ±15V
0.01
10k
20
10
6
OUTPUT SWING (V)
VOLTAGE GAIN (dB)
80
40
1M
40
FREQUENCY (Hz)
VS = ±15V
TA = 25°C
10mV SETTLING
8
PHASE MARGIN (DEGREES)
VS = ±5V
100k
60
0
100M
10
VS = ±15V
10k
80
Output Swing vs Settling Time
80
1k
100
LT1224 • TPC11
LT1224 • TPC10
–20
100
10M
VS = ±15V
TA = 25°C
FREQUENCY (Hz)
FREQUENCY (Hz)
60
COMMON-MODE REJECTION RATIO (dB)
10
1000
POWER SUPPLY REJECTION RATIO (dB)
VS = ±15V
TA = 25°C
AV = +101
RS = 100k
INPUT CURRENT NOISE (pA/√Hz)
INPUT VOLTAGE NOISE (nV/√Hz)
100
100
10000
Common Mode Rejection Ratio vs
Frequency
200
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
LT1224 • TPC17
LT1224 • TPC18
5
LT1224
U
W
U
UO
APPLICATI
S I FOR ATIO
The LT1224 may be inserted directly into HA2541, HA2544,
AD847, EL2020 and LM6361 applications, provided that
the nulling circuitry is removed. The suggested nulling
circuit for the LT1224 is shown below.
overshoot in the unity-gain small-signal transient response. Higher noise gain configurations exhibit less
overshoot as seen in the inverting gain of one response.
Small Signal, AV = 1
Small Signal, AV = –1
Offset Nulling
V+
5k
1
3
+
0.1µF
8
7
LT1224
2
–
6
4
LT1224 • TA04
0.1µF
V–
LT1224 • TA03
Layout and Passive Components
As with any high speed operational amplifier, care must be
taken in board layout in order to obtain maximum performance. Key layout issues include: use of a ground plane,
minimization of stray capacitance at the input pins, short
lead lengths, RF-quality bypass capacitors located close
to the device (typically 0.01µF to 0.1µF), and use of low
ESR bypass capacitors for high drive current applications
(typically 1µF to 10µF tantalum). Sockets should be
avoided when maximum frequency performance is
required, although low profile sockets can provide
reasonable performance up to 50MHz. For more details
see Design Note 50. Feedback resistor values greater than
5k are not recommended because a pole is formed with the
input capacitance which can cause peaking. If feedback
resistors greater than 5k are used, a parallel
capacitor of 5pF to 10pF should be used to cancel the input
pole and optimize dynamic performance.
Transient Response
The LT1224 gain bandwidth is 45MHz when measured at
f = 1MHz. The actual frequency response in unity-gain is
considerably higher than 45MHz due to peaking caused by
a second pole beyond the unity-gain crossover. This is
reflected in the 50° phase margin and shows up as
6
The large-signal responses in both inverting and noninverting gain show symmetrical slewing characteristics.
Normally the noninverting response has a much faster
rising edge than falling edge due to the rapid change in
input common-mode voltage which affects the tail current
of the input differential pair. Slew enhancement circuitry
has been added to the LT1224 so that the noninverting
slew rate response is balanced.
Large Signal, AV = 1
Large Signal, AV = –1
LT1224 • TA06
Input Considerations
Resistors in series with the inputs are recommended for
the LT1224 in applications where the differential input
voltage exceeds ±6V continuously or on a transient basis.
An example would be in noninverting configurations with
high input slew rates or when driving heavy capacitive
loads. The use of balanced source resistance at each input
is recommended for applications where DC accuracy must
be maximized.
LT1224
U
W
U
UO
APPLICATI
S I FOR ATIO
Capacitive Loading
The LT1224 is stable with all capacitive loads. This is
accomplished by sensing the load induced output pole and
adding compensation at the amplifier gain node. As the
capacitive load increases, both the bandwidth and phase
margin decrease so there will be peaking in the frequency
domain and in the transient response. The photo of the
small-signal response with 1000pF load shows 50% peaking. The large-signal response with a 10,000pF load shows
the output slew rate being limited by the short-circuit
current.
AV = – 1, CL = 1000pF
AV = 1, CL = 10,000pF
LT1224 • TA06
The LT1224 can drive coaxial cable directly, but for best
pulse fidelity the cable should be doubly terminated with
a resistor in series with the output.
Cable Driving
R3
75 Ω
+
VIN
75Ω CABLE
LT1224
VOUT
–
R4
75Ω
R1
1k
R2
1k
LT1224 • TA07
DAC Current-to-Voltage Converter
The wide bandwidth, high slew rate and fast settling time
of the LT1224 make it well-suited for current-to-voltage
conversion after current output D/A converters. A typical
application is shown on the first page of this data sheet
with a DAC-08 type converter with a full-scale output of
2mA. A compensation capacitor is used across the feedback resistor to null the pole at the inverting input caused
by the DAC output capacitance. The combination of the
LT1224 and DAC settles to 40mV in 140ns for both a 0V
to 10V step and for a 10V to 0V step.
UO
TYPICAL APPLICATI
S
Two Op Amp Instrumentation Amplifier
1MHz, 2nd Order Butterworth Filter
R1
10k
C2
100pF
R1
619Ω
R4
10k
R5
220Ω
R2
619Ω
R3
825Ω
R2
1k
LT1224
LT1224
C1
500pF
R3
1k
–
–
VIN
VOUT
+
AV =
LT1224 • TA08
[
1
R4
1+
2
R3
LT1224
VOUT
+
VIN
+
–38dB AT 10MHz
SMALL SIGNAL OVERSHOOT = 10%
–
+
–
( R2R1 + R3R4 ) + R2R5+ R3 ] = 102
TRIM R5 FOR GAIN
TRIM R1 FOR COMMON-MODE REJECTION
BW = 430kHz
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
LT1224 • TA09
7
LT1224
W
W
SI PLIFIED SCHE ATIC
V+
7
NULL
1
8
BIAS 1
+IN
3
BIAS 2
2 –IN
6
V–
OUT
4
LT1224 • TA10
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead Plastic DIP
0.300 – 0.320
(7.620 – 8.128)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
8
0.009 - 0.015
(0.229 - 0.381)
+0.025
0.325 –0.015
(
+0.635
8.255
–0.381
0.125
(3.175)
MIN
0.045 ± 0.015
(1.143 ± 0.381)
)
0.400
(10.160)
MAX
0.100 ± 0.010
(2.540 ± 0.254)
7
6
5
0.250 ± 0.010
(6.350 ± 0.254)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
1
3
2
4
N8 1291
S8 Package
8-Lead Plastic SOIC
0.010 – 0.020
× 45°
(0.254 – 0.508)
8
0°– 8° TYP
6
5
0.004 – 0.010
(0.102 – 0.254)
0.228 – 0.244
(5.791 – 6.198)
0.014 – 0.019
(0.356 – 0.483)
0.150 – 0.157
(3.810 – 3.988)
0.050
(1.270)
BSC
1
8
7
0.053 – 0.069
(1.346 – 1.753)
0.008 – 0.010
(0.203 – 0.254)
0.016 – 0.050
0.406 – 1.270
0.189 – 0.197
(4.801 – 5.004)
Linear Technology Corporation
2
3
4
S8 1291
LT/GP 1192 5K REV A
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1991