CY14C512J CY14B512J CY14E512J 512-Kbit (64 K × 8) Serial (I2C) nvSRAM 512-Kbit (64 K × 8) Serial (I2C) nvSRAM Features ■ 512-Kbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 64 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL) ❐ Automatic STORE on power-down with a small capacitor (except for CY14X512J1) ■ High reliability ■ Infinite read, write, and RECALL cycles 1 million STORE cycles to QuantumTrap ❐ Data retention: 20 years at 85 C 2 ■ High speed I C interface ❐ Industry standard 100 kHz and 400 kHz speed ❐ Fast-mode Plus: 1 MHz speed ❐ High speed: 3.4 MHz ❐ Zero cycle delay reads and writes ■ Write protection ❐ Hardware protection using Write Protect (WP) pin ❐ Software block protection for one-quarter, one-half, or entire array 2 ■ I C access to special functions ❐ Nonvolatile STORE/RECALL ❐ 8 byte serial number ❐ Manufacturer ID and Product ID ❐ Sleep mode ■ Low power consumption ❐ Average active current of 1 mA at 3.4 MHz operation ❐ Average standby mode current of 150 µA ❐ Sleep mode current of 8 µA ❐ ❐ Logic Block Diagram Industry standard configurations ❐ Operating voltages: • CY14C512J: VCC = 2.4 V to 2.6 V • CY14B512J: VCC = 2.7 V to 3.6 V • CY14E512J: VCC = 4.5 V to 5.5 V ❐ Industrial temperature ❐ 8- and 16-pin small outline integrated circuit (SOIC) package ❐ Restriction of hazardous substances (RoHS) compliant Overview The Cypress CY14C512J/CY14B512J/CY14E512J combines a 512-Kbit nvSRAM[1] with a nonvolatile element in each memory cell. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X512J1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands. Configuration Feature CY14X512J1 CY14X512J2 CY14X512J3 AutoStore No Yes Software STORE Yes Yes Yes Hardware STORE No No Yes Slave Address pins A2, A1, A0 A2, A1 A2, A1, A0 Serial Number 8x8 VCC VCAP Manufacturer ID / Product ID Power Control Block Memory Control Register Quantum Trap 64 K x 8 Command Register Sleep SDA SCL A2, A1, A0 WP Yes Control Registers Slave 2 I C Control Logic Slave Address Decoder Memory Address and Data Control Memory Slave SRAM 64 K x 8 STORE RECALL Note 1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet. Cypress Semiconductor Corporation Document Number: 001-65232 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 24, 2012 CY14C512J CY14B512J CY14E512J Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 I2C Interface ...................................................................... 4 Protocol Overview ............................................................ 4 I2C Protocol – Data Transfer ....................................... 4 Data Validity ................................................................ 5 START Condition (S) ................................................... 5 STOP Condition (P) ..................................................... 5 Repeated START (Sr) ................................................. 5 Byte Format ................................................................. 5 Acknowledge / No-acknowledge ................................. 5 High Speed Mode (Hs-mode) ...................................... 6 Slave Device Address ................................................. 7 Write Protection (WP) .................................................. 9 AutoStore Operation .................................................... 9 Hardware STORE and HSB pin Operation ................. 9 Hardware RECALL (Power-Up) .................................. 9 Write Operation ......................................................... 10 Read Operation ......................................................... 10 Memory Slave Access ............................................... 10 Control Registers Slave ............................................. 14 Serial Number ................................................................. 16 Serial Number Write .................................................. 16 Serial Number Lock ................................................... 16 Serial Number Read .................................................. 16 Device ID ......................................................................... 17 Executing Commands Using Command Register ..... 17 Document Number: 001-65232 Rev. *D Maximum Ratings ........................................................... 18 Operating Range ............................................................. 18 DC Electrical Characteristics ........................................ 18 Data Retention and Endurance ..................................... 19 Thermal Resistance ........................................................ 19 AC Test Loads and Waveforms ..................................... 20 AC Test Conditions ........................................................ 20 AC Switching Characteristics ....................................... 21 Switching Waveforms .................................................... 21 nvSRAM Specifications ................................................. 22 Switching Waveforms .................................................... 22 Software Controlled STORE/RECALL Cycles .............. 23 Switching Waveforms .................................................... 23 Hardware STORE Cycle ................................................. 24 Switching Waveforms .................................................... 24 Ordering Information ...................................................... 25 Ordering Code Definitions ......................................... 25 Package Diagrams .......................................................... 26 Acronyms ........................................................................ 28 Document Conventions ................................................. 28 Units of Measure ....................................................... 28 Document History Page ................................................. 29 Sales, Solutions, and Legal Information ...................... 30 Worldwide Sales and Design Support ....................... 30 Products .................................................................... 30 PSoC Solutions ......................................................... 30 Page 2 of 30 CY14C512J CY14B512J CY14E512J Pinouts Figure 1. 8-pin SOIC pinout A0 1 A1 2 A2 3 VSS 4 CY14X512J1 Top View not to scale VCAP 1 WP A1 2 6 SCL A2 3 5 SDA VSS 4 8 VCC 7 CY14X512J2 Top View not to scale 8 VCC 7 WP 6 SCL 5 SDA Figure 2. 16-pin SOIC pinout NC 1 16 VCC NC 2 15 NC NC 3 14 VCAP NC 4 13 A2 CY14X512J3 Top View not to scale WP 5 12 SDA A0 6 11 SCL NC 7 10 A1 8 9 HSB VSS Pin Definitions Pin Name I/O Type SCL Input SDA Description Clock. Runs at speeds up to a maximum of fSCL. Input/Output I/O. Input/Output of data through I2C interface. Output: Is open-drain and requires an external pull-up resistor. WP Input Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be left open if not connected. A2-A0[2] Input Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can be left open if not connected. HSB Input/Output Hardware STORE Busy Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional). Input: Hardware STORE implemented by pulling this pin LOW externally. VCAP Power Supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It must never be connected to ground. NC No connect No connect. This pin is not connected to the die. VSS Power supply Ground. VCC Power supply Power supply. Note 2. A0 pin is not available in CY14X512J2. Document Number: 001-65232 Rev. *D Page 3 of 30 CY14C512J CY14B512J CY14E512J I2C Interface bit slave address and eighth bit (R/W) indicating a read (1) or a write (0) operation. All signals are transmitted on the open-drain SDA line and are synchronized with the clock on SCL line. Each byte of data transmitted on the I2C bus is acknowledged by the receiver by holding the SDA line LOW on the ninth clock pulse. The request for write by the master is followed by the memory address and data bytes on the SDA line. The writes can be performed in burst-mode by sending multiple bytes of data. The memory address increments automatically after receiving /transmitting of each byte on the falling edge of 9th clock cycle. The new address is latched just prior to sending/receiving the acknowledgment bit. This allows the next sequential byte to be accessed with no additional addressing. On reaching the last memory location, the address rolls back to 0x0000 and writes continue. The slave responds to each byte sent by the master during a write operation with an ACK. A write sequence can be terminated by the master generating a STOP or Repeated START condition. I2C bus consists of two lines – serial clock line (SCL) and serial data line (SDA) that carry information between multiple devices on the bus. I2C supports multi-master and multi-slave configurations. The data is transmitted from the transmitter to the receiver on the SDA line and is synchronized with the clock SCL generated by the master. The SCL and SDA lines are open-drain lines and are pulled up to VCC using resistors. The choice of pull-up resistor on the system depends on the bus capacitance and the intended speed of operation. The master generates the clock and all the data I/Os are transmitted in synchronization with this clock. The CY14X512J supports up to 3.4 MHz clock speed on SCL line. Protocol Overview This device supports only a 7-bit addressable scheme. The master generates a START condition to initiate the communication followed by broadcasting a slave select byte. The slave select byte consists of a seven bit address of the slave that the master intends to communicate with and R/W bit indicating a read or a write operation. The selected slave responds to this with an acknowledgement (ACK). After a slave is selected, the remaining part of the communication takes place between the master and the selected slave device. The other devices on the bus ignore the signals on the SDA line till a STOP or Repeated START condition is detected. The data transfer is done between the master and the selected slave device through the SDA pin synchronized with the SCL clock generated by the master. A read request is performed at the current address location (address next to the last location accessed for read or write). The memory slave device responds to a read request by transmitting the data on the current address location to the master. A random address read may also be performed by first sending a write request with the intended address of read. The master must abort the write immediately after the last address byte and issue a Repeated START or STOP signal to prevent any write operation. The following read operation starts from this address. The master acknowledges the receipt of one byte of data by holding the SDA pin LOW for the ninth clock pulse. The reads can be terminated by the master sending a no-acknowledge (NACK) signal on the SDA line after the last data byte. The no-acknowledge signal causes the CY14X512J to release the SDA line and the master can then generate a STOP or a Repeated START condition to initiate a new operation. I2C Protocol – Data Transfer Each transaction in I2C protocol starts with the master generating a START condition on the bus, followed by a seven Figure 3. System Configuration using Serial (I2C) nvSRAM Vcc RPmin = (VCC - VOLmax) / IOL RPmax = tr / (0.8473 * Cb) SDA Microcontroller SCL Vcc Vcc A0 SCL A0 SCL A0 SCL A1 SDA A1 SDA A1 SDA WP A2 WP A2 CY14X512J #0 Document Number: 001-65232 Rev. *D A2 WP CY14X512J CY14X512J #1 #7 Page 4 of 30 CY14C512J CY14B512J CY14E512J Data Validity STOP Condition (P) The data on the SDA line must be stable during the HIGH period of the clock. The state of the data line can only change when the clock on the SCL line is LOW for the data to be valid. There are only two conditions under which the SDA line may change state with SCL line held HIGH, that is, START and STOP condition. The START and STOP conditions are generated by the master to signal the beginning and end of a communication sequence on the I2C bus. A LOW to HIGH transition on the SDA line while SCL is HIGH indicates a STOP condition. This condition indicates the end of the ongoing transaction. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again after the STOP condition. Repeated START (Sr) START Condition (S) A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. Every transaction in I2C begins with the master generating a START condition. If an Repeated START condition is generated instead of a STOP condition the bus continues to be busy. The ongoing transaction on the I2C lines is stopped and the bus waits for the master to send a slave ID for communication to restart. Figure 4. START and STOP Conditions full pagewidth SDA SDA SCL SCL S P STOP Condition START Condition Figure 5. Data Transfer on the I2C Bus ndbook, full pagewidth P SDA Acknowledgement signal from slave MSB SCL S or Sr 1 2 START or Repeated START condition 7 8 1 9 ACK Each operation in I2C is done using 8 bit words. The bits are sent in MSB first format on SDA line and each byte is followed by an ACK signal by the receiver. An operation continues till a NACK is sent by the receiver or STOP or Repeated START condition is generated by the master The SDA line must remain stable when the clock (SCL) is HIGH except for a START or STOP condition. Acknowledge / No-acknowledge After transmitting one byte of data or address, the transmitter releases the SDA line. The receiver pulls the SDA line LOW to acknowledge the receipt of the byte. Every byte of data transferred on the I2C bus needs to be responded with an ACK signal by the receiver to continue the operation. Failing to do so is considered as a NACK state. NACK is the state where receiver 2 3-8 9 ACK Byte complete, interrupt within slave Byte Format Document Number: 001-65232 Rev. *D Acknowledgement signal from receiver Clock line held LOW while interrupts are serviced Sr Sr or P STOP or Repeated START condition does not acknowledge the receipt of data and the operation is aborted. NACK can be generated by master during a READ operation in following cases: ■ The master did not receive valid data due to noise ■ The master generates a NACK to abort the READ sequence. After a NACK is issued by the master, nvSRAM slave releases control of the SDA pin and the master is free to generate a Repeated START or STOP condition. NACK can be generated by nvSRAM slave during a WRITE operation in following cases: nvSRAM did not receive valid data due to noise. ■ The master tries to access write protected locations on the nvSRAM. Master must restart the communication by generating a STOP or Repeated START condition. ■ Page 5 of 30 CY14C512J CY14B512J CY14E512J Figure 6. Acknowledge on the I2C Bus handbook, full pagewidth DATA OUTPUT BY MASTER not acknowledge (A) DATA OUTPUT BY SLAVE acknowledge (A) SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition High Speed Mode (Hs-mode) Serial Data Format in Hs-mode In Hs-mode, nvSRAM can transfer data at bit rates of up to 3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place the device into high speed mode. This enables master slave communication for speed upto 3.4 MHz. A stop condition exits Hs-mode. Serial data transfer format in Hs-mode meets the standard-mode I2C-bus specification. Hs-mode can only commence after the following conditions (all of which are in F/S-modes): 1. START condition (S) 2. 8-bit master code (0000 1XXXb) 3. No-acknowledge bit (A) Figure 7. Data transfer format in Hs-mode handbook, full pagewidth Hs-mode F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A F/S-mode DATA n (bytes+ ack.) A/A P Hs-mode continues Sr SLAVE ADD. Single and multiple-byte reads and writes are supported. After the device enters into Hs-mode, data transfer continues in Hs-mode until stop condition is sent by master device. The slave switches back to F/S-mode after a STOP condition (P). To Document Number: 001-65232 Rev. *D continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode timings for read and write operation. Page 6 of 30 CY14C512J CY14B512J CY14E512J Slave Device Address 2 Every slave device on an I C bus has a device select address. The first byte after START condition contains the slave device address with which the master intends to communicate. The seven MSBs are the device address and the LSB (R/W bit) is used for indicating Read or Write operation. The CY14X512J reserves two sets of upper 4 MSBs [7:4] in the slave device address field for accessing Memory and Control Registers. The accessing mechanism is described in Memory Slave Device on page 7. The nvSRAM product provides two different functionalities: Memory and Control Registers functions (such as serial number and product ID). The two functions of the device are accessed through different slave device addresses. The first four most significant bits [7:4] in the device address register are used to select between the nvSRAM functions. Table 1. Slave device Addressing Bit 7 Bit 6 Bit 5 Bit 4 1 0 1 0 Bit 3 Bit 2 Bit 1 Device Select ID nvSRAM Bit 0 Function Select CY14X512J Slave Devices R/W Selects Memory Memory, 64 K × 8 Control Registers - Memory Control Register, 1 × 8 0 0 1 1 Device Select ID R/W - Serial Number, 8 × 8 Selects Control Registers - Device ID, 4 × 8 - Command Register, 1 × 8 Memory Slave Device The nvSRAM device is selected for Read/Write if the master issues the slave address as 1010b followed by two/three bits of device select. For CY14X512J1/J3, the device select is three bits and for CY14X512J2, it is two bits with the third bit don’t care. If the slave address sent by the master matches with the Memory Slave device address, then depending on the R/W bit of the slave address, data is either read from (R/W = ‘1’) or written to (R/W = ‘0’) the nvSRAM. The address length for CY14X512J is 16 bits and thus it requires two address bytes to map the entire memory address location. The dedicated two address bytes represent bit A0 to A15. Figure 8. Memory Slave Device Address MSB handbook, halfpage 1 LSB 0 1 0 Slave ID A2 A1 A0/X R/W Device Select Control Registers Slave Device The Control Registers Slave device includes the Serial Number, Product ID, Memory Control and Command Register. The nvSRAM Control Register Slave device is selected for Read/Write if the master issues the Slave address as 0011b followed by two/three bits of device select. For CY14X512J1/J3 device select is 3 bits and for CY14X512J2 it is two bits with third bit don’t care. If slave address sent by the master matches with the Memory Slave device address then depending on the R/W Document Number: 001-65232 Rev. *D bit of the slave address, data is either read from (R/W = ‘1’) or written to (R/W = ‘0’) the nvSRAM. Figure 9. Control Registers Slave Device Address MSB handbook, halfpage 0 LSB 0 1 1 A2 A1 A0/X R/W Device Select Slave ID Table 2. Control Registers Map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Description Memory Control Register Serial Number 8 Bytes Read/Write Details Read/Write Contains Block Protect Bits and Serial Number Lock bit Read/Write Programmable Serial (Read only Number. Locked by when SNL setting the Serial is set) Number lock bit in the Memory Control Register to ‘1’. Page 7 of 30 CY14C512J CY14B512J CY14E512J Table 2. Control Registers Map (continued) Address 0x09 0x0A 0x0B 0x0C 0x0D 0xAA Description Device ID Read/Write Details Read only Device ID is factory programmed Reserved Command Register Table 5. Refer to Serial Number on page 16 for details on how to execute a command register byte. Table 5. Command Register Bytes Reserved Reserved Write only Allows commands for STORE, RECALL, AutoStore Enable/Disable, SLEEP Mode Memory Control Register The Memory Control Register contains the following bits: ■ Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 SNL (0) 0 0 BP1 (0) BP0 (0) 0 0 BP1:BP0: Block Protect bits are used to protect 1/4, 1/2 or full memory array. These bits can be written through a write instruction to the 0x00 location of the Control Register Slave device. However, any STORE cycle causes transfer of SRAM data into a nonvolatile cell regardless of whether or not the block is protected. The default value shipped from the factory for BP0 and BP1 is ‘0’. BP1:BP0 00 01 10 11 Block Protection None 0xC000–0xFFFF 0x8000–0xFFFF 0x0000–0xFFFF SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to lock the serial number. Once the bit is set to ‘1’, the serial number registers are locked and no modification is allowed. This bit cannot be cleared to ‘0’. The serial number is secured on the next STORE operation (Software STORE or AutoStore). If AutoStore is not enabled, user must perform the Software STORE operation to secure the lock bit status. If a STORE was not performed, the serial number lock bit will not survive the power cycle. The default value shipped from the factory for SNL is ‘0’. Command Register The Command Register resides at address “AA” of the Control Registers Slave device. This is a write only register. The byte written to this register initiates a STORE, RECALL, AutoStore Enable, AutoStore Disable and sleep mode operation as listed in Description STORE 0110 0000 RECALL 0101 1001 0001 1001 1011 1001 ASENB ASDISB SLEEP STORE SRAM data to nonvolatile memory RECALL data from nonvolatile memory to SRAM Enable AutoStore Disable AutoStore Enter Sleep Mode for low power consumption STORE: Initiates nvSRAM Software STORE. The nvSRAM cannot be accessed for tSTORE time after this instruction has been executed. When initiated, the device performs a STORE operation regardless of whether a write has been performed since the last NV operation. After the tSTORE cycle time is completed, the SRAM is activated again for read and write operations. ■ RECALL: Initiates nvSRAM Software RECALL. The nvSRAM cannot be accessed for tRECALL time after this instruction has been executed. The RECALL operation does not alter the data in the nonvolatile elements. A RECALL may be initiated in two ways: Hardware RECALL, initiated on power-up; and Software RECALL, initiated by a I2C RECALL instruction. ■ ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be accessed for tSS time after this instruction has been executed. This setting is not nonvolatile and needs to be followed by a manual STORE sequence if this is desired to survive power cycle. The part comes from the factory with AutoStore Enabled and 0x00 written in all cells. ■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot be accessed for tSS time after this instruction has been executed. This setting is not nonvolatile and needs to be followed by a manual STORE sequence if this is desired to survive power cycle. Table 4. Block Protection Level 0 1/4 1/2 1 Command ■ Table 3. Memory Control Register Bits Bit 7 Data Byte [7:0] 0011 1100 Note If AutoStore is disabled and VCAP is not required, it is required that the VCAP pin is left open. VCAP pin must never be connected to ground. Power-Up RECALL operation cannot be disabled in any case. ■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode. When the SLEEP instruction is registered, the nvSRAM takes tSS time to process the SLEEP request. Once the SLEEP command is successfully registered and processed, the nvSRAM toggles HSB LOW, performs a STORE operation to secure the data to nonvolatile memory and then enters into SLEEP mode. Whenever nvSRAM enters into sleep mode, it initiates non volatile STORE cycle which results in losing an endurance cycle per sleep command execution. A STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. The nvSRAM enters into sleep mode as follows: 1. The Master sends a START command. 2. The Master sends Control Registers Slave device ID with I2C Write bit set (R/W = ‘0’). Document Number: 001-65232 Rev. *D Page 8 of 30 CY14C512J CY14B512J CY14E512J 4. The Master sends Command Register address (0xAA). 5. The Slave (nvSRAM) sends an ACK back to the Master. 6. The Master sends Command Register byte for entering into Sleep mode. 7. The Slave (nvSRAM) sends an ACK back to the Master. 8. The Master generates a STOP condition. Figure 10. AutoStore Mode VCC 0.1 uF VCC Once in Sleep mode the device starts consuming IZZ current tSLEEP time after SLEEP instruction is registered. The device is not accessible for normal operations until it is out of sleep mode. The nvSRAM wakes up after tWAKE duration after the device slave address is transmitted by the master. Transmitting any of the two slave addresses wakes the nvSRAM from Sleep mode. The nvSRAM device is not accessible during tSLEEP and tWAKE interval, and any attempt to access the nvSRAM device by the master is ignored and nvSRAM sends NACK to the master. As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. Write Protection (WP) The WP pin is an active high pin and protects entire memory and all registers from write operations. To inhibit all the write operations, this pin must be held high. When this pin is high, all memory and register writes are prohibited and address counter is not incremented. This pin is internally pulled LOW and hence can be left open if not used. AutoStore Operation The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap cells during power-down. This STORE makes use of an external capacitor (VCAP) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from VCC to charge the capacitor connected to the VCAP pin. When the voltage on the VCC pin drops below VSWITCH during power-down, the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the VCAP capacitor. The AutoStore operation is not initiated if no write cycle has been performed since the last STORE or RECALL. VCAP VSS VCAP Hardware STORE and HSB pin Operation The HSB pin in CY14X512J is used to control and acknowledge STORE operations. If no STORE or RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the device conditionally initiates a STORE operation after tDELAY duration. An actual STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for tSTORE duration or as long as HSB pin is LOW. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. Note For successful last data byte STORE, a hardware STORE should be initiated at least one clock cycle after the last data bit D0 is received. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB pin unconnected if not used. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled by issuing the AutoStore Disable instruction specified in Command Register on page 8. If AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This will corrupt the data stored in nvSRAM as well as the serial number and it will unlock the SNL bit. During power-up, when VCC crosses VSWITCH, an automatic RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM. The data would previously have been stored on the nonvolatile memory through a STORE sequence. Figure 10 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 18 for the size of the VCAP. A Power-Up RECALL cycle takes tFA time to complete and the memory access is disabled during this time. HSB pin can be used to detect the Ready status of the device. Document Number: 001-65232 Rev. *D Hardware RECALL (Power-Up) Page 9 of 30 CY14C512J CY14B512J CY14E512J Write Operation The last bit of the slave device address indicates a read or a write operation. In case of a write operation, the slave device address is followed by the memory or register address and data. A write operation continues as long as a STOP or Repeated START condition is generated by the master or if a NACK is issued by the nvSRAM. A NACK is issued from the nvSRAM under the following conditions: 1. A valid Device ID is not received. 2. A write (burst write) access to a protected memory block address returns a NACK from nvSRAM after the data byte is received. However, the address counter is set to this address and the following current read operation starts from this address. 3. A write/random read access to an invalid or out-of-bound memory address returns a NACK from the nvSRAM after the address is received. The address counter remains unchanged in such a case. After a NACK is sent out from the nvSRAM, the write operation is terminated and any data on the SDA line is ignored till a STOP or a Repeated START condition is generated by the master. For example, consider a case where the burst write access is performed on Control Register Slave address 0x01 for writing the serial number and continued to the address 0x09, which is a read only register. The device returns a NACK and address counter will not be incremented. A following read operation will be started from the address 0x09. Further, any write operation which starts from a write protected address (say, 0x09) will be responded by the nvSRAM with a NACK after the data byte is sent and set the address counter to this address. A following read operation will start from the address 0x09 in this case also. Note In case the user tries to read/write access an address that does not exist (for example 0x0D in Control Register Slave), nvSRAM responds with a NACK immediately after the out-of-bound address is transmitted. The address counter remains unchanged and holds the previous successful read or write operation address. A write operation is performed internally with no delay after the eighth bit of data is transmitted. If a write operation is not intended, the master must terminate the write operation before the eighth clock cycle by generating a STOP or Repeated START condition. More details on write instruction are provided in Section Memory Slave Access on page 10. Read Operation immediately after the slave device address byte is sent out by the master. The read operation starts from the current address location (the location following the previous successful write or read operation). When the last address is reached, the address counter loops back to the first address. In case of the Control Register Slave, whenever a burst read is performed such that it flows to a non-existent address, the reads operation will loop back to 0x00. This is applicable, in particular for the Command Register. There are the following ways to end a read operation: 1. The Master issues a NACK on the 9th clock cycle followed by a STOP or a Repeated START condition on the 10th clock cycle. 2. Master generates a STOP or Repeated START condition on the 9th clock cycle. More details on write instruction are provided in Section Memory Slave Access on page 10. Memory Slave Access The following sections describe the data transfer sequence required to perform Read or Write operations from nvSRAM. Write nvSRAM Each write operation consists of a slave address being transmitted after the start condition. The last bit of slave address must be set as ‘0’ to indicate a Write operation. The master may write one byte of data or continue writing multiple consecutive address locations while the internal address counter keeps incrementing automatically. The address register is reset to 0x0000 after the last address in memory is accessed. The write operation continues till a STOP or Repeated START condition is generated by the master or a NACK is issued by the nvSRAM. A write operation is executed only after all the 8 data bits have been received by the nvSRAM. The nvSRAM sends an ACK signal after a successful write operation. A write operation may be terminated by the master by generating a STOP condition or a Repeated START operation. If the master desires to abort the current write operation without altering the memory contents, this should be done using a START/STOP condition prior to the 8th data bit. If the master tries to access a write protected memory address on the nvSRAM, a NACK is returned after the data byte intended to write the protected address is transmitted and address counter will not be incremented. Similarly, in a burst mode write operation, a NACK is returned when the data byte that attempts to write a protected memory location and the address counter will not be incremented. If the last bit of the slave device address is ‘1’, a read operation is assumed and the nvSRAM takes control of the SDA line Document Number: 001-65232 Rev. *D Page 10 of 30 CY14C512J CY14B512J CY14E512J Figure 11. Single-Byte Write into nvSRAM (except Hs-mode) S T A R T By Master SDA Line Most Significant Address Byte Memory Slave Address S 1 0 1 0 A2 A1 A0 Least Significant Address Byte S T 0 P Data Byte P 0 By nvSRAM A A A A Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode) SDA Line S 1 0 1 Least Significant Address Byte Most Significant Address Byte Data Byte 1 S T 0 P Data Byte N ~ ~ By Master S T A R Memory Slave Address T 0 A2 A1 A0 0 P By nvSRAM A A A A A Figure 13. Single-Byte Write into nvSRAM (Hs-mode) S T A R T By Master SDA Line Hs-mode command S 0 0 0 0 1 Most Significant Address Byte Memory Slave Address X X X Sr 1 0 Least Significant Address Byte S T 0 P Data Byte P 1 0 A2 A1 A0 0 By nvSRAM A A A A A Figure 14. Multi-Byte Write into nvSRAM (Hs-mode) SDA Line Hs-mode command S 0 0 0 0 1 Most Significant Address Byte Memory Slave Address X X X Sr 1 0 Least Significant Address Byte Data Byte 1 ~ ~ By Master S T A R T 1 0 A2 A1 A0 0 By nvSRAM A By Master A By nvSRAM ~ ~ SDA Line A Document Number: 001-65232 Rev. *D A A S T 0 P Data Byte N Data Byte 3 Data Byte 2 A A P A Page 11 of 30 CY14C512J CY14B512J CY14E512J terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the address 0x0000. The valid methods of terminating read access are described in Section Read Operation on page 10. Current nvSRAM Read Each read operation starts with the master transmitting the nvSRAM slave address with the LSB set to ‘1’ to indicate “Read”. The reads start from the address on the address counter. The address counter is set to the address location next to the last accessed with a “Write” or “Read” operation. The master may Figure 15. Current Location Single-Byte nvSRAM Read (except Hs-mode) S T A R T By Master SDA Line A Memory Slave Address S 1 1 0 0 S T 0 P P A2 A1 A0 1 By nvSRAM Data Byte A Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs-mode) SDA Line S A A Memory Slave Address 1 0 1 0 A2 A1 A0 1 By nvSRAM S T 0 P P ~ ~ By Master S T A R T Data Byte N Data Byte A Figure 17. Current Location Single-Byte nvSRAM Read (Hs-mode) By Master SDA Line S T A R T Hs-mode command S 0 0 0 0 1 S A T 0 P Memory Slave Address X X X Sr 1 0 P 1 0 A2 A1 A0 1 By nvSRAM A A Data Byte Figure 18. Current Location Multi-Byte nvSRAM Read (Hs-mode) SDA Line A Hs-mode command S 0 0 0 0 1 X X X Sr 1 0 1 0 A2 A1 A0 1 Data Byte By nvSRAM A Document Number: 001-65232 Rev. *D A Memory Slave Address ~ ~ By Master S T A R T S T 0 P P Data Byte N A Page 12 of 30 CY14C512J CY14B512J CY14E512J Random Address Read A random address read is performed by first initiating a write operation and generating a Repeated START immediately after the last address byte is acknowledged. The address counter is set to this address and the next read access to this slave will initiate read operation from here. The master may terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the start address 0x0000. Figure 19. Random Address Single-Byte Read (except Hs-mode) S T A R T By Master SDA Line Most Significant Address Byte Memory Slave Address S 1 1 0 Least Significant Address Byte A Memory Slave Address 0 A2 A1 A0 0 0 Sr 1 1 S T 0 P P 0 A2 A1 A0 1 By nvSRAM Data Byte A A A A Figure 20. Random Address Multi-Byte Read (except Hs-mode) SDA Line S 1 0 1 Least Significant Address Byte Most Significant Address Byte Memory Slave Address A Memory slave Address 0 A2 A1 A0 0 Sr 1 0 1 0 A2 A1 A0 1 By nvSRAM Data Byte 1 A A S T 0 P A ~ ~ By Master S T A R T A A P Data Byte N Figure 21. Random Address Single-Byte Read (Hs-mode) SDA Line Hs-mode command S 0 0 0 0 1 Most Significant Address Byte Memory Slave Address X X X Sr 1 0 Least Significant Address Byte Memory Slave Address 1 0 A2 A1 A0 0 Sr 1 0 1 0 A2 A1 A0 1 ~ ~ By Master S T A R T By nvSRAM A A A A A S T A 0 P P Data Byte Document Number: 001-65232 Rev. *D Page 13 of 30 CY14C512J CY14B512J CY14E512J Figure 22. Random Address Multi-Byte Read (Hs-mode) SDA Line Hs-mode command S 0 0 0 0 1 Most Significant Address Byte Memory Slave Address X X X Sr 1 0 Least Significant Address Byte Memory Slave Address Sr 1 0 1 0 A2 A1 A0 0 1 0 A2 A1 A0 1 ~ ~ By Master S T A R T By nvSRAM A A A A A A S T 0 P P ~ ~ Data Byte A Data Byte N Control Registers Slave The following sections describes the data transfer sequence required to perform Read or Write operations from Control Registers Slave. Write Control Registers To write the Control Registers Slave, the master transmits the Control Registers Slave address after generating the START condition. The write sequence continues from the address location specified by the master till the master generates a STOP condition or the last writable address location. If a non writable address location is accessed for write operation during a normal write or a burst, the slave generates a NACK after the data byte is sent and the write sequence terminates. Any following data bytes are ignored and the address counter is not incremented. If a write operation is performed on the Command Register (0xAA), the following current read operation also begins from the first address (0x00) as in this case, the current address is an out-of-bound address. The address is not incremented and the next current read operation begins from this address location. If a write operation is attempted on an out-of-bound address location, the nvSRAM sends a NACK immediately after the address byte is sent. Further, if the serial number is locked, only two addresses (0xAA or Command Register, and 0x00 or Memory Control Register) are writable in the Control Registers Slave. On a write operation to any other address location, the device will acknowledge command byte and address bytes but it returns a NACK from the Control Registers Slave for data bytes. In this case, the address will not be incremented and a current read will happen from the last acknowledged address. The nvSRAM Control Registers Slave sends a NACK when an out of bound memory address is accessed for write operation, by the master. In such a case, a following current read operation begins from the last acknowledged address. Figure 23. Single-Byte Write into Control Registers S T A R T By Master SDA Line S Control Registers Slave Address 0 0 1 Control Register Address S T 0 P Data Byte P 1 A2 A1 A0 0 By nvSRAM A A A Figure 24. Multi-Byte Write into Control Registers SDA Line S Control Registers Slave Address 0 0 1 Control Register Address Data Byte 1 A2 A1 A0 0 By nvSRAM A Document Number: 001-65232 Rev. *D S T 0 P Data Byte N P ~ ~ By Master S T A R T A A A Page 14 of 30 CY14C512J CY14B512J CY14E512J Current Control Registers Read A read of Control Registers Slave is started with master sending the Control Registers Slave address after the START condition with the LSB set to ‘1’. The reads begin from the current address which is the next address to the last accessed location. The reads to Control Registers Slave continues till the last readable address location and loops back to the first location (0x00). Note that the Command Register is a write only register and is not accessible through the sequential read operations. If a burst read operation begins from the Command Register (0xAA), the address counter wraps around to the first address in the register map (0x00). Figure 25. Control Registers Single-Byte Read S T A R T By Master SDA Line S Control Registers Slave Address 0 0 1 A S T 0 P P 1 A2 A1 A0 1 By nvSRAM Data Byte A Figure 26. Current Control Registers Multi-Byte Read S T A R T SDA Line S 0 0 1 A A 1 A2 A1 A0 1 ~ ~ By Master Control Registers Slave Address By nvSRAM Data Byte S T 0 P P Data Byte N A Random Control Registers Read A read of random address may be performed by initiating a write operation to the intended location of read and immediately following with a Repeated START operation. The reads to Control Registers Slave continues till the last readable address location and loops back to the first location (0x00). Note that the Command Register is a write only register and is not accessible through the sequential read operations. A random read starting at the Command Register (0xAA) loops back to the first address in the Control Registers map (0x00). If a random read operation is initiated from an out-of-bound memory address, the nvSRAM sends a NACK after the address byte is sent. . Figure 27. Random Control Registers Single-Byte Read By Master SDA Line S T A R T S Control Registers Slave Address 0 0 1 Control Register Address A Control Registers Slave Address Sr 0 1 A2 A1 A0 0 0 1 1 A2 A1 A0 1 S T 0 P P By nvSRAM Data Byte A Document Number: 001-65232 Rev. *D A A Page 15 of 30 CY14C512J CY14B512J CY14E512J Figure 28. Random Control Registers Multi-Byte Read SDA Line S Control Registers Slave Address 0 0 1 Control Register Address A Control Registers Slave Address Sr 0 1 A2 A1 A0 0 0 1 1 A2 A1 A0 1 ~ ~ By Master S T A R T By nvSRAM Data Byte A A A A S T 0 P P Data Byte N Serial Number Serial number is an 8 byte memory space provided to the user to uniquely identify this device. It typically consists of a two byte customer ID, followed by five bytes of unique serial number and one byte of CRC check. However, nvSRAM does not calculate the CRC and it is up to the user to utilize the eight byte memory space in the desired format. The default values for the eight byte locations are set to ‘0x00’. Serial Number Write The serial number can be accessed through the Control Registers Slave Device. To write the serial number, master transmits the Control Registers Slave address after the START condition and writes to the address location from 0x01 to 0x08. The content of Serial Number registers is secured to nonvolatile memory on the next STORE operation. If AutoStore is enabled, nvSRAM automatically stores the Serial number in the nonvolatile memory on power-down. However, if AutoStore is disabled, user must perform a STORE operation to secure the contents of Serial Number registers. Note If the serial number lock (SNL) bit is not set, the serial number registers can be re-written regardless of whether or not a STORE has happened. Once the serial number lock bit is set, no writes to the serial number registers are allowed. If the master tries to perform a write operation to the serial number registers Document Number: 001-65232 Rev. *D when the lock bit is set, a NACK is returned and write will not be performed. Serial Number Lock After writes to Serial Number registers is complete, master is responsible for locking the serial number by setting the serial number lock bit to ‘1’ in the Memory Control Register (0x00). The content of Memory Control Register and serial number are secured on the next STORE operation (STORE or AutoStore). If AutoStore is not enabled, user must perform STORE operation to secure the lock bit status. If a STORE was not performed, the serial number lock bit will not survive power cycle. The serial number lock bit and 8 - byte serial number is defaults to ‘0’ at power-up. Serial Number Read Serial number can be read back by a read operation of the intended address of the Control Registers Slave. The Control Registers Device loops back from the last address (excluding the Command Register) to 0x00 address location while performing burst read operation. The serial number resides in the locations from 0x01 to 0x08. Even if the serial number is not locked, a serial number read operation will return the current values written to the serial number registers. Master may perform a serial number read operation to confirm if the correct serial number is written to the registers before setting the lock bit. Page 16 of 30 CY14C512J CY14B512J CY14E512J Device ID Device ID is a 4 byte code consisting of JEDEC assigned manufacturer ID, product ID, density ID, and die revision. These registers are set in the factory and are read only registers for the user. Table 6. Device ID Device Device ID (4 bytes) CY14C512J1 CY14C512J2 CY14C512J3 CY14B512J1 CY14B512J2 CY14B512J3 CY14E512J1 CY14E512J2 CY14E512J3 0x06812098 0x0681A098 0x0681A298 0x06812898 0x0681A898 0x0681AA98 0x06813098 0x0681B098 0x0681B298 Device ID Description 20–7 6–3 (14 bits) (4 bits) Product ID Density ID 00001001000001 0011 00001101000001 0011 00001101000101 0011 00001001010001 0011 00001101010001 0011 00001101010101 0011 00001001100001 0011 00001101100001 0011 00001101100101 0011 31–21 (11 bits) Manufacture ID 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 2–0 (3 bits) Die Rev 000 000 000 000 000 000 000 000 000 The device ID is divided into four parts as shown in Table 6: 4. Die Rev (3 bits) 1. Manufacturer ID (11 bits) This is used to represent any major change in the design of the product. The initial setting of this is always 0x0. This is the JEDEC assigned manufacturer ID for Cypress. JEDEC assigns the manufacturer ID in different banks. The first three bits of the manufacturer ID represent the bank in which ID is assigned. The next eight bits represent the manufacturer ID. Executing Commands Using Command Register The Control Registers Slave allows different commands to be executed by writing the specific command byte in the Command Register (0xAA). The command byte codes for each command are specified in Table 5 on page 8. During the execution of these commands the device is not accessible and returns a NACK if any of the three slave devices is selected. If an invalid command is sent by the master, the nvSRAM responds with an ACK indicating that the command has been acknowledged with NOP (No Operation). The address will rollover to 0x00 location. Cypress manufacturer ID is 0x34 in bank 0. Therefore the manufacturer ID for all Cypress nvSRAM products is given as: Cypress ID - 000_0011_0100 2. Product ID (14 bits) The product ID for device is shown in the Table 6. 3. Density ID (4 bits) The 4 bit density ID is used as shown in Table 6 for indicating the 512 Kb density of the product. Figure 29. Command Execution using Command Register By Master SDA Line S T A R T S Control Register Slave Address 0 0 1 Command Register Address 1 A2 A1 A0 0 1 0 1 0 1 0 1 S T O P Command Byte P 0 By nvSRAM A Document Number: 001-65232 Rev. *D A A Page 17 of 30 CY14C512J CY14B512J CY14E512J Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount lead soldering temperature (3 seconds) ......................................... +260 C At 150 C ambient temperature ...................... 1000 h DC output current (1 output at a time, 1s duration). .... 15 mA At 85 C ambient temperature .................... 20 Years Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Ambient temperature with power applied .......................................... –55 C to +150 C Supply voltage on VCC relative to VSS CY14C512J: .....................................–0.5 V to +3.1 V CY14B512J: ......................................–0.5 V to +4.1 V CY14E512J: ......................................–0.5 V to +7.0 V DC voltage applied to outputs in High Z state .................................... –0.5 V to VCC + 0.5 V Input voltage ....................................... –0.5 V to VCC + 0.5 V Latch up current .................................................... > 140 mA Operating Range Ambient Temperature Product Range CY14C512J Industrial VCC –40 C to +85 C 2.4 V to 2.6 V CY14B512J 2.7 V to 3.6 V CY14E512J 4.5 V to 5.5 V DC Electrical Characteristics Over the Operating Range Parameter Description VCC Power supply Test Conditions CY14C512J CY14B512J CY14E512J fSCL = 3.4 MHz; Values obtained without output loads (IOUT = 0 mA) CY14C512J fSCL = 1 MHz; Values obtained without CY14B512J output loads (IOUT = 0 CY14E512J mA) Min 2.4 2.7 4.5 – Typ [3] 2.5 3.0 5.0 – Max 2.6 3.6 5.5 1 Unit V V V mA – – 400 A – – 450 A Average VCC current during STORE Average VCAP current during AutoStore cycle All inputs don’t care, VCC = Max Average current for duration tSTORE All inputs don’t care. Average current for duration tSTORE – – 3 mA – – 3 mA ISB VCC standby current – – 150 A IZZ Sleep mode current SCL > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. fSCL = 0 MHz. tSLEEP time after SLEEP Instruction is Issued. All inputs are static and configured at CMOS logic level. – – 8 A IIX[4] Input current in each I/O pin 0.1 VCC < VI < 0.9 VCC(max) (except HSB) Input current in each I/O pin (for HSB) –1 – +1 A –100 – +1 A –1 – – – +1 7 A pF ICC1 ICC2 ICC4 IOZ CI Average VCC current Output leakage current Capacitance for each I/O pin Capacitance measured across all input and output signal pin and VSS. Notes 3. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested. 4. Not applicable to WP, A2, A1 and A0 pins. Document Number: 001-65232 Rev. *D Page 18 of 30 CY14C512J CY14B512J CY14E512J DC Electrical Characteristics (continued) Over the Operating Range Parameter Description VIH Input HIGH voltage VIL VOL RIN[5] VHYS VCAP[6] VVCAP[7, 8] Min 0.7 × Vcc Typ [3] – Max VCC + 0.5 Unit V – 0.5 0 50 1 0.05 × VCC – – – – – 0.3 × Vcc 0.4 – – – V V k M V CY14C512J CY14B512J CY14E512J 170 42 220 47 270 180 F F CY14C512J CY14B512J CY14E512J – – VCC V – – VCC– 0.5 V Test Conditions Input LOW voltage Output LOW voltage IOL= 3 mA Input resistance (WP, A2, A1, A0) For VIN = VIL (max) For VIN = VIH (min) Hysteresis of Schmitt trigger inputs Storage capacitor Between VCAP pin and VSS Maximum voltage driven on VCAP VCC = Max pin by the device Data Retention and Endurance Over the Operating Range Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Thermal Resistance Parameter [8] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions 8-pin SOIC 16-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 101.08 56.68 C/W 37.86 32.11 C/W Notes 5. The input pull-down circuit is stronger (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH. 6. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. 7. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating temperature range should be higher than the VVCAP voltage. 8. These parameters are guaranteed by design and are not tested. Document Number: 001-65232 Rev. *D Page 19 of 30 CY14C512J CY14B512J CY14E512J AC Test Loads and Waveforms Figure 30. AC Test Loads and Waveforms For 3.0 V (CY14B512J) For 2.5 V (CY14C512J) For 5.0 V (CY14E512J) 3.0 V 2.5 V 867 700 OUTPUT OUTPUT 100 pF 5.0 V 1.6 K OUTPUT 100 pF 50 pF AC Test Conditions Description Input pulse levels Input rise and fall times (10%–90%) Input and output timing reference levels Document Number: 001-65232 Rev. *D CY14C512J 0 V to 2.5 V 10 ns 1.25 V CY14B512J 0 V to 3 V 10 ns 1.5 V CY14E512J 0 V to 5 V 10 ns 2.5 V Page 20 of 30 CY14C512J CY14B512J CY14E512J AC Switching Characteristics Over the Operating Range Parameter [9] 3.4 MHz [10] Description 1 MHz [10] 400 kHz [10] Unit Min Max Min Max Min Max – 3400 – 1000 – 400 kHz fSCL Clock frequency, SCL tSU; STA Setup time for Repeated START condition 160 – 250 – 600 – ns tHD;STA Hold time for START condition 160 – 250 – 600 – ns tLOW LOW period of the SCL 160 – 500 – 1300 – ns tHIGH HIGH period of the SCL 60 – 260 – 600 – ns tSU;DATA Data in setup time 10 – 100 – 100 – ns tHD;DATA Data hold time (In/Out) 0 – 0 – 0 – ns tDH Data out hold time 0 – 0 – 0 – ns [11] Rise time of SDA and SCL – 80 – 120 – 300 ns tf[11] Fall time of SDA and SCL – 80 – 120 – 300 ns tSU;STO Setup time for STOP condition 160 – 250 – 600 – ns tVD;DATA Data output valid time – 130 – 400 – 900 ns tVD;ACK ACK output valid time – 130 – 400 – 900 ns tOF[11] Output fall time from VIH min to VILmax – 80 – 120 – 300 ns tBUF Bus free time between STOP and next START condition 0.3 – 0.5 – 1.3 – µs tSP Pulse width of spikes that must be suppressed by input filter – 10 – 50 – 50 ns tr Switching Waveforms ~ ~ ~ ~ ~ ~ Figure 31. Timing Diagram t SU;DATA ~ ~ ~ ~ t HIGH ~ ~ tr t LOW ~ ~ SDA tf t VD;DAT t SP t HD;STA t VD;ACK t BUF t SU;STO t HD;DATA tf t SU;STA ~ ~ t HD;STA ~ ~ SCL S Sr START condition Repeated START condition tr 9th clock (ACK) P S STOP condition START condition Notes 9. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL and load capacitance shown in Figure 30. 10. Bus Load (Cb) Considerations; Cb < 500 pF for I2C clock frequency (SCL) 100/400/1000 kHz; Cb < 100 pF for SCL at 3.4 MHz. 11. These parameters are guaranteed by design and are not tested. Document Number: 001-65232 Rev. *D Page 21 of 30 CY14C512J CY14B512J CY14E512J nvSRAM Specifications Over the Operating Range Parameter Description tFA [12] Power-Up RECALL duration tSTORE [13] tDELAY[14] tVCCRISE[15] VSWITCH STORE cycle duration Time allowed to complete SRAM write cycle VCC rise time Low voltage trigger level tLZHSB[15] VHDIS[15] tHHHD[15] tWAKE HSB high to nvSRAM active time HSB output disable voltage HSB HIGH active time Time for nvSRAM to wake up from SLEEP mode tSLEEP tSB[15] Time to enter low power mode after issuing SLEEP instruction Time to enter into standby mode after issuing STOP condition CY14C512J CY14B512J CY14E512J CY14C512J CY14B512J CY14E512J CY14C512J CY14B512J CY14E512J Min Max Unit – – – – – 150 – – – – – – – – – – – 40 20 20 8 25 – 2.35 2.65 4.40 5 1.9 500 40 20 20 8 100 ms ms ms ms ns µs V V V µs V ns ms ms ms ms µs Switching Waveforms Figure 32. AutoStore or Power-Up RECALL [16] VCC VSWITCH VHDIS t VCCRISE tHHHD Note 13 tSTORE Note tHHHD 17 Note 13 tSTORE 17 Note HSB OUT tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL tFA tFA Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 12. tFA starts from the time VCC rises above VSWITCH. 13. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 14. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 15. These parameters are guaranteed by design and are not tested. 16. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 17. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document Number: 001-65232 Rev. *D Page 22 of 30 CY14C512J CY14B512J CY14E512J Software Controlled STORE/RECALL Cycles Over the Operating Range Parameter CY14X512J Description Min Max Unit tRECALL RECALL duration – 600 µs tSS[18, 19] Software sequence processing time – 500 µs Switching Waveforms Figure 33. Software STORE/RECALL Cycle [19] DATA OUTPUT BY MASTER Command Reg Address nvSRAM Control Slave Address acknowledge (A) by Slave acknowledge (A) by Slave SCL FROM MASTER 1 2 8 9 1 Command Byte (STORE/RECALL) 2 8 9 1 acknowledge (A) by Slave 2 8 9 P S START condition RWI t STORE / t RECALL Figure 34. AutoStore Enable/Disable Cycle DATA OUTPUT BY MASTER Command Reg Address nvSRAM Control Slave Address acknowledge (A) by Slave acknowledge (A) by Slave SCL FROM MASTER 1 2 8 9 1 Command Byte (ASENB/ASDISB) 2 8 9 1 acknowledge (A) by Slave 2 8 9 P S START condition RWI t SS Notes 18. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 19. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. Document Number: 001-65232 Rev. *D Page 23 of 30 CY14C512J CY14B512J CY14E512J Hardware STORE Cycle Over the Operating Range Parameter tPHSB CY14X512J Description Hardware STORE pulse width Min Max 15 – Unit ns Switching Waveforms Figure 35. Hardware STORE Cycle [20] Write Latch set ~ ~ tPHSB HSB (IN) tSTORE tHHHD ~ ~ tDELAY HSB (OUT) tLZHSB RWI tPHSB HSB (IN) HSB pin is driven HIGH to VCC only by Internal 100 K: resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. tDELAY RWI ~ ~ HSB (OUT) ~ ~ Write Latch not set Note 20. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated. Document Number: 001-65232 Rev. *D Page 24 of 30 CY14C512J CY14B512J CY14E512J Ordering Information Ordering Code Package Diagram CY14B512J2-SXIT 51-85066 Package Type Operating Range 8-pin SOIC (with VCAP) Industrial CY14B512J2-SXI All these parts are Pb-free. This table contains Final information. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 14 B 512 J 2 - S X I T Option: T - Tape and Reel Blank - Std. Temperature: I - Industrial (–40 to 85°C) Pb-free 1 - Without VCAP 2 - With VCAP 3 - With VCAP and HSB Package: S - 8-pin SOIC SF - 16-pin SOIC J - Serial (I2C) nvSRAM Density: Voltage: C - 2.5 V B - 3.0 V E - 5.0 V 512 - 512 Kb 14 - nvSRAM Cypress Document Number: 001-65232 Rev. *D Page 25 of 30 CY14C512J CY14B512J CY14E512J Package Diagrams Figure 36. 8-pin SOIC (150 mils) Package Outline, 51-85066 51-85066 *E Document Number: 001-65232 Rev. *D Page 26 of 30 CY14C512J CY14B512J CY14E512J Package Diagrams (continued) Figure 37. 16-pin SOIC (0.413 × 0.299 × 0.0932) Inches Package Outline, 51-85022 51-85022 *D Document Number: 001-65232 Rev. *D Page 27 of 30 CY14C512J CY14B512J CY14E512J Acronyms Acronym Document Conventions Description Units of Measure ACK acknowledge CMOS complementary metal oxide semiconductor °C degree Celsius CRC cyclic redundancy check Hz hertz EIA electronic industries alliance I2C kHz kilohertz inter-integrated circuit k kilohm I/O input/output Mbit megabit JEDEC joint electron devices engineering council MHz megahertz LSB least significant bit M megaohm MSB most significant bit A microampere nvSRAM nonvolatile static random access memory F microfarad NACK no acknowledge s microsecond RoHS restriction of hazardous substances mA milliampere R/W read/write ms millisecond RWI read and write inhibit ns nanosecond SCL serial clock line ohm SDA serial data access % percent SNL serial number lock pF picofarad SOIC small outline integrated circuit V volt SRAM static random access memory W watt WP write protect Document Number: 001-65232 Rev. *D Symbol Unit of Measure Page 28 of 30 CY14C512J CY14B512J CY14E512J Document History Page Document Title: CY14C512J, CY14B512J, CY14E512J, 512-Kbit (64 K × 8) Serial (I2C) nvSRAM Document Number: 001-65232 Rev. ECN No. Submission Date Orig. of Change ** 3089600 11/18/2010 GVCH New data sheet. *A 3201524 03/21/2011 GVCH Updated Configuration (Added Slave Address information). Updated AutoStore Operation (description). Updated Hardware STORE and HSB pin Operation (Added more clarity on HSB pin operation). Updated Table 6 (Product ID column). Updated nvSRAM Specifications (description of tLZHSB parameter). Fixed Typo error in Figure 32. Updated Ordering Code Definitions. Updated in new template. *B 3248510 05/04/2011 GVCH Datasheet status changed from “Preliminary” to “Final” *C 3390041 11/28/2011 GVCH Updated Pin Definitions (SDA pin description). Updated Command Register (SLEEP description on page 8). Updated Device ID (Added device ID (4 bytes) column in Table 6). Updated Executing Commands Using Command Register (description). Updated DC Electrical Characteristics (Added ICC1 parameter value for 1 MHz frequency, changed maximum value of ICC2 parameter value from 2 mA to 3 mA, removed ICC3 parameter, and added Note 6 and referred the note in the VCAP parameter). Updated AC Switching Characteristics (Added Note 9 and referred the note in the Parameter column, and updated maximum value of tSP parameter from 5 ns to 10 ns for 3.4 MHz). Updated Software Controlled STORE/RECALL Cycles (Updated Figure 33 and Figure 34). Updated Package Diagrams. *D 3631817 07/24/2012 GVCH Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note 7 and referred the same note in VVCAP parameter, also referred Note 8 in VVCAP parameter). Document Number: 001-65232 Rev. *D Description of Change Page 29 of 30 CY14C512J CY14B512J CY14E512J Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2012. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-65232 Rev. *D Revised July 24, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 30 of 30