CYPRESS CY14C101J_1105

CY14C101J
CY14B101J, CY14E101J
2
1-Mbit (128 K × 8) Serial (I C) nvSRAM
1-Mbit (128 K × 8) Serial (I2C) nvSRAM
Features
■
■
1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14X101J1)
❐
❐
■
■
■
Industry standard configurations
❐ Operating voltages:
• CY14C101J: VCC = 2.4 V to 2.6 V
• CY14B101J: VCC = 2.7 V to 3.6 V
• CY14E101J: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8- and 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C101J/CY14B101J/CY14E101J combines a
1-Mbit nvSRAM[1] with a nonvolatile element in each memory
cell. The memory is organized as 128 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X101J1). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through I2C commands.
High reliability
❐
■
■
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
High speed I2C interface
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast-mode Plus: 1 MHz speed
❐ High speed: 3.4 MHz
❐ Zero cycle delay reads and writes
Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for 1/4, 1/2, or entire array
I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8 byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
Configuration
Low power consumption
❐ Average active current of 1 mA at 3.4 MHz operation
❐ Average standby mode current of 150 µA
❐ Sleep mode current of 8 µA
Feature
Logic Block Diagram
CY14X101J1 CY14X101J2 CY14X101J3
AutoStore
No
Yes
Yes
Software STORE
Yes
Yes
Yes
Hardware STORE
No
No
Yes
Serial Number
8x8
VCC VCAP
Manufacture ID/
Product ID
Power Control
Block
Memory Control Register
Quantrum Trap
128 K x 8
Command Register
Sleep
SDA
SCL
A2, A1
WP
Control Registers Slave
2
I C Control Logic
Slave Address
Decoder
Memory Slave
Memory
Address and Data
Control
SRAM
128 K x 8
STORE
RECALL
Note
1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation
Document #: 001-54050 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2011
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CY14C101J
CY14B101J, CY14E101J
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
I2C Interface ...................................................................... 4
Protocol Overview ............................................................ 4
I2C Protocol – Data Transfer ....................................... 4
Data Validity ...................................................................... 5
START Condition (S) ........................................................ 5
STOP Condition (P) .......................................................... 5
Repeated START (Sr) ....................................................... 5
Byte Format ....................................................................... 5
Acknowledge / No-acknowledge ..................................... 5
High-Speed Mode (Hs-mode) .......................................... 6
Serial Data Format in Hs-mode ................................... 6
Slave Device Address ...................................................... 7
Memory Slave Device ................................................. 7
Control Registers Slave Device ................................... 7
Memory Control Register ............................................ 8
Command Register ..................................................... 8
Write Protection (WP) ....................................................... 9
AutoStore Operation ........................................................ 9
Hardware STORE and HSB pin Operation ..................... 9
Hardware RECALL (Power-Up) .................................. 9
Write Operation ............................................................... 10
Read Operation ............................................................... 10
Memory Slave Access .................................................... 10
Write nvSRAM ........................................................... 10
Current nvSRAM Read .............................................. 12
Random Address Read ............................................. 13
Control Registers Slave ................................................. 14
Write Control Registers ................................................. 14
Current Control Registers Read ................................ 15
Random Control Registers Read .............................. 15
Document #: 001-54050 Rev. *F
Serial Number ................................................................. 16
Serial Number Write .................................................. 16
Serial Number Lock ................................................... 16
Serial Number Read .................................................. 16
Device ID Read ......................................................... 17
Executing Commands Using Command Register ....... 17
Best Practices ................................................................. 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
DC Electrical Characteristics ........................................ 19
Data Retention and Endurance ..................................... 20
Thermal Resistance ........................................................ 20
AC Test Conditions ........................................................ 21
AC Switching Characteristics ....................................... 22
nvSRAM Specifications ................................................. 23
Software Controlled STORE/RECALL Cycles .............. 24
Hardware STORE Cycle ................................................. 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
Page 2 of 31
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CY14C101J
CY14B101J, CY14E101J
Pinouts
Figure 1. Pin Diagram – 8-pin SOIC
[2]
NC
1
A1
2
A2
3
VSS
4
CY14X101J1
Top View
not to scale
VCAP
1
WP
A1
2
6
SCL
A2
3
5
SDA
VSS
4
8
VCC
7
CY14X101J2
Top View
not to scale
8
VCC
7
WP
6
SCL
5
SDA
Figure 2. Pin Diagram – 16-pin SOIC
NC
1
16
VCC
NC
2
15
NC
NC
3
14
VCAP
NC
4
13
A2
CY14X101J3
Top View
not to scale
WP
5
12
SDA
NC
6
11
SCL
NC
7
10
A1
8
9
HSB
[2]
VSS
Pin Definitions
Pin Name
I/O Type
Description
Clock. Runs at speeds up to a maximum of fSCL.
SCL
Input
SDA
Input/Output
WP
Input
Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can
be left open if not connected.
A2-A1
Input
Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can
be left open if not connected.
HSB
Input/Output
Hardware STORE Busy
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no
connect. It must never be connected to ground.
NC
No connect
VSS
Power supply
Ground.
VCC
Power supply
Power supply.
I/O. Input/Output of data through I2C interface.
No connect. This pin is not connected to the die.
Note
2. This pin is reserved for lower densities.
Document #: 001-54050 Rev. *F
Page 3 of 31
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CY14C101J
CY14B101J, CY14E101J
I2C Interface
bit slave address and eighth bit (R/W) indicating a read (1) or a
write (0) operation. All signals are transmitted on the open-drain
SDA line and are synchronized with the clock on SCL line. Each
byte of data transmitted on the I2C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after receiving
/transmitting of each byte on the falling edge of 9th clock cycle.
The new address is latched just prior to sending/receiving the
acknowledgment bit. This allows the next sequential byte to be
accessed with no additional addressing. On reaching the last
memory location, the address rolls back to 0x00000 and writes
continue. The slave responds to each byte sent by the master
during a write operation with an ACK. A write sequence can be
terminated by the master generating a STOP or Repeated
START condition.
I2C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) that carry information between multiple devices
on the bus. I2C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to VCC using resistors. The choice of a pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock and all the data
I/Os are transmitted in synchronization with this clock. The
CY14X101J supports up to 3.4 MHz clock speed on SCL line.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates a START condition to initiate the
communication followed by broadcasting a slave select byte.
The slave select byte consists of a seven bit address of the slave
that the master intends to communicate with and R/W bit
indicating a read or a write operation. The selected slave
responds to this with an acknowledgement (ACK). After a slave
is selected, the remaining part of the communication takes place
between the master and the selected slave device. The other
devices on the bus ignore the signals on the SDA line till a STOP
or Repeated START condition is detected. The data transfer is
done between the master and the selected slave device through
the SDA pin synchronized with the SCL clock generated by the
master.
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The
no-acknowledge signal causes the CY14X101J to release the
SDA line and the master can then generate a STOP or a
Repeated START condition to initiate a new operation.
I2C Protocol – Data Transfer
Each transaction in I2C protocol starts with the master
generating a START condition on the bus, followed by a seven
Figure 3. System Configuration using Serial (I2C) nvSRAM
Vcc
RPmin = (VCC - VOLmax) / IOL
RPmax = tr / Cb
SDA
Microcontroller
SCL
Vcc
Vcc
A1
SCL
A1
SCL
A1
SCL
A2
SDA
A2
SDA
A2
SDA
WP
WP
WP
CY14X101J
CY14X101J
CY14X101J
#0
Document #: 001-54050 Rev. *F
#1
#3
Page 4 of 31
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CY14C101J
CY14B101J, CY14E101J
Data Validity
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH, that is, START and STOP condition.
The START and STOP conditions are generated by the master
to signal the beginning and end of a communication sequence
on the I2C bus.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I2C begins
with the master generating a START condition.
If an Repeated START condition is generated instead of a STOP
condition the bus continues to be busy. The ongoing transaction
on the I2C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 4. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
SCL
S
P
STOP Condition
START Condition
Figure 5. Data Transfer on the
I2C
Bus
handbook, full pagewidth
P
SDA
Acknowledgement
signal from slave
MSB
SCL
S
or
Sr
1
START or
Repeated START
condition
2
7
8
ACK
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
Acknowledge / No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I2C bus needs to be responded with an ACK
signal by the receiver to continue the operation. Failing to do so
2
3-8
9
ACK
Byte complete,
interrupt within slave
Each operation in I2C is done using 8 bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
Document #: 001-54050 Rev. *F
1
9
Byte Format
Acknowledgement
signal from receiver
Clock line held LOW while
interrupts are serviced
Sr
Sr
or
P
STOP or
Repeated START
condition
is considered as a NACK state. NACK is the state where receiver
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
■
The master did not receive valid data due to noise
■
The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE
operation in following cases:
■
■
nvSRAM did not receive valid data due to noise.
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Page 5 of 31
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CY14C101J
CY14B101J, CY14E101J
Figure 6. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
not acknowledge (A)
DATA OUTPUT
BY SLAVE
acknowledge (A)
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
High-Speed Mode (Hs-mode)
Serial Data Format in Hs-mode
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device into high speed mode. This enables master slave
communication for speed upto 3.4 MHz. A stop condition exits
Hs-mode.
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
Hs-mode
F/S-mode
S
MASTER CODE
A Sr SLAVE ADD. R/W A
F/S-mode
DATA
n (bytes+ ack.)
A/A P
Hs-mode continues
Sr SLAVE ADD.
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
Document #: 001-54050 Rev. *F
continue data transfer in Hs-mode, the master sends Repeated
START (Sr).
See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode
timings for read and write operation.
Page 6 of 31
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CY14C101J
CY14B101J, CY14E101J
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X101J
reserves two sets of upper 4 MSBs [7:4] in the slave device
address field for accessing Memory and Control Registers. The
accessing mechanism is described in Memory Slave Device on
page 7.
The nvSRAM product provides two different functionalities:
Memory and Control Registers functions (such as serial number
and product ID). The two functions of the device are accessed
through different slave device addresses. The first four most
significant bits [7:4] in the device address register are used to
select between the nvSRAM functions.
Table 1. Slave device Addressing
Bit 7
Bit 6
Bit 5
Bit 4
1
0
1
0
Bit 3
Bit 2
Device Select ID
Bit 1
nvSRAM
Bit 0 Function
Select
A16
R/W Selects Memory
CY14X101J Slave Devices
Memory, 128 K × 8
Control Registers
- Memory Control Register, 1 × 8
0
0
1
1
Device Select ID
X
R/W
- Serial Number, 8 × 8
Selects Control
Registers
- Device ID, 4 × 8
- Command Register, 1 × 8
Memory Slave Device
The nvSRAM device is selected for Read/Write if the master
issues the slave address as 1010b followed by two bits of device
select. If slave address sent by the master matches with the
Memory Slave device address then depending on the R/W bit of
the slave address, data is either read from (R/W = ‘1’) or written
to (R/W = ’0’) the nvSRAM.
The address length for CY14X101J is 17 bits and thus it requires
3 address bytes to map the entire memory address location. To
save an extra byte for memory addressing, the 17th bit (A16) is
mapped to the slave address select bit (A0). The dedicated two
address bytes represent bit A0 to A15.
Figure 8. Memory Slave Device Address
MSB
handbook, halfpage
1
R/W bit of the Slave address, data is either read from (R/W = ‘1’)
or written to (R/W = ‘0’) the device.
Figure 9. Control Registers Slave Device Address
MSB
handbook, halfpage
0
1
0
A2
Slave ID
A1
Device
Select
A16 R/W
MSB of
Address
Control Registers Slave Device
The Control Registers Slave device includes the Serial Number,
Product ID, Memory Control and Command Register.
The nvSRAM Control Register Slave device is selected for
Read/Write if the master issues the Slave address as 0011b
followed by two bits of device select. Then, depending on the
Document #: 001-54050 Rev. *F
0
1
1
A2
A1
X
R/W
Device
Select
Slave ID
Table 2. Control Registers Map
Address
0x00
LSB
0
LSB
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Description
Memory
Control
Register
Serial Number
8 Bytes
Read/Write
Details
Read/Write Contains Block
Protect Bits and Serial
Number Lock bit
Read/Write Programmable Serial
(Read only Number. Locked by
when SNL setting the Serial
is set)
Number lock bit in the
Memory Control
Register to ‘1’.
Page 7 of 31
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CY14C101J
CY14B101J, CY14E101J
Table 5. Command Register Bytes
Table 2. Control Registers Map (continued)
0x09
0x0A
0x0B
0x0C
0x0D
0xAA
Device ID
Read only Device ID is factory
programmed
Reserved
Command
Register
Reserved Reserved
Write only Allows commands for
STORE, RECALL,
AutoStore
Enable/Disable,
SLEEP Mode
Memory Control Register
The Memory Control Register contains the following bits:
■
Bit 6
SNL
(0)
Bit 5
0
Bit 4
0
Bit 3
BP1
(0)
Bit 2
BP0
(0)
Bit 1
0
■
BP1:BP0
00
01
10
11
Block Protection
None
0x18000-0x1FFFF
0x10000-0x1FFFF
0x00000-0x1FFFF
SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to
lock the serial number. Once the bit is set to ‘1’, the serial
number registers are locked and no modification is allowed.
This bit cannot be cleared to ‘0’. The serial number is secured
on the next STORE operation (Software STORE or AutoStore).
If AutoStore is not enabled, user must perform the Software
STORE operation to secure the lock bit status. If a STORE was
not performed, the serial number lock bit will not survive the
power cycle. The default value shipped from the factory for SNL
is ‘0’.
Command Register
The Command Register resides at address “AA” of the Control
Registers Slave device. This is a write only register. The byte
written to this register initiates a STORE, RECALL, AutoStore
Enable, AutoStore Disable and sleep mode operation as listed in
Table 5. Refer to Serial Number on page 16 for details on how to
execute a command register byte.
Document #: 001-54050 Rev. *F
STORE
0110 0000
RECALL
0101 1001
0001 1001
1011 1001
ASENB
ASDISB
SLEEP
STORE SRAM data to nonvolatile
memory
RECALL data from nonvolatile
memory to SRAM
Enable AutoStore
Disable AutoStore
Enter Sleep Mode for low power
consumption
■
RECALL: Initiates nvSRAM Software RECALL. The nvSRAM
cannot be accessed for tRECALL time after this instruction has
been executed. The RECALL operation does not alter the data
in the nonvolatile elements. A RECALL may be initiated in two
ways: Hardware RECALL, initiated on power-up; and Software
RECALL, initiated by a I2C RECALL instruction.
■
ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be
accessed for tSS time after this instruction has been executed.
This setting is not nonvolatile and needs to be followed by a
manual STORE sequence if this is desired to survive the power
cycle. The part comes from the factory with AutoStore Enabled.
■
ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot
be accessed for tSS time after this instruction has been
executed. This setting is not nonvolatile and needs to be
followed by a manual STORE sequence if this is desired to
survive power cycle.
Table 4. Block Protection
Level
0
1/4
1/2
1
Description
STORE: Initiates nvSRAM Software STORE. The nvSRAM
cannot be accessed for tSTORE time after this instruction has
been executed. When initiated, the device performs a STORE
operation regardless of whether a write has been performed
since the last NV operation. After the tSTORE cycle time is
completed, the SRAM is activated again for read and write
operations.
Bit 0
0
BP1:BP0: Block Protect bits are used to protect 1/4, 1/2 or full
memory array. These bits can be written through a write
instruction to the 0x00 location of the Control Register Slave
device. However, any STORE cycle causes transfer of SRAM
data into a nonvolatile cell regardless of whether or not the
block is protected. The default value shipped from the factory
for BP0 and BP1 is ‘0’.
Command
■
Table 3. Memory Control Register Bits
Bit 7
0
Data Byte
[7:0]
0011 1100
Note If AutoStore is disabled and VCAP is not required, it is
required that the VCAP pin is left open. VCAP pin must never be
connected to ground. Power-Up RECALL operation cannot be
disabled in any case.
■
SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.
When the SLEEP instruction is registered, the nvSRAM
performs a STORE operation to secure the data to nonvolatile
memory and then enters into sleep mode. Whenever nvSRAM
enters into sleep mode, it initiates non volatile STORE cycle
which results in losing an endurance cycle per sleep command
execution. A STORE cycle starts only if a write to the SRAM
has been performed since the last STORE or RECALL cycle.
The nvSRAM enters into sleep mode as follows:
1. The Master sends a START command
2. The Master sends Control Registers Slave device ID with I2C
Write bit set (R/W = ’0’)
3. The Slave (nvSRAM) sends an ACK back to the Master
4. The Master sends Command Register address (0xAA)
5. The Slave (nvSRAM) sends an ACK back to the Master
6. The Master sends Command Register byte for entering into
Sleep mode
Page 8 of 31
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CY14C101J
CY14B101J, CY14E101J
7. The Slave (nvSRAM) sends an ACK back to the Master
8. The Master generates a STOP condition.
Once in Sleep mode the device starts consuming IZZ current
tSLEEP time after SLEEP instruction is registered. The device is
not accessible for normal operations until it is out of sleep mode.
The nvSRAM wakes up after tWAKE duration after the device
slave address is transmitted by the master.
Transmitting any of the two slave addresses wakes the nvSRAM
from Sleep mode. The nvSRAM device is not accessible during
tSLEEP and tWAKE interval, and any attempt to access the
nvSRAM device by the master is ignored and nvSRAM sends
NACK to the master. As an alternative method of determining
when the device is ready, the master can send read or write
commands and look for an ACK.
Figure 10. AutoStore Mode
VCC
0.1 uF
VCC
VCAP
VSS
VCAP
Write Protection (WP)
Hardware STORE and HSB pin Operation
The WP pin is an active high pin and protects entire memory and
all registers from write operations. To inhibit all the write
operations, this pin must be held high. When this pin is high, all
memory and register writes are prohibited and address counter
is not incremented. This pin is internally pulled LOW and hence
can be left open if not used.
The HSB pin in CY14X101J is used to control and acknowledge
STORE operations. If no STORE or RECALL is in progress, this
pin can be used to request a Hardware STORE cycle. When the
HSB pin is driven LOW, the device conditionally initiates a
STORE operation after tDELAY duration. An actual STORE cycle
starts only if a write to the SRAM has been performed since the
last STORE or RECALL cycle. Reads and Writes to the memory
are inhibited for tSTORE duration or as long as HSB pin is LOW.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
STORE or RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in Command Register on page 8. If AutoStore is
enabled without a capacitor on VCAP pin, the device attempts an
AutoStore operation without sufficient charge to complete the
Store. This will corrupt the data stored in nvSRAM as well as the
serial number and it will unlock the SNL bit.
Figure 10 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical
Characteristics on page 19 for the size of the VCAP.
Document #: 001-54050 Rev. *F
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB pin unconnected if not used.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the Ready status of the device.
Page 9 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Write Operation
Read Operation
The last bit of the slave device address indicates a read or a write
operation. In case of a write operation, the slave device address
is followed by the memory or register address and data. A write
operation continues as long as a STOP or Repeated START
condition is generated by the master or if a NACK is issued by
the nvSRAM.
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
A NACK is issued from the nvSRAM under the following
conditions:
1. A valid Device ID is not received.
2. A write (burst write) access to a protected memory block
address returns a NACK from nvSRAM after the data byte is
received. However, the address counter is set to this address
and the following current read operation starts from this
address.
3. A write/random read access to an invalid or out-of-bound
memory address returns a NACK from the nvSRAM after the
address is received. The address counter remains unchanged
in such a case.
4. A write to the Command Register with an invalid command.
This operation would return a NACK from the nvSRAM.
After a NACK is sent out from the nvSRAM, the write operation
is terminated and any data on the SDA line is ignored till a STOP
or a Repeated START condition is generated by the master.
For example, consider a case where the burst write access is
performed on Control Register Slave address 0x01 for writing the
serial number and continued to the address 0x09, which is a read
only register. The device returns a NACK and address counter
will not be incremented. A following read operation will be started
from the address 0x09. Further, any write operation which starts
from a write protected address (say, 0x09) will be responded by
the nvSRAM with a NACK after the data byte is sent and set the
address counter to this address. A following read operation will
start from the address 0x09 in this case also.
Note In case the user tries to read/write access an address that
does not exist (for example 0x0D in Control Register Slave),
nvSRAM responds with a NACK immediately after the
out-of-bound address is transmitted. The address counter
remains unchanged and holds the previous successful read or
write operation address.
A write operation is performed internally with no delay after the
eighth bit of data is transmitted. If a write operation is not
intended, the master must terminate the write operation before
the eighth clock cycle by generating a STOP or Repeated
START condition.
More details on write instruction are provided in Section Memory
Slave Access on page 10.
Document #: 001-54050 Rev. *F
In case of the Control Register Slave, whenever a burst read is
performed such that it flows to a non-existent address, the reads
operation will loop back to 0x00. This is applicable, in particular
for the Command Register.
There are the following ways to end a read operation:
1. The Master issues a NACK on the 9th clock cycle followed by
a STOP or a Repeated START condition on the 10th clock
cycle.
2. Master generates a STOP or Repeated START condition on
the 9th clock cycle.
More details on write instruction are provided in Section Memory
Slave Access on page 10.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform Read or Write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x00000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after all the 8 data bits have
been received by the nvSRAM. The nvSRAM sends an ACK
signal after a successful write operation. A write operation may
be terminated by the master by generating a STOP condition or
a Repeated START operation. If the master desires to abort the
current write operation without altering the memory contents, this
should be done using a START/STOP condition prior to the 8th
data bit.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and the address counter will
not be incremented.
Page 10 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
S
T
A
R
T
By Master
SDA Line
S
Memory Slave Address
1
1
0
Address MSB
Address LSB
S
T
0
P
Data Byte
P
0 A2 A1 A16 0
By nvSRAM
A
A
A
A
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
SDA Line
S
1
0
1
Address MSB
Address LSB
Data Byte 1
S
T
0
P
Data Byte N
~
~
By Master
S
T
A
R Memory Slave Address
T
0 A2 A1 A16 0
P
By nvSRAM
A
A
A
A
A
Figure 13. Single-Byte Write into nvSRAM (Hs-mode)
By Master
SDA Line
S
T
A
R
T
Hs-mode command
S 0 0 0
0 1
Memory Slave Address
X X X
Sr 1 0
Address MSB
S
T
0
P
Data Byte
Address LSB
P
1 0 A2 A1 A16 0
By nvSRAM
A
A
A
A
A
Figure 14. Multi-Byte Write into nvSRAM (Hs-mode)
SDA Line
Hs-mode command
S 0 0 0
0 1
Memory Slave Address
X X X
Sr 1 0
Address MSB
Data Byte 1
Address LSB
~
~
By Master
S
T
A
R
T
1 0 A2 A1 A16 0
By nvSRAM
A
By Master
A
By nvSRAM
Document #: 001-54050 Rev. *F
~
~
SDA Line
A
A
A
S
T
0
P
Data Byte N
Data Byte 3
Data Byte 2
A
A
P
A
Page 11 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Current nvSRAM Read
terminate a read operation after reading 1 byte or continue
reading addresses sequentially till the last address in the
memory after which the address counter rolls back to the
address 0x00000. The valid methods of terminating read access
are described in Section Read Operation on page 10.
Each read operation starts with the master transmitting the
nvSRAM slave address with the LSB set to ‘1’ to indicate “Read”.
The reads start from the address on the address counter. The
address counter is set to the address location next to the last
accessed with a “Write” or “Read” operation. The master may
Note A16-bit is ignored while using the current nvSRAM read.
Figure 15. Current Location Single-Byte nvSRAM Read (except Hs-mode)
By Master
SDA Line
S
T
A
R
T
S
A
Memory Slave Address
1
1
0
0
A2 A1 X
S
T
0
P
P
1
By nvSRAM
Data Byte
A
Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs-mode)
SDA Line
S
A
A
Memory Slave Address
1
0
1
0 A2 A1 X
1
By nvSRAM
S
T
0
P
P
~
~
By Master
S
T
A
R
T
Data Byte N
Data Byte
A
Figure 17. Current Location Single-Byte nvSRAM Read (Hs-mode)
By Master
SDA Line
S
T
A
R
T
Hs-mode command
S 0 0 0
0 1
S
A T
0
P
Memory Slave Address
X X X
Sr 1 0
P
1 0 A2 A1 X 1
By nvSRAM
A
A
Data Byte
Figure 18. Current Location Multi-Byte nvSRAM Read (Hs-mode)
SDA Line
A
Hs-mode command
S 0 0 0
0 1
X X X
Sr 1 0
1 0 A2 A1 X 1
Data Byte
By nvSRAM
A
Document #: 001-54050 Rev. *F
A
Memory Slave Address
~
~
By Master
S
T
A
R
T
S
T
0
P
P
Data Byte N
A
Page 12 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Random Address Read
A random address read is performed by first initiating a write
operation and generating a Repeated START immediately after
the last address byte is acknowledged. The address counter is
set to this address and the next read access to this slave will
initiate read operation from here. The master may terminate a
read operation after reading 1 byte or continue reading
addresses sequentially till the last address in the memory after
which the address counter rolls back to the start address
0x00000.
Figure 19. Random Address Single-Byte Read (except Hs-mode)
By Master
SDA Line
S
T
A
R
T
S
S
T
0
P
A
Memory Slave Address
1
1
0
Address MSB
Address LSB
Memory slave Address
0 A2 A1 A16 0
Sr 1
0
1
0 A2 A1
X
P
1
By nvSRAM
Data Byte
A
A
A
A
Figure 20. Random Address Multi-Byte Read (except Hs-mode)
SDA Line
S
A
Memory Slave Address
1
0
1
Address MSB
Address LSB
Memory slave Address
0 A2 A1 A16 0
Sr 1
0
1
0 A2 A1
X
1
By nvSRAM
Data Byte 1
A
A
S
T
0
P
A
~
~
By Master
S
T
A
R
T
A
A
P
Data Byte N
Figure 21. Random Address Single-Byte Read (Hs-mode)
SDA Line
Hs-mode command
S 0 0 0
0 1
Address MSB
Memory Slave Address
X X X
Sr 1 0
Address LSB
Memory Slave Address
1 0 A2 A1 A16 0
Sr 1 0
1 0 A2 A1 X 1
~
~
By Master
S
T
A
R
T
By nvSRAM
A
A
A
A
A
S
T
A 0
P
P
Data Byte
Document #: 001-54050 Rev. *F
Page 13 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Figure 22. Random Address Multi-Byte Read (Hs-mode)
SDA Line
Hs-mode command
S 0 0 0
0 1
Address MSB
Memory Slave Address
X X X
Sr 1 0
Address LSB
Memory Slave Address
Sr 1 0
1 0 A2 A1 A16 0
1 0 A2 A1 X 1
~
~
By Master
S
T
A
R
T
By nvSRAM
A
A
A
A
A
A
P
~
~
Data Byte
A
S
T
0
P
Data Byte N
Control Registers Slave
The following sections describes the data transfer sequence
required to perform Read or Write operations from Control
Registers Slave.
Write Control Registers
To write the Control Registers Slave, the master transmits the
Control Registers Slave address after generating the START
condition. The write sequence continues from the address
location specified by the master till the master generates a STOP
condition or the last writable address location.
If a non writable address location is accessed for write operation
during a normal write or a burst, the slave generates a NACK
after the data byte is sent and the write sequence terminates.
Any following data bytes are ignored and the address counter is
not incremented.
If a write operation is performed on the Command Register
(0xAA), the following current read operation also begins from the
first address (0x00) as in this case, the current address is an
out-of-bound address. The address is not incremented and the
next current read operation begins from this address location. If
a write operation is attempted on an out-of-bound address
location, the nvSRAM sends a NACK immediately after the
address byte is sent.
Further, if the serial number is locked, only two addresses (0xAA
or Command Register, and 0x00 or Memory Control Register)
are writable in the Control Registers Slave. On a write operation
to any other address location, the device will acknowledge
command byte and address bytes but it returns a NACK from the
Control Registers Slave for data bytes. In this case, the address
will not be incremented and a current read will happen from the
last acknowledged address.
The nvSRAM Control Registers Slave sends a NACK when an
out of bound memory address is accessed for write operation, by
the master. In such a case, a following current read operation
begins from the last acknowledged address.
Figure 23. Single-Byte Write into Control Registers
S
T
A
R
T
By Master
SDA Line
S
Control Registers
Slave Address
0
0
1
1 A2 A1 X
Control Register Address
S
T
0
P
Data Byte
P
0
By nvSRAM
A
A
A
Figure 24. Multi-Byte Write into Control Registers
SDA Line
S
Control Registers
Slave Address
0
0
1
1 A2 A1 X
Control Register Address
Data Byte
0
By nvSRAM
A
Document #: 001-54050 Rev. *F
S
T
0
P
Data Byte N
P
~
~
By Master
S
T
A
R
T
A
A
A
Page 14 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Current Control Registers Read
A read of Control Registers Slave is started with master sending
the Control Registers Slave address after the START condition
with the LSB set to ‘1’. The reads begin from the current address
which is the next address to the last accessed location. The
reads to Control Registers Slave continues till the last readable
address location and loops back to the first location (0x00). Note
that the Command Register is a write only register and is not
accessible through the sequential read operations. If a burst read
operation begins from the Command Register (0xAA), the
address counter wraps around to the first address in the register
map (0x00).
Figure 25. Control Registers Single-Byte Read
S
T
A
R
T
By Master
SDA Line
S
Control Registers
Slave Address
0
0
1
1 A2 A1
S
T
0
P
A
X
P
1
By nvSRAM
Data Byte
A
Figure 26. Current Control Registers Multi-Byte Read
S
T
A
R
T
SDA Line
S
0
0
1
1 A2 A1 X
A
A
1
By nvSRAM
Data Byte
S
T
0
P
P
~
~
By Master
Control Registers
Slave Address
Data Byte N
A
Random Control Registers Read
A read of random address may be performed by initiating a write
operation to the intended location of read and immediately
following with a Repeated START operation. The reads to
Control Registers Slave continues till the last readable address
location and loops back to the first location (0x00). Note that the
Command Register is a write only register and is not accessible
through the sequential read operations. A random read starting
at the Command Register (0xAA) loops back to the first address
in the Control Registers register map (0x00). If a random read
operation is initiated from an out-of-bound memory address, the
nvSRAM sends a NACK after the address byte is sent.
.
Figure 27. Random Control Registers Single-Byte Read
By Master
SDA Line
S
T
A
R
T
S
Control Registers
Slave Address
0
0
1
1 A2 A1 X
Control Register Address
A
Control Registers Slave Address
Sr 0
0
0
1
1
A2 A1 X
S
T
0
P
P
1
By nvSRAM
Data Byte
A
Document #: 001-54050 Rev. *F
A
A
Page 15 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Figure 28. Random Control Registers Multi-Byte Read
SDA Line
S
Control Registers
Slave Address
0
0
1
1 A2 A1
Control Register Address
X
A
Control Registers Slave Address
Sr 0
0
0
1
1
A2 A1 X
1
~
~
By Master
S
T
A
R
T
By nvSRAM
Data Byte
A
A
A
A
S
T
0
P
P
Data Byte N
Serial Number
Serial number is an 8 byte memory space provided to the user
to uniquely identify this device. It typically consists of a two byte
customer ID, followed by five bytes of unique serial number and
one byte of CRC check. However, nvSRAM does not calculate
the CRC and it is up to the user to utilize the eight byte memory
space in the desired format. The default values for the eight byte
locations are set to ‘0x00’.
Serial Number Write
The serial number can be accessed through the Control
Registers Slave Device. To write the serial number, master
transmits the Control Registers Slave address after the START
condition and writes to the address location from 0x01 to 0x08.
The content of Serial Number registers is secured to nonvolatile
memory on the next STORE operation. If AutoStore is enabled,
nvSRAM automatically stores the serial number in the
nonvolatile memory on power-down. However, if AutoStore is
disabled, user must perform a STORE operation to secure the
contents of Serial Number registers.
Note If the serial number lock (SNL) bit is not set, the serial
number registers can be re-written regardless of whether or not
a STORE has happened. Once the serial number lock bit is set,
no writes to the serial number registers are allowed. If the master
tries to perform a write operation to the serial number registers
Document #: 001-54050 Rev. *F
when the lock bit is set, a NACK is returned and write will not be
performed.
Serial Number Lock
After writes to Serial Number registers is complete, master is
responsible for locking the serial number by setting the serial
number lock bit to ‘1’ in the Memory Control Register (0x00). The
content of Memory Control Register and serial number are
secured on the next STORE operation (STORE or AutoStore). If
AutoStore is not enabled, user must perform STORE operation
to secure the lock bit status.
If a STORE was not performed, the serial number lock bit will not
survive the power cycle. The serial number lock bit and 8 - byte
serial number is defaults to ‘0’ at power-up.
Serial Number Read
Serial number can be read back by a read operation of the
intended address of the Control Registers Slave. The Control
Registers Device loops back from the last address (excluding the
Command Register) to 0x00 address location while performing
burst read operation. The serial number resides in the locations
from 0x01 to 0x08. Even if the serial number is not locked, a
serial number read operation will return the current values written
to the serial number registers. Master may perform a serial
number read operation to confirm if the correct serial number is
written to the registers before setting the lock bit.
Page 16 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Device ID Read
registers are set in the factory and are read only registers for the
user.
Device ID is a 4 byte code consisting of JEDEC assigned
manufacturer ID, product ID, density ID, and die revision. These
Table 6. Device ID
Bits
#of Bits
Device
CY14C101J1
CY14C101J2
CY14C101J3
CY14B101J1
CY14B101J2
CY14B101J3
CY14E101J1
CY14E101J2
CY14E101J3
31 - 21
(11 bits)
Manufacture ID
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
20 - 7
(14 bits)
Product ID
00001001000001
00001101000001
00001101000101
00001001010001
00001101010001
00001101010101
00001001100001
00001101100001
00001101100101
6- 3
(4 bits)
Density ID
0100
0100
0100
0100
0100
0100
0100
0100
0100
2-0
(3 bits)
Die Rev
000
000
000
000
000
000
000
000
000
The device ID is divided into four parts as shown in Table 6:
4. Die Rev (3 bits)
1. Manufacturer ID (11 bits)
This is used to represent any major change in the design of the
product. The initial setting of this is always 0x0.
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
Executing Commands Using Command
Register
Cypress manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is given as:
The Control Registers Slave allows different commands to be
executed by writing the specific command byte in the command
register (0xAA). The command byte codes for each command
are specified in Table 5. During the execution of these
commands the device is not accessible and returns NACK if any
of the two slave devices is selected. If an invalid command is sent
by the master, nvSRAM responds with a NACK indicating that
command was not successful. The address latch of this slave
continues to point to the command register address.
Cypress ID - 000_0011_0100
2. Product ID (14 bits)
The product ID for device is shown in the Table 6.
3. Density ID (4 bits)
The 4 bit density ID is used as shown in Table 6 for indicating the
1 Mb density of the product.
Figure 29. Command Execution using Command Register
By Master
SDA Line
S
T
A
R
T
S
Control Register
Slave Address
0
0
1
1 A2 A1 X
Command Register Address
1
0
0
1
0
1
0
1
S
T
O
P
Command Byte
P
0
By nvSRAM
A
Document #: 001-54050 Rev. *F
A
A
Page 17 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Best Practices
■
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection.
nvSRAM products have been used effectively for over 26 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Document #: 001-54050 Rev. *F
Page 18 of 31
[+] Feedback
CY14C101J
CY14B101J, CY14E101J
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Maximum accumulated storage time
Transient voltage (<20 ns) on
any pin to ground potential .................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) .................................................. 1.0 W
Surface mount lead soldering
temperature (3 seconds) .......................................... +260 °C
At 150 °C ambient temperature ....................... 1000 h
DC output current (1 output at a time, 1s duration). .... 15 mA
At 85 °C ambient temperature ..................... 20 Years
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Ambient temperature with
power applied ........................................... –55 °C to +150 °C
Latch up current..................................................... > 140 mA
Supply voltage on VCC relative to VSS
CY14C101J: VCC = 2.4 V to 2.6 V .....–0.5 V to +3.1 V
CY14B101J: VCC = 2.7 V to 3.6 V .....–0.5 V to +4.1 V
CY14E101J: VCC = 4.5 V to 5.5 V .....–0.5 V to +7.0 V
DC voltage applied to outputs
in High Z state ..................................... –0.5 V to VCC + 0.5 V
Operating Range
Input voltage ........................................ –0.5 V to VCC + 0.5 V
Product
Range
Ambient
Temperature
VCC
CY14C101J Industrial –40 °C to +85 °C
2.4 V to 2.6 V
CY14B101J
2.7 V to 3.6 V
CY14E101J
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VCC
Test Conditions
Power supply
Min
Typ[3]
Max
Unit
CY14C101J
2.4
2.5
2.6
V
CY14B101J
2.7
3.0
3.6
V
CY14E101J
4.5
5.0
5.5
V
ICC1
Average VCC current
fSCL = 3.4 MHz;
Values obtained without output loads (IOUT = 0 mA)
–
–
1
mA
ICC2
Average VCC current
during STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
2
mA
ICC3
Average VCC current fSCL = All inputs cycling at CMOS levels.
Values obtained without output loads (IOUT = 0 mA)
100 kHz;
VCC = VCC (Typ), 25 °C
–
–
1
mA
ICC4
Average VCAP current
during AutoStore cycle
All inputs don't care. Average current for duration
tSTORE
–
–
3
mA
ISB
VCC standby current
SCL > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile cycle is
complete. Inputs are static. fSCL = 0 MHz.
–
–
150
A
IZZ
Sleep mode current
tSLEEP time after SLEEP Instruction is Issued. All
inputs are static and configured at CMOS logic level.
–
–
8
A
IIX[4]
Input current in each I/O pin 0.1 VCC < Vi < 0.9 VCCmax
(except HSB)
–1
–
+1
A
–100
–
+1
A
–1
–
+1
A
–
–
7
pF
Input current in each I/O pin
(for HSB)
IOZ
Output leakage current
Ci
Capacitance for each I/O
pin
Capacitance measured across all input and output
signal pin and VSS.
Note
3. Typical values are at 25 °C, VCC = VCC (Typ). Not 100% tested.
4. Not applicable to WP, A2 and A1 pins.
Document #: 001-54050 Rev. *F
Page 19 of 31
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CY14C101J
CY14B101J, CY14E101J
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ[3]
Max
Unit
VIH
Input HIGH voltage
0.7 Vcc
–
VCC +
0.5
V
VIL
Input LOW voltage
– 0.5
–
0.3 Vcc
V
VOL
Output LOW voltage
IOL= 3 mA
0
–
0.4
V
Rin[5]
Input resistance (WP, A2,
A1)
For VIN = VIL (Max)
50
–
–
K
Vhys
Hysteresis of Schmitt
trigger inputs
VCAP
Storage capacitor
For VIN = VIH (Max)
Between VCAP pin and VSS
1
–
–
M
0.05 VCC
–
–
V
CY14C101J
170
220
270
F
CY14B101J
CY14E101J
42
47
180
F
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
Thermal Resistance
Parameter[6]
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
8-pin SOIC 16-pin SOIC
Unit
101.08
56.68
C/W
37.86
32.11
C/W
Notes
5. The input pull-down circuit is stronger (50 K) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
6. These parameters are guaranteed by design and are not tested.
Document #: 001-54050 Rev. *F
Page 20 of 31
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CY14C101J
CY14B101J, CY14E101J
Figure 30. AC Test Loads and Waveforms
For 3.0 V (CY14B101J)
For 2.5 V (CY14C101J)
For 5.0 V (CY14E101J)
3.0 V
2.5 V
867 
700 
OUTPUT
OUTPUT
5.0 V
1.6 K
OUTPUT
100 pF
100 pF
50 pF
AC Test Conditions
Input pulse levels
Input rise and fall times (10% - 90%)
Input and output timing reference levels
Document #: 001-54050 Rev. *F
CY14C101J
0 V to 2.5 V
10 ns
1.25 V
CY14B101J
0 V to 3 V
10 ns
1.5 V
CY14E101J
0 V to 5 V
10 ns
2.5 V
Page 21 of 31
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CY14C101J
CY14B101J, CY14E101J
AC Switching Characteristics
Parameter
3.4 MHz[7]
Description
1 MHz[7]
400 kHz[7]
Unit
Min
Max
Min
Max
Min
Max
–
3400
–
1000
–
400
kHz
fSCL
Clock frequency, SCL
tSU; STA
Setup time for Repeated START condition
160
–
250
–
600
–
ns
tHD;STA
Hold time for START condition
160
–
250
–
600
–
ns
tLOW
LOW period of the SCL
160
–
500
–
1300
–
ns
tHIGH
HIGH period of the SCL
60
–
260
–
600
–
ns
tSU;DATA
Data in setup time
10
–
100
–
100
–
ns
tHD;DATA
Data hold time (In/Out)
0
–
0
–
0
–
ns
tDH
Data out hold time
0
–
0
–
0
–
ns
Rise time of SDA and SCL
–
80
–
120
–
300
ns
tr
[8]
tf[8]
Fall time of SDA and SCL
tSU;STO
Setup time for STOP condition
tVD;DATA
tVD;ACK
[8]
–
80
–
120
–
300
ns
160
–
250
–
600
–
ns
Data output valid time
–
130
–
400
–
900
ns
ACK output valid time
–
130
–
400
–
900
ns
–
80
–
120
–
300
ns
tBUF
Bus free time between STOP and next START condition
0.3
–
0.5
–
1.3
–
us
tSP
Pulse width of spikes that must be suppressed by input
filter
–
5
–
50
–
50
tOF
Output fall time from VIH min to VILmax
ns
~
~
~
~
Figure 31. Timing Diagram
tr
t LOW
~
~
~
~
SDA
t HD;STA
t SU;DATA
tf
t SP
t BUF
S
t HD;DATA
t HIGH
~
~
t HD;STA
~
~
SCL
t SU;STA
tr
tf
t SU;STO
Sr
P
S
Note
7. Bus Load (Cb) Considerations; Cb < 500 pF for I2C clock frequency (SCL) 100/400/1000 KHz; Cb < 100 pF for SCL at 3.4 MHz.
8. These parameters are guaranteed by design and are not tested.
Document #: 001-54050 Rev. *F
Page 22 of 31
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CY14C101J
CY14B101J, CY14E101J
nvSRAM Specifications
Parameter
tFA [9]
Description
CY14C101J
CY14B101J
CY14E101J
Power-Up RECALL duration
tSTORE [10]
STORE cycle duration
tDELAY[11]
tVCCRISE[12]
Time allowed to complete SRAM write cycle
VCC rise time
VSWITCH
Low voltage trigger level
[12]
CY14C101J
CY14B101J
CY14E101J
Min
Max
Unit
–
40
ms
–
20
ms
–
20
ms
–
8
ms
–
150
25
–
ns
µs
–
2.35
V
–
2.65
V
–
4.40
V
µs
HSB high to nvSRAM active time
–
5
VHDIS[12]
tHHHD[12]
HSB output disable voltage
–
1.9
V
HSB HIGH active time
–
500
ns
tWAKE
Time for nvSRAM to wake up from SLEEP mode
–
40
ms
–
20
ms
–
20
ms
–
8
ms
–
100
µs
tLZHSB
CY14C101J
CY14B101J
CY14E101J
tSLEEP
Time to enter low power mode after issuing SLEEP instruction
tSB
Time to enter into standby mode after issuing STOP condition
Figure 32. AutoStore or Power-Up
RECALL[13]
VCC
VSWITCH
VHDIS
t VCCRISE
tHHHD
Note 10
tSTORE
Note
tHHHD
14
Note
10
tSTORE
14
Note
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
9. tFA starts from the time VCC rises above VSWITCH.
10. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
11. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
12. These parameters are guaranteed by design and are not tested.
13. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
14. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-54050 Rev. *F
Page 23 of 31
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CY14C101J
CY14B101J, CY14E101J
Software Controlled STORE/RECALL Cycles
Parameter
CY14X101J
Description
Min
Max
Unit
tRECALL
RECALL duration
–
600
µs
tSS[15, 16]
Software sequence processing time
–
500
µs
Figure 33. Software STORE/RECALL Cycle[16]
DATA OUTPUT
BY MASTER
Command Reg Address
nvSRAM Control Slave Address
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM
MASTER
1
2
8
9
1
Command Byte (STORE/RECALL)
2
8
9
1
acknowledge (A) by Slave
2
8
9
S
P
START
condition
STOP
condition
RWI
t STORE / t
RECALL
Figure 34. AutoStore Enable/Disable Cycle
DATA OUTPUT
BY MASTER
Command Reg Address
nvSRAM Control Slave Address
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM
MASTER
1
2
S
START
condition
8
9
1
Command Byte (ASENB/ASDISB)
2
8
9
1
acknowledge (A) by Slave
2
8
9
P
STOP
condition
RWI
t SS
Notes
15. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.
16. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-54050 Rev. *F
Page 24 of 31
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CY14C101J
CY14B101J, CY14E101J
Hardware STORE Cycle
Parameter
tPHSB
CY14X101J
Description
Min
Max
15
–
Hardware STORE pulse width
Unit
ns
Figure 35. Hardware STORE Cycle[17]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
tDELAY
HSB (OUT)
tLZHSB
RWI
tPHSB
HSB (IN)
HSB pin is driven HIGH to VCC only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
tDELAY
RWI
~
~
HSB (OUT)
~
~
Write Latch not set
Note
17. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
Document #: 001-54050 Rev. *F
Page 25 of 31
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CY14C101J
CY14B101J, CY14E101J
Ordering Information
Ordering Code
Package Diagram
CY14B101J2-SXIT
51-85066
Package Type
Operating Range
8-pin SOIC (with VCAP)
Industrial
CY14B101J2-SXI
All these parts are Pb-free. This table contains Final information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 B 101 J 2 - S X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
1 - Without VCAP
2 - With VCAP
3 - With VCAP and HSB
Package:
S - 8-pin SOIC
SF - 16-pin SOIC
J - Serial (I2C) nvSRAM
Density:
Voltage:
C - 2.5 V
B - 3.0 V
E - 5.0 V
101 - 1 Mb
14 - nvSRAM
Cypress
Document #: 001-54050 Rev. *F
Page 26 of 31
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CY14C101J
CY14B101J, CY14E101J
Package Diagrams
Figure 36. 8-pin (150 mil) SOIC Package, 51-85066
51-85066 *D
Document #: 001-54050 Rev. *F
Page 27 of 31
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CY14C101J
CY14B101J, CY14E101J
Package Diagrams (continued)
Figure 37. 16-pin (300 mil) SOIC, 51-85022
51-85022 *C
Document #: 001-54050 Rev. *F
Page 28 of 31
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CY14C101J
CY14B101J, CY14E101J
Acronyms
Document Conventions
Acronym
Description
Units of Measure
ACK
Acknowledge
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
CRC
Cyclic Redundancy Check
Hz
Hertz
EIA
Electronic Industries Alliance
I2C
kbit
1024 bits
Inter-Integrated Circuit Bus
kHz
kilo Hertz
I/O
Input/Output
K
kilo ohms
JEDEC
Joint Electron Devices Engineering Council
A
micro Amperes
nvSRAM
nonvolatile Static Random Access Memory
mA
milli Amperes
NACK
No acknowledge
F
micro Farad
RWI
Read and Write Inhibited
MHz
Mega Hertz
RoHS
Restriction of Hazardous Substances
s
micro seconds
SNL
Serial Number Lock
ms
milli seconds
SCL
Serial Clock Line
ns
nano seconds
SDA
Serial Data Line
pF
pico Farad
SOIC
Small Outline Integrated Circuit
V
Volts
WP
Write protect

ohms
W
Watts
Document #: 001-54050 Rev. *F
Symbol
Unit of Measure
Page 29 of 31
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CY14C101J
CY14B101J, CY14E101J
Document History Page
Document Title: CY14C101J, CY14B101J, CY14E101J 1-Mbit (128 K × 8) Serial (I2C) nvSRAM
Document Number: 001-54050
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
2754627
08/21/09
GVCH
New Data Sheet
*A
2860397
01/20/2010
GVCH
Changed Vcc range for CY14C101I from 2.3 - 2.7V to 2.4-2.6V
Removed 16-SOIC 150 mil package option
Added 16-SOIC 300 mil package option
Added 3.4MHz bus frequency related information
Changed IOL min value from 20 mA to 3mA
Changed tLOW min value from 400ns to 500ns for 1MHz
Changed tLOW min value from 600ns to 1300ns for 400 KHz
Changed tHIGH min value from 400ns to 260ns
Changed tDH min value from 50ns to 0ns
Updated tr max value.
Removed tSP min value
*B
2963131
06/28/2010
GVCH
Changed datasheet status from “Advance” to “Preliminary”
Changed data sheet title from CY14C101J, CY14B101J, CY14E101J 1 Mbit
(128K x 8) Serial (I2C) nvSRAM with Real Time Clock (RTC) to
CY14C101J, CY14B101J, CY14E101J 1 Mbit (128K x 8) Serial (I2C)
nvSRAM
Updated logic block diagram
Updated Pinouts
Updated Pin Definitions
Complete content write
Changed ICC4 value from 2 mA to 3 mA
Added IOZ and Ci parameter in DC Electrical Characteristics
Removed IOL parameter in DC Electrical Characteristics
Changed VCAP value from for VCC=2.4V-2.6V
1. Changed min value from 100 uF to 170 uF
2. Changed typ value from 150 uF to 220 uF
3. Changed max value from 330 uF to 270 uF
Changed VCAP value from for VCC=2.7V-3.6V and VCC=4.5-5.5 V
1. Changed min value from 40 uF to 42 uF
Added Data Retention and Endurance Table
Added Thermal Resistance Table
Added AC Test Conditions Table
Added Figures
Added Software Controlled STORE/RECALL Cycles Table
Added Hardware STORE Cycle Table
Added tFA for VCC=2.4V-2.6V
Added tWAKE for VCC=2.4V-2.6V
Added tSB parameter
Changed VSWITCH from 4.45 V to 4.40V for VCC = 4.5 V to 5.5 V
Updated tRECALL value from 200 us to 300 us
Changed tSS value from 100 to 200 µs
Added tPHSB parameter
Updated Ordering Information
*C
3084950
11/12/2010
GVCH
Updated tSP max value from 10 ns to 5 ns for 3.4 MHz
Updated tSS value from 200 us to 500 us
Updated tRECALL value from 300 us to 600 us
Added Units of Measure table
*D
3147585
01/19/2011
GVCH
Hardware STORE and HSB pin Operation: Added more clarity on HSB pin
operation
Updated tLZHSB parameter description
Fixed typo in Figure 32.
Document #: 001-54050 Rev. *F
Description of Change
Page 30 of 31
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CY14C101J
CY14B101J, CY14E101J
Document History Page (continued)
Document Title: CY14C101J, CY14B101J, CY14E101J 1-Mbit (128 K × 8) Serial (I2C) nvSRAM
Document Number: 001-54050
Rev.
ECN No.
Submission
Date
Orig. of
Change
*E
3191637
03/21/2011
GVCH
Updated AutoStore Operation (description).
Updated Table 6 (Product ID column).
Updated DC Electrical Characteristics (Added note 4).
Updated in new template.
*F
3248609
05/04/2011
GVCH
Datasheet status changed from “Preliminary” to “Final”
Updated Ordering Information
Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-54050 Rev. *F
Revised May 4, 2011
Page 31 of 31
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