CY25560 Spread Spectrum Clock Generator Features Applications ■ 25 MHz to 100 MHz operating frequency range ■ Desktop, notebook, and tablet PCs ■ Nine different spread select options ■ VGA controllers ■ Accepts clock and crystal inputs ■ LCD panels and monitors ■ Low power dissipation: ❐ 56 mW at Fin = 25 MHz ❐ 89 mW at Fin = 65 MHz ❐ 139 mW at Fin = 100 MHz ■ Printers and multifunction devices (MFP) Benefits ■ Peak electromagnetic interference (EMI) reduction by 8 to 16 dB Center spread modulation ■ Fast time to market ■ Low cycle-to-cycle jitter ■ Cost reduction ■ 8-pin SOIC package ■ Commercial and industrial temperature ranges ■ Frequency spread disable function ■ Logic Block 250 K Xin/ CLK 1 Xout 8 VDD VSS REFERENCE DIVIDER MODULATION CONTROL 2 VDD vco DIVIDER & MUX 4 SSCLK VDD 20 K 20 K 20 K 20 K VSS • Loop Filter CP FEEDBACK DIVIDER INPUT DECODER LOGIC 3 Cypress Semiconductor Corporation Document #: 38-07425 Rev. *G PD VSS 5 6 7 SSCC S1 S0 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 12, 2011 CY25560 Contents Pinouts .............................................................................. 3 General Description ......................................................... 3 Tri-Level Logic .................................................................. 4 SSCG Theory of Operation .............................................. 4 EMI .............................................................................. 4 SSCG .......................................................................... 5 Modulation Rate .......................................................... 5 CY25560 Application Schematic ..................................... 6 Absolute Maximum Ratings ............................................ 7 Absolute Maximum Conditions ....................................... 8 Ordering Information ........................................................ 9 Document #: 38-07425 Rev. *G Ordering Code Definition ................................................. 9 Package Drawing and Dimensions ............................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 Page 2 of 13 CY25560 Pinouts Figure 1. Pin Configuration – 8-Pin SOIC Package XIN/CLK 1 8 XOUT VDD 2 7 S0 CY25560 VSS 3 SSCLK 4 6 S1 5 SSCC Table 1. Pin Description Pin Number Pin Name Type Pin Description 1 Xin/CLK I Clock or crystal connection input. See the Table 2 on page 4 for input frequency range selection. 2 VDD P Positive power supply. 3 GND P Power supply ground. 4 SSCLK O Modulated clock output, that is the same frequency as the input clock or the crystal frequency. 5 SSCC I Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input is high and disabled when input is low. This pin is pulled high internally. 6 S1 I Tri-level logic input control pin used to select input frequency range and spread percent. See the “Tri-Level Logic” on page 4 for programming details. Pin 6 has an internal resistor divider network to VDD and VSS. See the Logic Block Diagram on page 1. 7 S0 I Tri-level logic input control pin used to select input frequency range and spread percent. See the “Tri-Level Logic” on page 4 for programming details. Pin 7 has an internal resistor divider network to VDD and VSS. See the Logic Block Diagram on page 1. 8 Xout O Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock is used to drive xin/clk input (Pin 1). General Description The Cypress CY25560 is a spread spectrum clock generator (SSCG) IC used to reduce the EMI found in today’s high-speed digital electronic systems. CY25560 is optimized for SVGA (40 MHz) and XVGA (65 MHz) controller clocks and also suitable for applications where the frequency range is 25 MHz to 100 MHz. The CY25560 uses Cypress’s proprietary phase-locked loop (PLL) and spread spectrum clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is greatly reduced. A wide range of digitally selectable spread percentages is made possible by using three-level (High, Low, and Middle) logic at the S0 and S1 digital control inputs. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading system performance. The CY25560 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L), and Middle (M) logic levels to select one of the nine available spread% ranges. See the Table 2 on page 4 for programming details. Document #: 38-07425 Rev. *G The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. The CY25560 is available in an 8-pin SOIC package with 0 C to 70 C Commercial and –40 C to 85 C Industrial operating temperature ranges. Page 3 of 13 CY25560 Figure 2. Three-Level Logic Examples VDD CY25560 CY25560 S0 S0 = "M" (N/C) 7 S1 = "0" (GND) 6 SSCC = "1" 5 VDD CY25560 S0 S0 = "1" S0 7 S1 S0 = "1" 7 S1 = "1" 6 SSCC = "1" 5 S1 S1 = "0" (GND) 6 SSCC = "1" 5 VDD S1 VDD Table 2. Frequency and Spread% Selection 25 – 50 MHz (Low Range) Input Frequency (MHz) 25 – 35 35 – 40 40 – 45 45 – 50 S1=M S0=M (%) 4.3 3.9 3.7 3.4 S1=M S0=0 (%) 3.8 3.5 3.3 3.1 S1=1 S0=0 (%) 3.4 3.1 2.8 2.6 S1=0 S0=0 (%) 2.9 2.5 2.4 2.2 S1=0 S0=M (%) 2.8 2.4 2.3 2.1 Select the Frequency and Center Spread % desired and then set S1, S0 as indicated. 50 – 100 MHz (High Range) Input Frequency (MHz) 50 – 60 60 – 70 70 – 80 80 – 100 S1=1 S0=M (%) 2.9 2.8 2.6 2.4 S1=0 S0=1 (%) 2.1 2.0 1.8 1.7 S1=1 S0=1 (%) 1.5 1.4 1.3 1.2 Tri-Level Logic With binary logic, four states can be programmed with two control lines, whereas three-level logic can program nine logic states using two control lines. Three-level logic in the CY25560 is implemented by defining a third logic state in addition to the standard logic ‘1’ and ‘0’. Pins 6 and 7 of the CY25560 recognize a logic state by the voltage applied to their respective pin. These states are defined as ‘0’ (Low), ‘M’ (Middle), and ‘1’ (One). Each of these states have a defined voltage range that is interpreted by the CY25560 as a ‘0’, ‘M’, or ‘1’ logic state. See the Table 3 for voltage ranges for each logic state. The CY25560 has two equal value resistor dividers connected internally to Pins 6 and 7 that produce the default ‘M’ (Middle) state if these pins are left unconnected (NC). Pins 6 and/or 7 can be tied directly to ground or VDD to program a logic ‘0’ or ‘1’ state, respectively. SSCG Theory of Operation The CY25560 is a PLL-type clock generator using a proprietary Cypress design. By precisely controlling the bandwidth of the output clock, the CY25560 becomes a low-EMI clock generator. Document #: 38-07425 Rev. *G S1=M S0=1 (%) 1.2 1.1 1.1 1.0 Select the Frequency and Center Spread % desired and then set S1, S0 as indicated. The theory and detailed operation of the CY25560 is discussed in the following sections. EMI All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50 percent. Because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, seventh, and so on. It is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a very high Q factor, that means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for EMI. Conventional methods of reducing EMI have been to use shielding, filtering, multilayer PCBs, and so on. The CY25560 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the Q factor. Page 4 of 13 CY25560 SSCG SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle-to-cycle. The CY25560 takes a narrow band digital reference clock in the range of 25 to 100 MHz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. To understand what happens to a clock when SSCG is applied, consider a 65 MHz clock with a 50 percent duty cycle. From a 65 MHz clock we know the following: 50 % Clock frequency = fc = 65 MHz Clock period = Tc =1/65 MHz = 15.4 ns 50 % Tc = 15.4 ns If this clock is applied to the Xin/CLK pin of CY25560, the output clock at Pin 4 (SSCLK) sweeps back and forth between two frequencies. These two frequencies, F1 and F2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at Pin 1. As the clock is making the transition from F1 to F2, the amount of time and sweep waveform play a very important role in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. Figure 3 shows the modulation profile of a 65 MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. Figure 3 also shows a scan of the same SSCG clock using a spectrum analyzer. In this scan you can see a 6.48 dB reduction in the peak RF energy when using the SSCG clock. Modulation Rate SSCGs utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmod. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the Modulation Rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the device. The CY25560 has a fixed divider count of 1166. Figure 3. SSCG Clock, CY25560, Fin = 65 MHz Device CY25560 Divider Count (Cdiv) 1166 (All Ranges) Example: Device = Fin = Range = CY25560 65 MHz S1 = 1, S0 = 0 Then: Modulation Rate = Fmod = 65 MHz/1166 = 55.7 kHz. Modulation Profile Document #: 38-07425 Rev. *G Spectrum Analyzer Page 5 of 13 CY25560 CY25560 Application Schematic The schematic in Figure 4 demonstrates how the CY25560 is configured in a typical application. This application is shown as using a 30 MHz fundamental crystal. In most applications, an external reference clock is used. Apply the external clock signal at Xin (Pin 1) and leave Xout (Pin 8) unconnected (see Table 1 for pin descriptions). Contact Cypress if higher order crystal is to be used. Figure 4. Application Schematic VDD C3 0.1 uF 2 C2 1 27 pF C3 X IN /C LK VDD 4 Y1 30 M H z 8 S S C LK XOUT 27 pF C Y 25560 6 S1 VDD 5 SSCC S0 7 VSS 3 Document #: 38-07425 Rev. *G Page 6 of 13 CY25560 Absolute Maximum Ratings Commercial Grade[1, 2] Supply Voltage (VDD):...................................–0.5 V to +6.0 V DC Input Voltage: .................................. –0.5 V to VDD+0.5 V Junction Temperature ............................... –40 °C to +140 °C Operating Temperature:.................................... 0 °C to 70 °C Storage Temperature ................................ –65 °C to +150 °C Static Discharge Voltage (ESD) .......................... 2,000 V-Min Table 3. DC Electrical Characteristics VDD = 3.3 V ± 10%, T = 0 °C to 70 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted Parameter Description Conditions VDD Power supply range ±10% Min Typ Max Unit 2.97 3.3 3.63 V VIH Input high voltage S0 and S1 only 0.85 VDD VDD VDD V VIM Input middle voltage S0 and S1 only 0.40 VDD 0.50 VDD 0.60 VDD V VIL Input low voltage S0 and S1 only 0.0 0.0 0.15 VDD V VOH Output high voltage IOH = 6 mA 2.4 – – V VOL Output low voltage IOH = 6 mA – – 0.4 V Cin1 Input capacitance Xin/CLK (Pin 1) 3 4 5 pF Cin2 Input capacitance Xout (Pin 8) 6 8 10 pF Cin2 Input capacitance S0, S1, SSCC (Pins 7, 6, 5) 3 4 5 pF IDD1 Power supply current FIN = 25 MHz, CL= 0 – 17 23 mA IDD2 Power supply current FIN = 65 MHz, CL= 0 – 27 41 mA IDD3 Power supply current FIN = 100 MHz, CL= 0 – 42 59 mA Min Typ Max Unit Table 4. Electrical Timing Characteristics VDD = 3.3 V ± 10%, T = 0 °C to 70 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted Parameter Description Conditions ICLKFR Input clock frequency range VDD = 3.30 V 25 – 100 MHz tF Clock rise time (Pin 4) SSCLK at 0.4 – 2.4 V 1.0 1.8 2.8 ns tR Clock fall time (Pin 4) SSCLK at 0.4 – 2.4 V 1.0 1.8 2.8 ns DTYin Input clock duty cycle XIN/CLK (Pin 1) 25 50 75 % DTYout Output clock duty cycle SSCLK (Pin 4) 45 50 55 % JCC1 Cycle-to-cycle jitter Fin = 25 MHz–50 MHz, SSCC = 1 – 150 300 ps JCC2 Cycle-to-cycle jitter Fin = 50 MHz–100 MHz, SSCC = 1 – 130 200 ps Notes 1. Operation at any Absolute Maximum Rating is not implied. 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Document #: 38-07425 Rev. *G Page 7 of 13 CY25560 Absolute Maximum Conditions Industrial Grade[3, 4] Supply Voltage (VDD):...................................–0.5 V to +6.0 V DC Input Voltage: .................................. –0.5 V to VDD+0.5 V Junction Temperature ............................... –40 °C to +140 °C Operating Temperature:................................ –40 °C to 85 °C Storage Temperature ................................ –65 °C to +150 °C Static Discharge Voltage (ESD) .......................... 2,000 V-Min Table 5. DC Electrical Characteristics (Preliminary) VDD = 3.3 V ± 10%, T= –40 °C to 85 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted Parameter Description Conditions VDD Power supply range ±10% Min Typ Max Unit 2.97 3.3 3.63 V VIH Input high voltage S0 and S1 only 0.85 VDD VDD VDD V VIM Input middle voltage S0 and S1 only 0.40 VDD 0.50 VDD 0.60 VDD V VIL Input low voltage S0 and S1 only 0.0 0.0 0.15 VDD V VOH Output high voltage IOH = 6 mA 2.2 – – V VOL Output low voltage IOH = 6 mA – – 0.4 V Cin1 Input capacitance Xin/CLK (Pin 1) 3 4 5 pF Cin2 Input capacitance Xout (Pin 8) 6 8 10 pF Cin2 Input capacitance S0, S1, SSCC (Pins 7, 6, 5) 3 4 5 pF IDD1 Power supply current FIN = 25 MHz, CL= 0 – 17 24 mA IDD2 Power supply current FIN = 65 MHz, CL= 0 – 27 41 mA IDD3 Power supply current FIN = 100 MHz, CL= 0 – 42 61 mA Min Typ Max Unit Table 6. Electrical Timing Characteristics (Preliminary) VDD = 3.3 V ± 10%, T= –40 °C to 85 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted Parameter Description Conditions ICLKFR Input clock frequency range VDD = 3.30 V 25 – 100 MHz tF Clock rise time (Pin 4) SSCLK at 0.4 – 2.4 V 1.0 1.8 3.0 ns tR Clock fall time (Pin 4) SSCLK at 0.4 – 2.4 V 1.0 1.8 3.0 ns DTYin Input clock duty cycle XIN/CLK (Pin 1) 25 50 75 % DTYout Output clock duty cycle SSCLK (Pin 4) 45 50 55 % JCC1 Cycle-to-cycle jitter Fin = 25 MHz–50 MHz, SSCC = 1 – 150 300 ps JCC2 Cycle-to-cycle jitter Fin = 50 MHz–100 MHz, SSCC = 1 – 130 200 ps Notes 3. Operation at any Absolute Maximum Rating is not implied. 4. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Document #: 38-07425 Rev. *G Page 8 of 13 CY25560 Ordering Information Part Number Package Type Product Flow Pb-free CY25560SXC 8-pin SOIC Commercial, 0 C to 70 C CY25560SXCT 8-pin SOIC – Tape and Reel Commercial, 0 C to 70 C CY25560SXI 8-pin SOIC Industrial, –40 C to 85 C CY25560SXIT 8-pin SOIC – Tape and Reel Industrial, –40 C to 85 C Ordering Code Definition Document #: 38-07425 Rev. *G Page 9 of 13 CY25560 Package Drawing and Dimensions Figure 5. 8-Pin (150-Mil) SOIC S8 51-85066 *E Document #: 38-07425 Rev. *G Page 10 of 13 CY25560 Acronyms Acronym EMI Description electromagnetic interference ESD electrostatic discharge PLL phase locked loop SSC spread spectrum clock SSCG spread spectrum clock generator SVGA super video graphics array XVGA extended video graphics array Document Conventions Units of Measure Symbol Unit of Measure °C degree Celcius MHz megahertz mA milliamperes ns nanoseconds % percent pF picofarads ps picoseconds Document #: 38-07425 Rev. *G Page 11 of 13 CY25560 Document History Page Document Title: CY25560 Spread Spectrum Clock Generator Document Number: 38-07425 Revision ECN Orig. of Change Submission Date ** 115261 OXC 06/12/02 New Datasheet. *A 119441 RGL 10/17/02 Corrected the values in the Absolute Maximum Ratings to match the device. Description of Change *B 122704 RBI 12/30/02 Added power up requirements to maximum ratings information. *C 125549 RGL 05/15/03 Added Industrial Temperature Range to the device. Removed VOL2 and VOH2 spec in the DC specs table Changed IDD Values from 11/17/25 typ and 14/22/34max to 17/27/42 typ and 23/41/59 max Changed TF/TR values from 1.3/1.3 typ and 1.6/1.6 max to 1.8/1.8 typ and 2.8/2.8 max in the Electrical Char. table. Changed JCC1/2 values from 200/250 typ and 250/300 max to 150/130 typ to 300/200 max in the Electrical Char. table. Changed the low power dissipation from 36/56/82mW to 56/89/139mW respectively. Changed the low cycle-to-cycle jitter from 195/175/100ps-typ to 450/225/150 ps-max *D 314293 RGL See ECN Added Pb-free devices. *E 2762435 CXQ/HMT 09/11/09 Fixed the frequency in figure of SSCG section on page 3. Removed Pb devices from Ordering Information table. *F 2819309 VED 12/01/09 Minor change - updated revision number and corrected the document number at the beginning of this table. *G 3343531 PURU 08/12/2011 Document #: 38-07425 Rev. *G Added Ordering Code Definition, Acronyms, and Units of Measure. Updated Package Drawing and Dimensions. Page 12 of 13 CY25560 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07425 Rev. *G Revised August 12, 2011 Page 13 of 13 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.