CY25560
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator
Features
Applications
■
25 MHz to 100 MHz operating frequency range
■
Desktop, notebook, and tablet PCs
■
Nine different spread select options
■
VGA controllers
■
Accepts clock and crystal inputs
■
LCD panels and monitors
■
Low power dissipation:
❐ 56 mW at Fin = 25 MHz
❐ 89 mW at Fin = 65 MHz
❐ 139 mW at Fin = 100 MHz
■
Printers and multifunction devices (MFP)
Benefits
■
Peak electromagnetic interference (EMI) reduction by 8 to
16 dB
Center spread modulation
■
Fast time to market
■
Low cycle-to-cycle jitter
■
Cost reduction
■
8-pin SOIC package
■
Commercial and industrial temperature ranges
■
Frequency spread disable function
■
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
250 K
Xin/
CLK
1
Xout
8
VDD
VSS
REFERENCE
DIVIDER
PD
MODULATION
CONTROL
2
FEEDBACK
DIVIDER
INPUT
DECODER
LOGIC
3
VDD
4 SSCLK
VDD
20 K
20 K
20 K
VSS
5
6
7
SSCC
S1
S0
•
vco
DIVIDER
&
MUX
20 K
VSS
Cypress Semiconductor Corporation
Document Number: 38-07425 Rev. *J
Loop
Filter
CP
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY25560
Contents
Pinouts .............................................................................. 3
Pin Description ................................................................. 3
General Description ......................................................... 3
Frequency and Spread% Selection
(Center Spread) ................................................................. 4
Tri-Level Logic .................................................................. 4
SSCG Theory of Operation .............................................. 4
EMI .............................................................................. 4
SSCG .......................................................................... 5
Modulation Rate .......................................................... 5
CY25560 Application Schematic ..................................... 6
Absolute Maximum Ratings ............................................ 7
DC Electrical Characteristics .......................................... 7
XIN/CLK DC Specifications .............................................. 7
Electrical Timing Characteristics .................................... 7
Absolute Maximum Conditions ....................................... 8
Document Number: 38-07425 Rev. *J
DC Electrical Characteristics .......................................... 8
Electrical Timing Characteristics .................................... 8
Thermal Resistance .......................................................... 8
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Drawing and Dimensions ............................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC®Solutions ....................................................... 13
Cypress Developer Community ................................. 13
Technical Support ..................................................... 13
Page 2 of 13
CY25560
Pinouts
Figure 1. 8-pin SOIC pinout
XIN/CLK 1
8 XOUT
VDD 2
7 S0
CY25560
VSS 3
SSCLK 4
6 S1
5 SSCC
Pin Description
Pin Number
Pin Name
Type
1
Xin/CLK
I
Pin Description
Clock or crystal connection input. See the Table on page 4 for input frequency range
selection.
2
VDD
P
Positive power supply.
3
GND
P
Power supply ground.
4
SSCLK
O
Modulated clock output, that is the same frequency as the input clock or the crystal
frequency.
5
SSCC
I
Spread spectrum clock control (enable/disable) function. SSCG function is enabled when
input is high and disabled when input is low. This pin is pulled high internally.
6
S1
I
Tri-level logic input control pin used to select input frequency range and spread percent.
See the Tri-Level Logic on page 4 for programming details. Pin 6 has an internal resistor
divider network to VDD and VSS. See the Logic Block Diagram on page 1.
7
S0
I
Tri-level logic input control pin used to select input frequency range and spread percent.
See the Tri-Level Logic on page 4 for programming details. Pin 7 has an internal resistor
divider network to VDD and VSS. See the Logic Block Diagram on page 1.
8
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock
is used to drive xin/clk input (Pin 1).
General Description
The Cypress CY25560 is a spread spectrum clock generator
(SSCG) IC used to reduce the EMI found in today’s high-speed
digital electronic systems.
The CY25560 uses Cypress’s proprietary phase-locked loop
(PLL) and spread spectrum clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies of
clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
The CY25560 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L), and Middle (M) logic levels to select
Document Number: 38-07425 Rev. *J
one of the nine available spread% ranges. See the Frequency
and Spread% Selection (Center Spread) on page 4 for
programming details.
CY25560 is optimized for SVGA (40 MHz) and XVGA (65 MHz)
controller clocks and also suitable for applications where the
frequency range is 25 MHz to 100 MHz.
A wide range of digitally selectable spread percentages is made
possible by using three-level (High, Low, and Middle) logic at the
S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The CY25560 is available in an 8-pin SOIC package with 0 C to
70 C Commercial and –40 C to 85 C Industrial operating
temperature ranges.
Page 3 of 13
CY25560
Frequency and Spread% Selection (Center Spread)
25 – 50 MHz (Low Range)
Input
Frequency
(MHz)
25 – 35
35 – 40
40 – 45
45 – 50
S1=M
S0=M
(%)
4.3
3.9
3.7
3.4
S1=M
S0=0
(%)
3.8
3.5
3.3
3.1
S1=1
S0=0
(%)
3.4
3.1
2.8
2.6
S1=0
S0=0
(%)
2.9
2.5
2.4
2.2
S1=0
S0=M
(%)
2.8
2.4
2.3
2.1
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
50 – 100 MHz (High Range)
Input
Frequency
(MHz)
50 – 60
60 – 70
70 – 80
80 – 100
S1=1
S0=M
(%)
2.9
2.8
2.6
2.4
S1=0
S0=1
(%)
2.1
2.0
1.8
1.7
S1=1
S0=1
(%)
1.5
1.4
1.3
1.2
S1=M
S0=1
(%)
1.2
1.1
1.1
1.0
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
of these states have a defined voltage range that is interpreted
by the CY25560 as a ‘0’, ‘M’, or ‘1’ logic state. See the DC
Electrical Characteristics on page 7 for voltage ranges for each
logic state. The CY25560 has two equal value resistor dividers
connected internally to Pins 6 and 7 that produce the default ‘M’
(Middle) state if these pins are left unconnected (NC). Pins 6
and/or 7 can be tied directly to ground or VDD to program a logic
‘0’ or ‘1’ state, respectively.
Tri-Level Logic
With binary logic, four states can be programmed with two
control lines, whereas three-level logic can program nine logic
states using two control lines. Three-level logic in the CY25560
is implemented by defining a third logic state in addition to the
standard logic ‘1’ and ‘0’. Pins 6 and 7 of the CY25560 recognize
a logic state by the voltage applied to their respective pin. These
states are defined as ‘0’ (Low), ‘M’ (Middle), and ‘1’ (One). Each
Figure 2. Three-Level Logic Examples
VDD
CY25560
CY25560
S0
S0 = "M" (N/C)
7
S1 = "0" (GND)
6
SSCC = "1"
5
S0
S0 = "1"
7
S1
S0
S0 = "1"
7
S1 = "1"
6
SSCC = "1"
5
S1
S1 = "0" (GND)
6
SSCC = "1"
5
VDD
S1
VDD
SSCG Theory of Operation
The CY25560 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the CY25560 becomes a low-EMI clock generator.
The theory and detailed operation of the CY25560 is discussed
in the following sections.
Document Number: 38-07425 Rev. *J
VDD
CY25560
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50 percent. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the odd
harmonics, i.e., third, fifth, seventh, and so on. It is possible to
reduce the amount of energy contained in the fundamental and
odd harmonics by increasing the bandwidth of the fundamental
clock frequency. Conventional digital clocks have a very high Q
factor, that means that all of the energy at that frequency is
Page 4 of 13
CY25560
concentrated in a very narrow bandwidth, consequently, higher
energy peaks. Regulatory agencies test electronic equipment by
the amount of peak energy radiated from the equipment. By
reducing the peak energy at the fundamental and harmonic
frequencies, the equipment under test is able to satisfy agency
requirements for EMI. Conventional methods of reducing EMI
have been to use shielding, filtering, multilayer PCBs, and so on.
The CY25560 uses the approach of reducing the peak energy in
the clock by increasing the clock bandwidth, and lowering the Q
factor.
SSCG
SSCG uses a patented technology of modulating the clock over
a very narrow bandwidth and controlled rate of change, both
peak and cycle-to-cycle. The CY25560 takes a narrow band
digital reference clock in the range of 25 to 100 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand what
happens to a clock when SSCG is applied, consider a 65 MHz
clock with a 50 percent duty cycle. From a 65 MHz clock we know
the following:
50 %
Clock frequency = fc = 65 MHz
Clock period = Tc =1/65 MHz = 15.4 ns
50 %
Tc = 15.4 ns
If this clock is applied to the Xin/CLK pin of CY25560, the output
clock at Pin 4 (SSCLK) sweeps back and forth between two
frequencies. These two frequencies, F1 and F2, are used to
calculate to total amount of spread or bandwidth applied to the
reference clock at Pin 1. As the clock is making the transition
from F1 to F2, the amount of time and sweep waveform play a
very important role in the amount of EMI reduction realized from
an SSCG clock.
The modulation domain analyzer is used to visualize the sweep
waveform and sweep period. Figure 3 shows the modulation
profile of a 65 MHz SSCG clock. Notice that the actual sweep
waveform is not a simple sine or sawtooth waveform. Figure 3
also shows a scan of the same SSCG clock using a spectrum
analyzer. In this scan you can see a 6.48 dB reduction in the peak
RF energy when using the SSCG clock.
Modulation Rate
SSCGs utilize frequency modulation (FM) to distribute energy
over a specific band of frequencies. The maximum frequency of
the clock (Fmax) and minimum frequency of the clock (Fmin)
determine this band of frequencies. The time required to
transition from Fmin to Fmax and back to Fmin is the period of
the Modulation Rate, Tmod. Modulation Rates of SSCG clocks
are generally referred to in terms of frequency or
Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the device. The CY25560 has a fixed
divider count of 1166.
Figure 3. SSCG Clock, CY25560, Fin = 65 MHz
Spectrum Analyzer
Modulation Profile
BW = 2.46%
Document Number: 38-07425 Rev. *J
Page 5 of 13
CY25560
CY25560 Application Schematic
The schematic in Figure 4 demonstrates how the CY25560 is configured in a typical application. This application is shown as using
a 30 MHz fundamental crystal. In most applications, an external reference clock is used. Apply the external clock signal at Xin (Pin 1)
and leave Xout (Pin 8) unconnected (see Pin Description on page 3 for pin descriptions).
Contact Cypress if higher order crystal is to be used.
Figure 4. Application Schematic
VDD
C3
0.1 uF
2
C2
1
27 pF
C3
Y1
30 MHz
8
XIN/CLK
VDD
SSCLK
4
XOUT
27 pF
CY25560
VDD
5
S1
SSCC
VSS
S0
6
7
3
Document Number: 38-07425 Rev. *J
Page 6 of 13
CY25560
Junction Temperature .............................. –40 °C to +140 °C
Absolute Maximum Ratings
Operating Temperature .................................... 0 °C to 70 °C
Commercial Grade [1, 2]
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage (VDD) ...................................–0.5 V to +6.0 V
Static Discharge Voltage (ESD) ......................... 2,000 V-Min
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
DC Electrical Characteristics
VDD = 3.3 V ± 10%, T = 0 °C to 70 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
2.97
3.3
3.63
V
VDD
VDD
V
VDD
Power supply range
±10%
VIH
Input high voltage
S0 and S1 only
0.85 × VDD
VIM
Input middle voltage
S0 and S1 only
0.40 × VDD 0.50 × VDD 0.60 × VDD
VIL
Input low voltage
S0 and S1 only
0.0
0.0
0.15 × VDD
V
VOH
Output high voltage
IOH = 6 mA
2.4
–
–
V
VOL
Output low voltage
IOH = 6 mA
–
–
0.4
V
V
Cin1
Input capacitance
Xin/CLK (Pin 1)
3
4
5
pF
Cin2
Input capacitance
Xout (Pin 8)
6
8
10
pF
Cin2
Input capacitance
S0, S1, SSCC (Pins 7, 6, 5)
3
4
5
pF
IDD1
Power supply current
FIN = 25 MHz, CL = 0
–
17
23
mA
IDD2
Power supply current
FIN = 65 MHz, CL = 0
–
27
41
mA
IDD3
Power supply current
FIN = 100 MHz, CL = 0
–
42
59
mA
XIN/CLK DC Specifications
Parameter
Description
VIH(X)
Input high voltage,
XIN Clock Input
VIL(X)
Input low voltage,
XIN Clock Input
Conditions
F < 100 MHz
Min
Max
Units
80
–
% of VDD
–
15
% of VDD
Electrical Timing Characteristics
VDD = 3.3 V ± 10%, T = 0 °C to 70 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
ICLKFR
Input clock frequency range
VDD = 3.30 V
25
–
100
MHz
tF
Clock rise time (Pin 4)
SSCLK at 0.4 V–2.4 V
1.0
1.8
2.8
ns
tR
Clock fall time (Pin 4)
SSCLK at 0.4 V–2.4 V
1.0
1.8
2.8
ns
DTYin
Input clock duty cycle
XIN/CLK (Pin 1)
25
50
75
%
DTYout
Output clock duty cycle
SSCLK (Pin 4)
45
50
55
%
JCC1
Cycle-to-cycle jitter
Fin = 25 MHz–50 MHz, SSCC = 1
–
150
300
ps
JCC2
Cycle-to-cycle jitter
Fin = 50 MHz–100 MHz, SSCC = 1
–
130
200
ps
Notes
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document Number: 38-07425 Rev. *J
Page 7 of 13
CY25560
Junction Temperature .............................. –40 °C to +140 °C
Absolute Maximum Conditions
Operating Temperature ................................ –40 °C to 85 °C
Industrial Grade [3, 4]
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage (VDD) ...................................–0.5 V to +6.0 V
Static Discharge Voltage (ESD) ......................... 2,000 V-Min
DC Input Voltage .................................. –0.5 V to VDD+0.5 V
DC Electrical Characteristics
VDD = 3.3 V ± 10%, T= –40 °C to 85 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted
Parameter
Description
Conditions
Min
Typ
Max
Unit
2.97
3.3
3.63
V
S0 and S1 only
0.85 × VDD
VDD
VDD
V
S0 and S1 only
0.40 × VDD 0.50 × VDD 0.60 × VDD
VDD
Power supply range
±10%
VIH
Input high voltage
VIM
Input middle voltage
VIL
Input low voltage
S0 and S1 only
0.0
0.0
0.15 × VDD
V
VOH
Output high voltage
IOH = 6 mA
2.2
–
–
V
VOL
Output low voltage
IOH = 6 mA
–
–
0.4
V
Cin1
Input capacitance
Xin/CLK (Pin 1)
3
4
5
pF
Cin2
Input capacitance
Xout (Pin 8)
6
8
10
pF
Cin2
Input capacitance
S0, S1, SSCC (Pins 7, 6, 5)
3
4
5
pF
IDD1
Power supply current
FIN = 25 MHz, CL= 0
–
17
24
mA
IDD2
Power supply current
FIN = 65 MHz, CL= 0
–
27
41
mA
IDD3
Power supply current
FIN = 100 MHz, CL= 0
–
42
61
mA
Min
Typ
Max
Unit
V
Electrical Timing Characteristics
VDD = 3.3 V ± 10%, T= –40 °C to 85 °C and CL (Pin 4) = 15 pF, Unless Otherwise Noted
Parameter
Description
Conditions
ICLKFR
Input clock frequency range
VDD = 3.30 V
25
–
100
MHz
tF
Clock rise time (Pin 4)
SSCLK at 0.4 V–2.4 V
1.0
1.8
3.0
ns
tR
Clock fall time (Pin 4)
SSCLK at 0.4 V–2.4 V
1.0
1.8
3.0
ns
DTYin
Input clock duty cycle
XIN/CLK (Pin 1)
25
50
75
%
DTYout
Output clock duty cycle
SSCLK (Pin 4)
45
50
55
%
JCC1
Cycle-to-cycle jitter
Fin = 25 MHz–50 MHz, SSCC = 1
–
150
300
ps
JCC2
Cycle-to-cycle jitter
Fin = 50 MHz–100 MHz, SSCC = 1
–
130
200
ps
Thermal Resistance
Parameter [5]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
8-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
131
°C/W
41
°C/W
Notes
3. Operation at any Absolute Maximum Rating is not implied.
4. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. These parameters are guaranteed by design and are not tested.
Document Number: 38-07425 Rev. *J
Page 8 of 13
CY25560
Ordering Information
Part Number
Package Type
Product Flow
Pb-free
CY25560SXC
8-pin SOIC
Commercial, 0 C to 70 C
CY25560SXCT
8-pin SOIC – Tape and Reel
Commercial, 0 C to 70 C
CY25560SXI
8-pin SOIC
Industrial, –40 C to 85 C
CY25560SXIT
8-pin SOIC – Tape and Reel
Industrial, –40 C to 85 C
Ordering Code Definitions
CY 25560 S
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package: S = 8-pin SOIC
Base Device Part Number
Company ID: CY = Cypress
Document Number: 38-07425 Rev. *J
Page 9 of 13
CY25560
Package Drawing and Dimensions
Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07425 Rev. *J
Page 10 of 13
CY25560
Acronyms
Acronym
Document Conventions
Description
Units of Measure
EMI
Electromagnetic Interference
ESD
Electrostatic Discharge
°C
degree Celsius
PLL
Phase Locked Loop
MHz
megahertz
SOIC
Small Outline Integrated Circuit
mA
milliampere
SSC
Spread Spectrum Clock
ns
nanosecond
SSCG
Spread Spectrum Clock Generator
%
percent
SVGA
Super Video Graphics Array
pF
picofarad
XVGA
Extended Video Graphics Array
ps
picosecond
W
watt
Document Number: 38-07425 Rev. *J
Symbol
Unit of Measure
Page 11 of 13
CY25560
Document History Page
Document Title: CY25560, Spread Spectrum Clock Generator
Document Number: 38-07425
Revision
ECN
Orig. of
Change
Submission
Date
**
115261
OXC
06/12/02
*A
119441
RGL
10/17/02
Corrected the values in the Absolute Maximum Ratings to match the device.
*B
122704
RBI
12/30/02
Added power up requirements to maximum ratings information.
*C
125549
RGL
05/15/03
Added Industrial Temperature Range to the device.
Removed VOL2 and VOH2 spec in the DC specs table
Changed IDD Values from 11/17/25 typ and 14/22/34max to 17/27/42 typ and
23/41/59 max
Changed TF/TR values from 1.3/1.3 typ and 1.6/1.6 max to 1.8/1.8 typ and
2.8/2.8 max in the Electrical Char. table.
Changed JCC1/2 values from 200/250 typ and 250/300 max to 150/130 typ to
300/200 max in the Electrical Char. table.
Changed the low power dissipation from 36/56/82mW to 56/89/139mW
respectively.
Changed the low cycle-to-cycle jitter from 195/175/100ps-typ to 450/225/150
ps-max
*D
314293
RGL
See ECN
Updated Ordering Information:
Added Pb-free devices.
*E
2762435
CXQ / HMT
09/11/09
Updated SSCG Theory of Operation:
Updated SSCG:
Fixed the frequency in figure.
Updated Ordering Information:
Removed Pb devices.
*F
2819309
VED
12/01/09
Minor change - updated revision number and corrected the document number
at the beginning of this table.
*G
3343531
PURU
08/12/2011
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated Package Drawing and Dimensions.
*H
4511394
TAVA
09/26/2014
Added XIN/CLK DC Specifications.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*I
4586478
TAVA
03/12/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
5270202
PSR
05/13/2016
Updated SSCG Theory of Operation:
Updated SSCG:
Updated Figure 3.
Added Thermal Resistance.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
Document Number: 38-07425 Rev. *J
Description of Change
New data sheet.
Page 12 of 13
CY25560
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/memory
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Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2005-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07425 Rev. *J
Revised May 13, 2016
Page 13 of 13
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.