V-MT9V011 & V-MT9V011A i t n e l a 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR n o C d i f Datasheet Preliminary Version 0.85 2005-9-2 V-MT9V011 _100-0.85_En Notes1: The information is subject to change without notice. Before using this document, please confirm that this is the latest version. Notes2: Not all products and/or types are available in every country. Please check with a Vimicro sales representative availability and additional information. Important Notice l a i t n e Vimicro Corporation and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to Vimicro’ terms and conditions of sale supplied at the time of order acknowledgment. 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Vimicro is not responsible or liable for any such statements. www.vimicro.com Page 2 of 35 V-MT9V011 _100-0.85_En Content 1 GENERAL DESCRIPTION ..................................................................................................................... 7 FEATURES .......................................................................................................................................................... 8 APPLICATIONS ................................................................................................................................................... 8 2 BLOCK DIAGRAM .................................................................................................................................. 9 3 PIN LAYOUT............................................................................................................................................10 3.1 3.2 4 PIXEL DATA FORMAT .........................................................................................................................11 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.6 4.6.1 4.6.2 4.6.3 4.6.4 5 d i f n o C REGISTER MAP .....................................................................................................................................19 REGISTER DESCRIPTIONS ......................................................................................................................21 FUNCTION BLOCK DESCRIPTIONS .................................................................................................23 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 7 i t n e PIXEL ARRAY STRUCTURE ....................................................................................................................11 OUTPUT DATA FORMAT........................................................................................................................12 OUTPUT DATA TIMING .........................................................................................................................13 FRAME TIMING FORMULAS ...................................................................................................................14 SERIAL BUS DESCRIPTION ....................................................................................................................15 PROTOCOL ........................................................................................................................................15 SEQUENCE ........................................................................................................................................15 BUS IDLE STATE ...............................................................................................................................15 START BIT ..........................................................................................................................................15 STOP BIT ...........................................................................................................................................16 SLAVE ADDRESS .................................................................................................................................16 DATA BIT TRANSFER ........................................................................................................................16 ACKNOWLEDGE BIT .........................................................................................................................16 NO-ACKNOWLEDGE BIT ...................................................................................................................16 TWO-WIRE SERIAL INTERFACE SAMPLE READ AND WRITE SEQUENCES ..............................................16 16-BIT WRITE SEQUENCE .................................................................................................................16 16-BIT READ SEQUENCE ....................................................................................................................17 EIGHT-BIT WRITE SEQUENCE ............................................................................................................17 EIGHT-BIT READ SEQUENCE ..............................................................................................................17 REGISTERS..............................................................................................................................................19 5.1 5.2 6 l a PIN-OUT DIAGRAM ...............................................................................................................................10 PIN DEFINITIONS...................................................................................................................................10 WINDOW CONTROL ..............................................................................................................................23 BLANKING CONTROL ............................................................................................................................24 PIXEL INTEGRATION CONTROL .............................................................................................................24 PIXEL CLOCK SPEED .............................................................................................................................25 RESET ...................................................................................................................................................25 DIGITAL ZOOM .....................................................................................................................................25 TRUE DECIMATION MODE .....................................................................................................................25 READ MODE .........................................................................................................................................26 COLUMN MIRROR IMAGE..................................................................................................................26 ROW MIRROR IMAGE ........................................................................................................................26 COLUMN AND ROW SKIP ..................................................................................................................27 LINE VALID ......................................................................................................................................27 RECOMMDENDED GAIN SETTINGS ....................................................................................................27 ELECTRICAL CHARACTERISTICS...................................................................................................28 TABLE 7-1: DC ELECTRICAL CHARACTERISTICS ............................................................................................28 www.vimicro.com Page 3 of 35 V-MT9V011 _100-0.85_En TABLE 7-2: AC ELECTRICAL CHARACTERISTICS ............................................................................................29 7.3 PROPAGATION DELAYS FOR PIXCLK AND DATA OUT SIGNALS ............................................................29 7.4 PROPAGATION DELAYS FOR FRAME_VALID AND LINE_VALID SIGNALS ..........................................29 7.5 TWO-WIRE SERIAL BUS TIMING...............................................................................................................30 7.6 RELATIVE SPECTRAL RESPONSE ...............................................................................................................33 7.7 IMAGE CENTER OFFSET ............................................................................................................................33 8 PACKAGE INFORMATION ..................................................................................................................34 8.1 8.2 9 V-MT9V011 PACKAGING ....................................................................................................................34 V-MT9V011A PACKAGING:...............................................................................................................35 l a CONTACT INFORMATION ..................................................................................................................35 d i f i t n e n o C www.vimicro.com Page 4 of 35 V-MT9V011 _100-0.85_En Table List TABLE 1-1: TABLE 3-1: TABLE 3-2: TABLE 4-1: TABLE 4-2: TABLE 4-3: TABLE 5-1: TABLE 5-2: TABLE 5-3: TABLE 5-4: TABLE 5-5: TABLE 6-1: TABLE 6-2: TABLE 7-1: TABLE 7-2: TECHNICAL PARAMETERS .............................................................................................................. 7 PIN DESCRIPTIONS .........................................................................................................................10 PIN DESCRIPTIONS (CONTINUED): PIXEL DATA FORMAT ............................................................11 FRAME TIME ..................................................................................................................................14 CONSTANT VALUE .........................................................................................................................14 FRAME TIME—MASTER CLOCK SERIAL BUS DESCRIPTION .......................................................15 REGISTER MAP ..............................................................................................................................19 REGISTER MAP (CONTINUED) .......................................................................................................20 REGISTER DESCRIPTION ................................................................................................................21 REGISTER DESCRIPTION (CONTINUED).........................................................................................22 REGISTER DESCRIPTION (CONTINUED) FEATURE DESCRIPTION .................................................23 VERTICAL BLANKING ....................................................................................................................24 RECOMMENDED GAIN SETTINGS ..................................................................................................28 DC ELECTRICAL CHARACTERISTICS ............................................................................................28 AC ELECTRICAL CHARACTERISTICS ............................................................................................29 l a d i f i t n e n o C www.vimicro.com Page 5 of 35 V-MT9V011 _100-0.85_En Figure List FIGURE 2-1 FIGURE 2-2 FIGURE 3-1 FIGURE 4-1 FIGURE 4-2 FIGURE 4-3 FIGURE 4-4 FIGURE 4-5 FIGURE 4-6 FIGURE 4-7 FIGURE 4-8 FIGURE 4-9 FIGURE 6-1 FIGURE 6-2 FIGURE 6-3 FIGURE 6-4 FIGURE 6-5 FIGURE 6-6 FIGURE 7-1 FIGURE 7-2 FIGURE 7-3 FIGURE 7-4 FIGURE 7-5 FIGURE 7-6 FIGURE 7-7 FIGURE 7-8 FIGURE 7-9 FIGURE 7-10 FIGURE 7-11 FIGURE 18-1 FIGURE 18-2 SENSOR INTERFACE DIAGRAM ....................................................................................................... 9 TYPICAL CONFIGURATION (CONNECTION) ................................................................................... 9 PIN-OUT DIAGRAM – 28-PIN PLCC .............................................................................................10 PIXEL ARRAY DESCRIPTION .........................................................................................................11 PIXEL COLOR PATTERN DETAIL ...................................................................................................12 SPATIAL ILLUSTRATION OF IMAGE READOUT..............................................................................12 TIMING EXAMPLE OF PIXEL DATA ...............................................................................................13 ROW TIMING AND FRAME_VALID/LINE_VALID SIGNALS ...................................................13 TIMING DIAGRAM SHOWING A WRITE TO REG0X09 WITH THE VALUE 0X0284 ........................16 TIMING DIAGRAM SHOWING A READ FROM REG0X09; RETURNED VALUE 0X0284 ..................17 TIMING DIAGRAM SHOWING A WRITE TO REG0X09 WITH THE VALUE 0X0284 ........................17 TIMING DIAGRAM SHOWING A READ FROM REG0X09; RETURNED VALUE 0X0284 ..................18 READOUT OF 4 PIXELS IN NORMAL AND ZOOM 2X OUTPUT MODE ............................................25 READOUT OF 8 PIXELS IN NORMAL AND 2X DECIMATION OUTPUT MODE .................................26 READOUT OF 6 PIXELS IN NORMAL AND COLUMN MIRROR OUTPUT MODE ..............................26 READOUT OF 6 ROWS IN NORMAL AND ROW MIRROR OUTPUT MODE ......................................26 READOUT OF 8 PIXELS IN NORMAL AND COLUMN SKIP OUTPUT MODE ....................................27 DIFFERENT LINE VALID FORMATS ...............................................................................................27 PROPAGATION DELAYS FOR PIXCLK AND DATA OUT SIGNALS ................................................30 PROPAGATION DELAYS FOR FRAME_VALID AND LINE_VALID SIGNALS ............................30 DATA OUTPUT TIMING DIAGRAM .................................................................................................30 SERIAL HOST INTERFACE START CONDITION TIMING ................................................................31 SERIAL HOST INTERFACE STOP CONDITION TIMING ..................................................................31 SERIAL HOST INTERFACE DATA TIMING FOR WRITE..................................................................31 SERIAL HOST INTERFACE DATA TIMING FOR READ ....................................................................31 ACKNOWLEDGE SIGNAL TIMING AFTER AN 8-BIT WRITE TO THE SENSOR ................................32 ACKNOWLEDGE SIGNAL TIMING AFTER AN 8-BIT READ FROM THE SENSOR .............................32 SPECTRAL RESPONSE ..................................................................................................................33 IMAGE CENTER OFFSET ..............................................................................................................33 V-MT9V011 28-PIN PLCC PACKAGE OUTLINE DRAWING ......................................................34 V-MT9V011A 28-PIN PLCC PACKAGE OUTLINE DRAWING ...................................................35 l a d i f i t n e n o C www.vimicro.com Page 6 of 35 V-MT9V011 _100-0.85_En 1 GENERAL DESCRIPTION The Vimicro V-MT9V011 is a 1/4-inch VGA-format CMOS active-pixel digital image sensor that has the same functionalities and electrical characteristics as 1 Micron® Imaging sensor MT9V011.( Hereafter, the V-MT9V011 is referred as the sensor, in this datasheet.) The sensor’s active imaging pixel array is 649H x 489V. It incorporates sophisticated camera functions on-chip such as windowing, column and row mirroring. It is programmable through a simple two-wire serial bus interface and has very low power consumption. l a The sensors feature 2 DigitalClarity™—Micron’s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and integration advantages of CMOS. i t n e V-MT9V011A is a variation of V-MT9V011. The only difference between these two sensors is its package thickness. The thicknesses of V-MT9V011 and V-MT9V011A have 0.15 mm difference.. Table 1-1: Technical Parameters PARAMETER TYPICAL VALUE Optical Format 1/4-inch (4:3) Active Imager Size 3.58mm(H) x 2.69mm(V), 4.48mm Diagonal d i f Active Pixels 640H x 480V Pixel Size 5.6um x 5.6um Color Filter Array RGB Bayer Pattern Shutter Type Electronic Rolling Shutter (ERS) Maximum Data Rate/ Master Clock 13.5 MPS/27 MHz Frame Rate 30 fps at 27 MHz n o C VGA (640 x 480) CIF (352 x 288) Programmable up to 60 fps QVGA (320 x 240) Programmable up to 90 fps ADC Resolution 10-bit, on-chip Responsivity 2.0 V/lux-sec (550nm) Dynamic Range 60dB SNRMAX 45dB Supply Voltage Power Consumption 2.8V ±0.25V 70mW at 2.8V, 27 MHz, 30 fps Operating Temperature -20°C to +60°C Packaging 28-Pin PLCC The sensors can be operated in their default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs a VGA-size image at 30 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock which is synchronous with valid data. 1 2 Micron® is registered trademark by Micron Technology. Digital Claraity™ is a trademark that belongs to Micron Technology. www.vimicro.com Page 7 of 35 V-MT9V011 _100-0.85_En Features z z z z z z z DigitalClarity™ CMOS Imaging Technology Ultra low-power, low cost CMOS image sensor Superior low-light performance Simple two-wire serial interface Auto black level calibration Window Size: VGA, programmable to any smaller format (QVGA, CIF) Programmable Controls: Gain, frame rate, left-right and top-bottom image reversal, window size and panning l a Applications z z z z Cellular phones PDAs PC Cameras Toys and other battery-powered products d i f i t n e n o C www.vimicro.com Page 8 of 35 V-MT9V011 _100-0.85_En 2 BLOCK DIAGRAM d i f n o C l a i t n e Figure 2-1 Sensor Interface Diagram DGND AGND NOTE:1.5KΩ resistor value is recommended, but may be higher for slower two-wire speed. Figure 2-2 Typical Configuration (Connection) www.vimicro.com Page 9 of 35 V-MT9V011 _100-0.85_En 3 PIN LAYOUT 3.1 Pin-out Diagram The sensors pin-out are the same as following Figure 3-1 illustrated. l a Figure 3-1 Pin-Out Diagram – 28-Pin PLCC d i f 3.2 Pin Definitions i t n e The sensors pins and signals are defined in the following Table 3-1 and Table 3-2. Table 3-1: n o C PIN NUMBER TYPE Power Pin Descriptions 12 NAME VAA DESCRIPTION Analog Power (2.8V). 14 VAAPIX Power Pixel Power (2.8V). 1 VDD Power Digital Power Supply (2.8V). 28 DGND Ground Digital Ground. 11, 13 AGND Ground Analog Ground. 4 CLKIN Input 19 OE# Input 16 RESET# Input 15 SCAN_EN Input Tie to Digital Ground. 8 SCLK Input Serial Clock. 17 STANDBY Input 9 SDATA Bidirectional 3 DOUT0 Output Pixel Data Output Bit 0, D0 (LSB). 2 27 DOUT1 DOUT2 Output Output Pixel Data Output Bit 2, D2. Master Clock into sensor (27 MHz maximum). Output_Enable_Bar pin. When HIGH: disables the pixel data output drivers. Asynchronous reset of sensor when LOW. All registers assume factory defaults. When HIGH: disables the imager. Serial Data I/O. Pixel Data Output Bit 1, D1. www.vimicro.com Page 10 of 35 V-MT9V011 _100-0.85_En Table 3-2: PIN NUMBER Pin Descriptions (continued): Pixel Data Format 26 NAME DOUT3 TYPE Output DESCRIPTION Pixel Data Output Bit 3, D3. 25 DOUT4 Output Pixel Data Output Bit 4, D4. 24 DOUT5 Output Pixel Data Output Bit 5, D5. 23 DOUT6 Output Pixel Data Output Bit 6, D6. 22 DOUT7 Output Pixel Data Output Bit 7, D7. 21 DOUT8 Output Pixel Data Output Bit 8, D8. 20 DOUT9 Output Pixel Data Output Bit 9, D9 (MSB). 6 7 FRAME_VALID LINE_VALID Output Output 5 PIXCLK Output 10, 18 NC — Pixel Clock Output. Pixel data outputs are valid during rising edge of this clock. Frequency = 1/2 (master clock). Reserved 4 PIXEL DATA FORMAT d i f 4.1 Pixel Array Structure l a i t n e Active HIGH during frame of valid pixel data. Active HIGH during line of selectable valid pixel data (see Reg0x20 for options). The sensors pixel array is 668 columns by 496 (Top Right Corner) rows. The first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the column readout direction black level. The last column and the last row of pixels are also optically black. The black row data is used internally for automatic black level adjustment. There are 649 columns by 489 rows of optically active pixels, which provides a four-pixel boundary around the VGA (640 x 480) image to avoid boundary affects during color interpolation and correction. The additional active column and additional active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel, as shown in Figure 4-2. n o C Figure 4-1 Pixel Array Description www.vimicro.com Page 11 of 35 V-MT9V011 _100-0.85_En l a i t n e Figure 4-2 Pixel Color Pattern Detail The sensors use the RGB Bayer color pattern. Even numbered rows contain green and red color pixels, and odd numbered rows contain blue and green color pixels. Likewise, even numbered columns contain green and blue color pixels, and odd numbered 4.2 Output Data Format d i f The sensors image data is read-out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 4-3. The amount of horizontal and vertical blanking is programmable through Reg0x05 and Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure. See “Output Data Timing” section for the description of FRAME_VALID timing. n o C Figure 4-3 Spatial Illustration of Image Readout www.vimicro.com Page 12 of 35 V-MT9V011 _100-0.85_En 4.3 Output Data Timing The data output of the MT9V011 is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period. l a i t n e Figure 4-4 Timing Example of Pixel Data .... The rising edges of the PIXCLK signal are nominally timed to occur one-half of a master clock period after the DOUT edges. This allows PIXCLK to be used as a clock to latch the data. The PIXCLK is HIGH for one complete master clock period and then LOW for one complete master clock period. It is continuously enabled, even during the blanking period. The MT9V011 can be programmed to move the PIXCLK edge relative to the DOUT transitions from +1 to -1 master clock, in steps of one-half of a master clock. This can be achieved by programming the corresponding bits in Reg0x07. The parameters P, A, and Q in Figure 4-5 are defined in Table 4-1. d i f n o C Figure 4-5 Row Timing and FRAME_VALID/LINE_VALID Signals www.vimicro.com Page 13 of 35 V-MT9V011 _100-0.85_En 4.4 Frame Timing Formulas Table 4-1: Frame Time DEFAULT TIMING AT 27 MHZ 640 pixel clocks = 1280 master = 47.4µs PARAMETER NAME EQUATION A Active Data Time (Reg0x04 + 1) x (Reg0x0A + 2) P Frame Start/End Blanking 6 x (Reg0x0A + 2) Q Horizontal Blanking (113 + Reg0x05) x (Reg0x0A + 2) (minimum Reg0x05 value = 9) 244 pixel clocks = 488 master = 18.07µs A+Q Row Time (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) 884 pixel clocks = 1,768 master = 65.48µs V Vertical Blanking (Reg0x06 + 1) x (A + Q) + (Q - 2 x P) 25,868 pixel clocks = 51,736 master = 1.92ms Nrows x (A + Q) Frame Valid Time (Reg0x03 + 1) x (A + Q) - (Q - 2 x P) 424,088 pixel clocks = 848,176 master = 31.41ms F Total Frame Time d i f l a 6 pixel clocks = 12 master = 0.44µs i t n e (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 449,956 pixel clocks = 899,912 master = 33.33ms The constant 113 in the formulas in Table 4-1 is the constant value in default mode, when 8 dark columns are read out through Reg0x30. The constant follows the dark columns read out as shown in Table 4-2. Sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to Figure 4-6). The recommended master clock frequency is 27 MHz. n o C Table 4-2: Constant Value REG 0X30, BIT 1:0 CONSTANT 1x 121 For 16 columns 01 113 For 8 columns 00 107 For no dark columns read, no row-wise noise correction applied The vertical blanking and total frame time equations assume that the number of integration rows (bits 11 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 4-3.. www.vimicro.com Page 14 of 35 V-MT9V011 _100-0.85_En Table 4-3: Frame Time—Master Clock Serial Bus Description PARAMETER NAME EQUATION (MASTER CLOCK) DEFAULT TIMING V’ Vertical Blanking (long integration time) (Reg0x09 - Reg0x03) x (A + Q) + (Q - 2 x P) 25,868 pixel clocks = 51,736 master = 1.92 ms F’ Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) 449,956 pixel clocks = 899,912 master = 33.33ms l a 4.5 Serial Bus Description Registers are written to and read from the sensors through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out through the sensor serial data (SDATA) line. The SDATA line is pulled up to VDD off-chip by a 1.5KΩ resistor. Either the slave or master device can pull the SDATA line down—the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16 bits wide, and can be accessed through 16- or 8-bit two-wire serial bus sequences. 4.5.1 Protocol i t n e The two-wire serial interface defines several different transmission codes, as follows: a start bit the slave device 8-bit address a(n) (no) acknowledge bit an 8-bit message a stop bit d i f 4.5.2 Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device’s 8-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9V011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V011 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant eight bits to the register and then writing (or reading) the least significant eight bits to Reg0x80 (128). n o C 4.5.3 Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. 4.5.4 Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. www.vimicro.com Page 15 of 35 V-MT9V011 _100-0.85_En 4.5.5 Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. 4.5.6 Slave Address The 8-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. The write address of the sensor is 0xBA, while the read address is 0xBB. l a 4.5.7 Data Bit Transfer One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the serial clock—it can only change when the two-wire serial interface clock is LOW. Data is transferred eight bits at a time, followed by an acknowledge bit. 4.5.8 Acknowledge Bit i t n e The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. 4.5.9 No-Acknowledge Bit d i f The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. 4.6 Two-Wire Serial Interface Sample Read and Write Sequences n o C 4.6.1 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 4-6. A start bit given by the master, followed by the write address, starts the sequence. The image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit the image sensor will give an acknowledge bit. All 16 bits must be written before the register will be updated. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. Figure 4-6 Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 www.vimicro.com Page 16 of 35 V-MT9V011 _100-0.85_En 4.6.2 16-Bit Read Sequence A typical read sequence is shown in Figure 10. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Figure 4-7 l a i t n e Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 4.6.3 Eight-Bit Write Sequence To be able to write one byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper 8 bits to the desired register and the write the low 8 bit to special register address (Reg0x80). The register is not updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 4-7, a typical sequence for 8-bit writing is shown. The second byte is written to the special register (Reg0x80). d i f n o C Figure 4-8 Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 4.6.4 Eight-Bit Read Sequence To read one byte at a time the same special register address is used for the lower byte. The upper eight bits are read from the desired register. By following this with a read from the special register (Reg0x80) the lower eight bits are accessed (Figure 4-8). The master sets the no-acknowledge bits shown. www.vimicro.com Page 17 of 35 V-MT9V011 _100-0.85_En Figure 4-9 l a i t n e Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 d i f n o C www.vimicro.com Page 18 of 35 V-MT9V011 _100-0.85_En 5 REGISTERS 5.1 Register Map Table 5-1: Register Map REGISTER # (HEX) 0x00/0xFF Chip Version DATA FORMAT (BINARY) 1000 0010 0011 0010 0x01 Row Start 0000 000d dddd dddd 0x000A 0x02 Column Start 0000 00dd dddd dddd 0x0016 0x03 Window Height 0000 000d dddd dddd 0x01DF 0x04 Window Width 0000 00dd dddd dddd 0x05 Horizontal Blanking 0000 00dd dddd dddd 0x0083 0x06 Vertical Blanking 0000 dddd dddd dddd 0x001C 0x07 Output Control dddd dddd dddd dddd 0x3002 0x01FC DESCRIPTION DEFAULT VALUE (HEX) 0x8243 0x09 Shutter Width 0000 dddd dddd dddd 0x0A Pixel Clock Speed 0000 0000 000d dddd 0x0000 0x0B Restart 0000 0000 0000 000d 0x0000 0x0C Shutter Delay 0000 00dd dddd dddd 0x0000 0x0D Reset 0000 0000 0000 000d 0x0000 0x1E Digital Zoom 0x20 Read Mode 0x21 Reserved 0x22 Reserved 0x27 Reserved 0x2B Green1 Gain 0x2C 0000 0ddd 0000 00dd d i f Blue Gain n o C 0x2D Red Gain 0x2E Green2 Gain 0x0000 dddd dddd dddd dddd 0x1000 - 0x0000 - 0x0000 0x0024 0000 0ddd dddd dddd 0x0020 0000 0ddd dddd dddd 0x0020 0000 0ddd dddd dddd 0x0020 0000 0ddd dddd dddd 0x0020 - 0xF7B0 - 0x0005 - 0x002A 0x2F Reserved 0x30 Reserved 0x31 Reserved 0x32 Reserved - 0x0000 0x33 Reserved - 0x300F 0x34 Reserved 0x35 Global Gain 0x3B Reserved N/A l a i t n e 0x027F - 0x0100 0000 0ddd dddd dddd 0x0020 0x3C Reserved - 0x0820 0x3D Reserved - 0x068F 0x3E Reserved N/A 0x3F Reserved - 0x06A0 0x40 Reserved - 0x01E0 0x41 Reserved - 0x00D1 0x42 Reserved - 0x0882 0x58 Reserved - 0x0078 www.vimicro.com Page 19 of 35 V-MT9V011 _100-0.85_En DIGITAL IMAGE SE Table 5-2: Register Map (continued) REGISTER # (HEX) 0x59 DATA FORMAT (BINARY) - DESCRIPTION Reserved 0x5A 0x5B Reserved Reserved 0x5C Reserved R/O 0x5D Reserved R/O 0x5E Reserved R/O Reserved - 0x60 Reserved - 0x61 Reserved - 0x62 Reserved - 0x63 Reserved - 0x64 Reserved - Reserved Chip Enable 0xF7 Reserved R/O 0xF8 Reserved R/O Reserved 0xFB Reserved 0xFC Reserved 0xFD Reserved NOTE: l a i t n e 0x0000 0x65 Reserved 0x0427 0xA31D 0xF1 0xF9 0x0703 R/O 0x5F 0xFA DEFAULT VALUE (HEX) - 0000 0000 0000 00dd 0x0000 0x0418 0x0000 0x0000 0x0000 0x0001 0x002C d i f R/O R/O R/O R/O n o C 1 = always 1 0 = always 0 d = programmable ? = read only Do not change reserved register defaults; doing so may put device into an unknown state. www.vimicro.com Page 20 of 35 V-MT9V011 _100-0.85_En 5.2 Register Descriptions Table 5-3: Register Description REGISTER BIT DESCRIPTION 0x00 / 0xFF 0-15 This register is read-only and gives the chip identification number: 0x8243. Chip Version l a Window Control These registers control the size of the window. 0x01 0-8 0x02 0-9 0x03 0-8 0x04 0-9 First row to be read out—default = 0x000A (10). Minimum recommended value = 0x0006. i t n e First column to be read out—default = 0x0016 (22). Minimum recommended value = 0x0012 (18). Window height (number of rows - 1)—default = 0x01DF (479). Window width (number of columns - 1)—default = 0x027F (639). Minimum recommended value = 0x0009. Blanking Control These registers control the blanking time in a row and between frames. 0x05 0-9 Horizontal Blanking (number of columns)—default = 0x0083 (131 pixel clocks). Minimum value for 0x05 = 0x0009. Minimum recommended value for 0x05 = 0x007B (123 pixel clocks). 0x06 0-11 Vertical Blanking (number of rows -1)—default = 0x001C (28 rows). Minimum recommended value = 0x0003. d i f Output Control This register controls various features of the output format for the sensor. 0x07 0 Synchronize changes (copied to Reg0xF1, bit1). 0 = normal operation, update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to “0.” 1 Chip Enable (copied to Reg0xF1, bit0). 1 = normal operation. 0 = stop sensor readout. When this is returned to “1,” sensor readout restarts at the starting row in a new frame. The digital power consumption can then also be reduced to less than 5uA by turning off the master clock. 4 By setting this bit to “1,” the sampling and reset timing of the pixels will be halved. This bit should therefore only be used if the master clock frequency is 13.5 MHz or less. When this bit is set the minimum recommended horizontal blanking value is 17, compared to 123 when this bit is not set. Shutter Delay will be master clocks divided by 2 when this bit is set, compared to master clocks divided by 4 when this bit is 0. Note: Use this register for 15 fps with 12 MHz master clock. Allow Shutter Width to be exactly one full frame. 0 = normal operation = Maximum Shutter Width equals the total number of rows - 1. If Shutter Width exceeds the number of rows -1, the total number of rows in the image will be increased to Shutter Width + 1. 1 = Maximum Shutter Width equals the total number of rows. When the Shutter Width exceeds the number of rows, the total number of rows in the image will be increased to match the Shutter Width. n o C 5 6 8 -11 Reserved. 0 = normal operation. Shift pixel clock: (11,10,9,8) = (1, x, x, x): shift pixel clock 1 clock earlier (0, 1, x, x): shift pixel clock ½ clock earlier (0, 0, 1, x): delay pixel clock by ½ clock(0, 0, 0, 1): delay pixel clock by 1 clock (0, 0, 0, 0): no delay pixel clock (default mode). www.vimicro.com Page 21 of 35 V-MT9V011 _100-0.85_En Table 5-4: Register Description (continued) REGISTER BIT DESCRIPTION 15 Invert pixel clock: 0 = normal operation. 1 = invert pixel clock. Pixel Integration Control These registers (along with the Window Size and Blanking registers) control the integration time for the pixels. 0x09 0x0C 0-11 0-9 0x0A 4-0 0x0B 0 0x0D 0 Number of rows of integration, default = 0x01FC (508). l a Reset delay, default = 0x0000 (0). This is the number of master clocks x 4 that the timing and control logic waits before asserting the reset for a given row. Pixel Clock Speed This register determines the pixel data rate, default = 0x0000 (0). Pixel clock period = 2 master clocks + [Reg0x0A, bits (4-0)]. The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07 appropriately. Maximum value for 0x0A = 0x0015. i t n e Frame Restart Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current frame and restart from the first row. This register automatically resets itself to 0x0000 after the frame restart. The first frame after this event is considered to be a "bad frame" (see description for Reg0x20, bit 0). Reset (Soft) This register is used to reset the sensor to its default, power-up state. To reset the MT9V011, first write a “1” into bit 0 of this register to put the MT9V011 in reset mode, then write a “0” into bit 0 to resume operation. d i f Zoom Mode / True Decimation Mode 0x1E 0 Zoom by 2. 1 8 Zoom by 4 (if bit 0 is 0). 9 True decimation by 4. Decimate 4x will skip 3 rows/columns for every row/column read out, without considering the colors of the pixels. True decimation by 2. Decimate 2x will skip every other column and row, without considering the colors of the pixels. n o C 10 True decimation by 8. Decimate 8x will skip 7 rows/columns for every row/column read out, without considering the colors of the pixels. Read Mode This register is used to control many aspects of the readout of the sensor. 0x20 0 Show bad frames: 1 = output all frames (including bad frames). 0 = only output good frames. A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 3 4 Column skip: 1= read out two columns, and then skip two columns (as with rows). 0 = normal readout. Row skip: 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13…). 0 = normal readout. 9 "Continuous" Line Valid (continue producing line valid during vertical blanking). 0 = Normal Line Valid (default, no line valid during vertical blanking). 10 Line valid = "Continuous" Line Valid XOR Frame Valid. 0 = Normal Line Valid. Ineffective if Continuous Line Valid is set. 11 The four dark rows 0 to 3 are read out in addition to the valid data. 0 = normal readout. VGA DIGITAL www.vimicro.com Page 22 of 35 V-MT9V011 _100-0.85_En IMAGE SENSOR Table 5-5: Register Description (continued) Feature Description REGISTER BIT DESCRIPTION To preserve a right-reading image and the correct color order, all four of these bits should be set to “1” to invert the image. 5 1 = readout starting 1 column later. 0 = normal readout. 7 14 15 1 = read out from right to left (mirrored). 0 = normal readout. i t n e 1 = read out from bottom to top (upside down). 0 = normal readout. Gain Settings The gain can be individually controlled for each color in the Bayer pattern. 0x2B l a 1 = readout starting 1 row later. 0 = normal readout. Green1 Gain—default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6:0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x2C Blue Gain—default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x2D d i f Red gain—default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x2E Green2 gain—default = 0x0020 (32) = 1x gain. n o C 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x35 GlobalGain—default = 0x0020 (32) = 1x gain. This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 6 FUNCTION BLOCK DESCRIPTIONS 6.1 Window Control Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Window Height (row size), and Reg0x04 Window Width (column size) These registers control the size and starting coordinates of the window. By changing these registers, any image format smaller than or equal to VGA can be specified. www.vimicro.com Page 23 of 35 V-MT9V011 _100-0.85_En 6.2 Blanking Control Reg0x05 Horizontal Blanking, and Reg0x06 Vertical Blanking Blanking Control: These registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). Horizontal blanking is specified in terms of pixel clocks. Vertical blanking is specified in terms of row readout times. (The programmed value is one less than the actual value.) The actual imager timing can be calculated using l a Table 4-1 describes "Row Timing and FRAME_VALID/LINE_VALID Signals.” The number of dark rows read out depends on the vertical blanking set as shown in the Table 6-1. Table 6-1: Vertical Blanking REG0X06 i t n e # DARK ROWS 0 0 1-2 2 3+ 4 6.3 Pixel Integration Control Reg0x09 Shutter Width, and Reg0x0C Shutter Delay d i f These registers (along with the Window Size and horizontal blanking registers) control the integration time for the pixels. Reg0x09: number of rows of integration, default =0x01FC (508) Reg0x0C: reset delay, default = 0x0000 (0). This is the number of master clocks that the timing and controllogic waits before asserting the reset for a given row. The actual total integration time, t INT, is: n o C t INT = Reg0x09 x Row Time - Overhead time - Reset delay, where: Row Time = (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) master clock periods Overhead time = K x 57 master clock periods Reset delay = K x Reg0x0C master clock periods If the value in Reg0x0C exceeds (row time - 444)/K master clock cycles, the row time will be extended by (K x Reg0x0C - (row time - 444)) clock cycles. Where : K = 4 when Reg0x07[4] = 0, and K = 2 when Reg0x07[4] = 1 In this expression the row time term corresponds to the number of rows integrated. The overhead time is the time between the READ cycle and the RESET cycle, and the final term is the effect of the reset delay. Typically, the value of Reg0x09 (Shutter Width) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the sensor will add t additional blanking rows as needed. A second constraint is that INT must be adjusted to avoid t banding in the image from light flicker. Under 60 Hz flicker, this means INT must be a multiple www.vimicro.com Page 24 of 35 V-MT9V011 _100-0.85_En t of 1/120 of a second. Under 50 Hz flicker, INT must be a multiple of 1/100 of a second. 6.4 Pixel Clock Speed Reg0x0A Pixel Clock Speed The pixel clock speed is set by Reg0x0A. The pixel clock period will be the number set plus two master clock cycles. The default value is 0, which is equal to 2 master clock cycles. With a master clock frequency of 27 MHz the PIXCLK frequency will be 13.5 MHz. The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07 appropriately. l a 6.5 Reset Reg0x0D Reset i t n e This register is used to reset the sensor to its default, power-up state. To reset the MT9V011, first write a “1” into bit 0 of this register, then write a “0” into bit 0 to resume operation. 6.6 Digital Zoom Reg0x1E Digital Zoom/True decimation In zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. This is designed to give the controller logic time to repeat data to fill in window that is either 2 or 4 times larger with repeated data d i f The pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. In zoom by 2 mode, every row is followed by a blank row (with its own line valid, but all data bits = 0) of equal time. In zoom by 4 mode, every row is followed by three blank rows. The combination of this register and an appropriate change to the window sizing registers allows the user to zoom to a region of interest without affecting the frame rate. n o C Figure 6-1 Readout of 4 Pixels in Normal and Zoom 2x Output Mode 6.7 True Decimation mode Reg0x1E Digital Zoom/True decimation True decimation mode is intended for use in sensors without color filtering. There are three modes with different amount of decimation. In decimate 2x every other column and row is skipped. In decimate 4x, three rows/columns will www.vimicro.com Page 25 of 35 V-MT9V011 _100-0.85_En be skipped for every row/column read out, and in decimate 8x seven rows/columns will be skipped for every row/column read out. Decimate 2x is shown in Figure 6-2. In decimation mode the global gain register should be used to set the gain. l a i t n e Figure 6-2 Readout of 8 Pixels in Normal and 2x Decimation Output Mode 6.8 Read Mode 6.8.1 Column Mirror image By setting bits 14 and 5 of Reg0x20 the readout order of the columns will be reversed, as shown in Figure 6-3. d i f n o C Figure 6-3 Readout of 6 Pixels in Normal and Column Mirror Output Mode 6.8.2 Row Mirror Image By setting bits 15 and 7 of Reg0x20 the readout order of the rows will be reversed, as shown in Figure 6-4. Figure 6-4 Readout of 6 Rows in Normal and Row Mirror Output Mode www.vimicro.com Page 26 of 35 V-MT9V011 _100-0.85_En 6.8.3 Column and Row Skip By setting bit 3 of Reg0x20 only half of the columns set will be read out, as shown in , as shown in Figure 6-5., The row skip works in the same way and will only read out two out of four rows. For both row and column skip the number of rows/columns read out will be half of what is set in Reg0x03 and Reg0x04. Figure 6-5 l a i t n e Readout of 8 Pixels in Normal and Column Skip Output Mode 6.8.4 Line Valid d i f By setting bit 9 and 10 of Reg0x20 the line valid signal can get three different output formats. The formatting is shown in Figure 6-6 when reading out four rows and two vertical blanking rows. In the last format the line valid signal is the XOR between the continuously line valid signal and the frame valid signal. n o C Figure 6-6 Different Line Valid Formats 6.8.5 Recommdended Gain Settings The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be set globally by Reg0x35. The analog gain is set by bit[8:0] of the corresponding register as following: www.vimicro.com Page 27 of 35 V-MT9V011 _100-0.85_En Gain = (Bit[8] + 1) x (Bit[7] + 1) x (Bit[6:0]/32) Digital gain is set by bits 9 and 10 of the same registers. The analog gain circuitry (pre-ADC) is designed to offer signal gains from 1 to 15.875. The minimum gain of 1 (register set to 0x0020) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be followed at all times. Since bits 7 and 8 of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, while the same overall gain. Table 6-2 lists the recommended gain settings. l a i t n e Table 6-2: Recommended Gain Settings RECOMMENDED SETTINGS (GAIN REGISTERS) DESIRED GAIN CONVERSION FORMULA (ARITHMETIC) 1.000 to 1.969 0x0020 to 0x003F (Register value)/32 2.000 to 7.938 0x00A0 to 0x00FF (Register value - 128)/16 8.000 to 15.875 0x01C0 to 0x01FF (Register value - 384)/8 d i f 7 ELECTRICAL CHARACTERISTICS Table 7-1: DC Electrical Characteristics (VDD = VAA = 2.8 ±0.25V; TA = Ambient = 25°C; 30 fps at 27 MHz) SYMBOL DEFINITION VIH Input High Voltage VIL IIN VOH VOL IOH IOL IOZ IAA IDD n o C Input Low Voltage Input Leakage Current CONDITION No Pull-up Resistor; VIN = VDD or DGND Output High Voltage MIN TYP MAX UNIT VDD-0.25 VDD+0.25 V -0.3 -5 0.8 5 V µA VDD-0.2 NOTES V Output Low Voltage 0.2 V Output High Current 5.0 µA Output Low Current 5.0 5.0 µA µA Tri-state Output Leakage Current Analog Operating Current CLKIN = 27 MHz; default setting, CLOAD = 10pF 14.0 20.0 28.0 mA Digital Operating Current CLKIN = 27 MHz; default setting, CLOAD = 10pF STDBY = VDD 3.0 5.0 8.0 mA 0.0 0.0 5.0 µA 1, 2 STDBY = VDD 0.0 1.0 5.0 µA 1, 2 IAA Standby Analog Standby Supply Current IDD Standby Digital Standby Supply Current www.vimicro.com Page 28 of 35 V-MT9V011 _100-0.85_En NOTE: 1 To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles before turning off the master clock. Two master clock cycles are required to place the analog circuitry into standby, low-power mode. 2 When STANDBY is de-asserted, standby mode is exited immediately (within several master clocks), but the current frame and the next two frames will be invalid. The fourth frame will contain a valid image. (VDD = VAA = 2.8 ±0.25V; TA = Ambient = 25°C; 30 fps at 27 MHz) Table 7-2: SYMBOL fCLKIN AC Electrical Characteristics DEFINITION CONDITION MIN Input Clock Frequency Clock Duty Cycle 45 TYP MAX UNIT 27 27 MHz 50 55 % l a tR Input Clock Rise Time 2.5 ns tF Input Clock Fall Time 2.0 ns CLOAD = 10pF 12.0 10.0 ns CLOAD = 10pF 15.0 14.0 ns 9.0 ns 12.0 ns tPLHP tPHLP CLKIN to PIXCLK propagation LOW-to-HIGH HIGH-TO-LOW tDSETUP tDHOLD delay: PIXCLK to DOUT(9:0) Setup Time Hold Time Data Hold Time from PIXCLK falling edge tOH CLKIN to FRAME_VALID LINE_VALID propagation tPLHF,L delay: LOW-to-HIGH, tPHLF,L HIGH-to-LOW and i t n e CLOAD = 10pF 11.0 tPLHD tPHLD CLKIN to DOUT (9:0) propagation delay: LOW-to-HIGH, HIGH-to-LOW CLOAD = 10pF 7.5 7.0 ns tOUTR Output Rise Time CLOAD = 10pF 7.0 ns tOUTF Output Fall Time CLOAD = 10pF 9.0 ns d i f NOTE: 1. For 30 fps operation with a 27 MHz clock, it is very important to have a precise duty cycle equal to 50%. With a slower frame rate and a slower clock the clock duty cycle can be relaxed. 7.3 n o C Propagation Delays for PIXCLK and Data Out Signals The typical output delay, relative to the master clock edge, is 7.5 ns. Note that the data outputs change on the falling edge of the master clock, with the pixel clock rising on the subsequent rising edge of the master clock. 7.4 Propagation Delays for FRAME_VALID and LINE_VALID Signals The LINE_VALID and FRAME_VALID signals change on the same falling master clock edge as the data output. The LINE_VALID goes HIGH on the same falling master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock falling edge as the end of the output of the last valid pixel's data. As shown in the “Output Data Timing” , FRAME_VALID goes HIGH 6 pixel clocks prior to the time that the first LINE_VALID goes HIGH. It returns LOW at a time corresponding to 6 pixel clocks after the last LINE_VALID goes LOW. www.vimicro.com Page 29 of 35 V-MT9V011 _100-0.85_En l a Figure 7-1 Propagation Delays for PIXCLK and Data Out Signals Figure 7-2 i t n e Propagation Delays for FRAME_VALID and LINE_VALID Signals n o C d i f Figure 7-3 Data Output Timing Diagram PIXCLK = max. 27 MHz t FVHOLD t FVSETUP = / setup time for FRAME_VALID before rising edge of PIXCLK / = 18ns = / hold time for FRAME_VALID after rising edge of PIXCLK / = 18ns LINE_VALID before rising edge of PIXCLK / = 18ns t t LVHOLD t LVSETUP = / setup time for = / hold time for LINE_VALID after rising t edge of PIXCLK / = 18ns DSETUP = / setup time for DOUT before rising edge of PIXCLK / = 15ns DHOLD = / hold time for DOUT after rising edge of PIXCLK / = 14ns Frame start: FF00 00A0 Line start: FF00 0080 Line end: FF00 0090 Frame end: FF00 0010 7.5 Two-Wire Serial Bus Timing The two-wire serial bus operation requires certain Timing for Write minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles. www.vimicro.com Page 30 of 35 V-MT9V011 _100-0.85_En Figure 7-4 Serial Host Interface Start Condition Timing Figure 7-5 i t n e Serial Host Interface Stop Condition Timing d i f l a n o C Figure 7-6 Serial Host Interface Data Timing for Write Figure 7-7 Serial Host Interface Data Timing for Read www.vimicro.com Page 31 of 35 V-MT9V011 _100-0.85_En Figure 7-8 Figure 7-9 l a Acknowledge Signal Timing After an 8-bit Write to the Sensor i t n e Acknowledge Signal Timing After an 8-bit Read from the Sensor NOTE:After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float high. On the following cycle a start or stopbit may be used. d i f n o C www.vimicro.com Page 32 of 35 V-MT9V011 _100-0.85_En 7.6 Relative Spectral Response l a d i f Figure 7-10 7.7 i t n e Spectral Response n o C Image Center Offset Chip Center Sensor Chip NOTE: Not to scale. Figure 7-11 Image Center Offset www.vimicro.com Page 33 of 35 V-MT9V011 _100-0.85_En 8 Package Information There are two different packages used for the same silicon dies, named as V-MT9V011 and V-MT9V011A respectively. The difference of these two packages is really tiny. Mainly difference is the thickness of the chips. The thicknesses of V-MT9V011 and V-MT9V011A have 0.15 mm difference. 8.1 V-MT9V011 Packaging l a d i f i t n e n o C Figure 18-1 V-MT9V011 28-Pin PLCC Package Outline Drawing www.vimicro.com Page 34 of 35 V-MT9V011 _100-0.85_En 8.2 V-MT9V011A Packaging: l a Figure 18-2 d i f V-MT9V011A 28-Pin PLCC Package Outline Drawing n o C 9 Contact Information Vimicro Corporation 15/F Shining Tower No.35 Xueyuan Road Haidian District, Beijing P. R. China 100083 Tel: 86-10-6894-8888 Fax: 86-10-6894-4075 i t n e Vimicro Corporation – USA 1758 N. Shoreline Blvd. Mountain View, CA 94043 U.S.A. Tel: 1-650-966-1882 Fax: 1-650-966-1885 Web: www.vimicro.com www.vimicro.com Page 35 of 35