CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum Features ■ Two fully integrated phase locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ ■ Glitch-free outputs while frequency switching ■ 8-pin SOIC package ■ Commercial and Industrial temperature ranges ■ Multiple high performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ VDD supply voltage options: ❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482 ❐ 1.8V for CY25422 Application specific Programmable EMI reduction using Spread Spectrum for clocks ■ Programmable PLLs for system frequency margin tests ■ Selectable output clock voltages independent of VDD: ❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482 ❐ 1.8V for CY25422 Meets critical timing requirements in complex system designs ■ Suitability for PC, consumer, portable, and networking applications ■ Capable of Zero PPM frequency synthesis error ■ Uninterrupted system operation during clock frequency switch ■ Application compatibility in standard and low power systems Wide operating output frequency range ❐ 3 to 166 MHz ■ Programmable Spread Spectrum with Center and Down Spread option and Lexmark and Linear modulation profiles ■ Three clock outputs with Programmable drive strength Benefits Reference Clock input voltage range ❐ 2.5V, 3.0V, and 3.3V for CY25482 ❐ 1.8V for CY25402 and CY25422 ■ ■ ■ ■ Frequency Select feature with option to select four different frequencies ■ Power Down, Output Enable, and SS ON/OFF controls ■ Low jitter, high accuracy outputs ■ Ability to synthesize nonstandard frequencies with Fractional-N capability Block Diagram Crossbar Switch XIN/ EXCLKIN XOUT PLL 1 (SS) OSC CLK1 Dividers and MUX Drive and FS0 Output PLL 2 (SS) Control REFOUT Strength Logic Control FS1 CLK2 SSON PD#/OE Cypress Semiconductor Corporation Document #: 001-12565 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 13, 2007 [+] Feedback CY25402/CY25422/CY25482 Table 1. Device Selector Guide Device Crystal Input EXCKLKIN Input VDD CY25402 Yes 1.8V LVCMOS 2.5V, 3.0V, 3.3V CY25482 No 2.5V, 3.0V, 3.3V LVCMOS 2.5V, 3.0V, 3.3V CY25422 Yes 1.8V LVCMOS 1.8V Figure 1. Pin Diagram - CY25402 8-LD SOIC XIN/ EXCLKIN 1 VDD 2 CY25402 8 XOUT 7 GND CLK1 3 6 CLK2/SSON REFOUT/ FS0 4 5 PD#/OE/FS1 Table 1. Pin Definition - CY25402 (2.5V, 3.0V or 3.3V Supply) Pin Number Name IO Description 1 XIN/EXCLKIN Input 2 VDD Power Power Supply: 2.5V, 3.0V or 3.3V 3 CLK1 Output Programmable Clock Output with Spread Spectrum 4 REFOUT/FS0 Output/Input Multifunction Programmable pin: Reference Clock Output or Frequency Select pin 5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin 6 CLK2/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin 7 GND Power Power Supply Ground 8 XOUT Output Crystal Output Document #: 001-12565 Rev. *B Crystal Input or 1.8V External Clock Input Page 2 of 10 [+] Feedback CY25402/CY25422/CY25482 Figure 2. Pin Diagram - CY25482 8-LD SOIC EXCLKIN 1 VDD 2 CY25482 8 DNU 7 GND CLK1 3 6 CLK2/SSON REFOUT/ FS0 4 5 PD#/OE/FS1 Table 2. Pin Definition - CY25482 (2.5V, 3.0V or 3.3V Supply) Pin Number Name IO Description 1 EXCLKIN Input 2.5V, 3.0V or 3.3V External Clock Input 2 VDD Power Power Supply: 2.5V, 3.0V or 3.3V 3 CLK1 Output Programmable Clock Output with Spread Spectrum 4 REFOUT/FS0 Output/Input Multifunction Programmable pin: Reference Clock Output or Frequency Select pin 5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin 6 CLK2/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin 7 GND Power Power Supply Ground 8 DNU Output Do not use this pin Figure 3. Pin Diagram - CY25422 8-LD SOIC XIN/ EXCLKIN 1 VDD 2 CLK1 3 6 CLK2/SSON REFOUT/ FS0 4 5 PD#/OE/FS1 CY25422 8 XOUT 7 GND Table 3. Pin Definition - CY25422 (1.8V Supply) Pin Number Name IO Input Description 1 XIN/EXCLKIN Crystal Input or 1.8V External Clock Input 2 VDD Power Power Supply: 1.8V 3 CLK1 Output Programmable Clock Output with Spread Spectrum 4 REFOUT/FS0 Output/Input Multifunction Programmable pin: Reference Clock Output or Frequency Select pin 5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin 6 CLK2/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin 7 GND Power Power Supply Ground 8 XOUT Output Crystal Output Document #: 001-12565 Rev. *B Page 3 of 10 [+] Feedback CY25402/CY25422/CY25482 General Description 2 Configurable PLLs The CY25402, CY25482 and CY25422 have two programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having two PLLs is that a single device generates two independent frequencies from a single crystal. Input Reference Clocks The input reference clock can be either a crystal or a clock signal, for CY25402 and CY25422 while just a clock signal for CY25482. The input frequency range for crystal (XIN) is 8 MHz to 48 MHz and that for external reference clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the reference clock input for CY25482 is 2.5V/3.0V/3.3V while that for CY25402 and CY25422 is 1.8V. This gives user an option for this device to be compatible for different input clock voltage levels in the system. VDD Power Supply Options These devices have programmable power supply options. The CY25402/CY25482 is a high voltage part that can be programmed to operate at any voltage 2.5V, 3.0V, or 3.3V while CY25422 is a low voltage part that can operate at 1.8V. Output Source Selection These devices have programmable input sources for each of its clock outputs. There are three available clock sources and these clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock source selection is done by using three out of three crossbar switch. Thus, any one of these three available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have two independent clock outputs. Spread Spectrum Control Both PLLs (PLL1 and PLL2) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK2/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. Frequency Select frequency select inputs, can be used to select among these arbitrarily programmed frequency settings. Each output has programmable output divider options. Glitch-Free Frequency Switch When the frequency select pin, FS(1:0) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. PD#/OE Mode Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to operate as either frequency select (FS1), power down (PD#) or output enable (OE) mode. PD# is a low-true input. If activated it shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. When this pin is programmed as Output Enable (OE), clock outputs can be enabled or disabled using OE (pin 5). Individual clock outputs can be programmed to be sensitive to this OE pin. Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Table 4 shows the typical rise and fall times for different drive strength settings. Table 4. Output Drive Strength Output Drive Strength Rise/Fall Time (ns) (Typical Value) Low 6.8 Mid Low 3.4 Mid High 2.0 High 1.0 Generic Configuration and Custom Frequency There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The devices, CY25402, CY25482 and CY25422 can be custom programmed to any desired frequencies and listed features. For customer specific programming, please contact local Cypress Field Application Engineer (FAE) or sales representative. Each PLL can be programmed for up to four different frequencies. There are two multifunction programmable pins, REFOUT/FS0 and PD#/OE/FS1 which if programmed as Document #: 001-12565 Rev. *B Page 4 of 10 [+] Feedback CY25402/CY25422/CY25482 Absolute Maximum Conditions Parameter Description Condition VDD Supply Voltage for CY25402/CY25482 VDD Supply Voltage for CY25422 VIN Input Voltage for CY25402/CY25482 VIN TS Min Max Unit –0.5 4.5 V –0.5 2.6 V Relative to VSS –0.5 VDD+0.5 V Input Voltage for CY25422 Relative to VSS –0.5 2.2 V Temperature, Storage Non Functional –65 +150 °C ESDHBM ESD Protection (Human Body Model) JEDEC EIA/JESD22-A114-E 2000 UL-94 Flammability Rating V-0 @1/8 in. MSL Moisture Sensitivity Level SOIC package Volts 10 ppm Max Unit 3 Recommended Operating Conditions Parameter Description Min Typ VDD VDD Operating Voltage for CY25402/CY25482 2.25 – 3.60 V VDD VDD Operating Voltage for CY25422 1.65 1.8 1.95 V TAC Commercial Ambient Temperature TAI Industrial Ambient Temperature CLOAD Maximum Load Capacitance tPU Power up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Document #: 001-12565 Rev. *B 0 – +70 °C –40 -- +85 °C – – 15 pF 0.05 – 500 ms Page 5 of 10 [+] Feedback CY25402/CY25422/CY25482 DC Electrical Specifications Parameter VOL Description Output Low Voltage Conditions IOL = 2 mA, drive strength = [00] Min Typ Max Unit – – 0.4 V VDD – 0.4 – – V IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] Output High Voltage VOH IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VIL1 Input Low Voltage of PD#/OE, FS0, FS1 and SSON – – 0.2*VDD V VIL2 Input Low Voltage of EXCLKIN – – 0.18 V VIH1 Input High Voltage of PD#/OE, FS0, FS1 and SSON 0.8*VDD – – V VIH2 Input High Voltage of EXCLKIN for CY25402/CY25422 1.62 – 2.2 V VIH3 Input High Voltage of EXCLKIN for CY25482 0.8*VDD – – V IIL Input Low Current, PD#/OE/FS1 VIN = 0V – – 10 µA IIH Input High Current, PD#/OE/FS1 VIN = VDD – – 10 µA IILDN Input Low Current, SSON and FS0 pins VIN = 0V (Internal pull down resistor = 160k typ.) – – 10 µA IIHDN Input High Current, SSON and FS0 pins VIN = VDD (Internal pull down resistor = 160k typ.) 14 – 36 µA RDN Pull Down Resistor of CLK1, REFOUT/FS0 and CLK2/SSON pins Output clocks in off state by setting PD# = Low 100 160 250 kΩ IDD[1,2] Supply Current for CY25422 IDDS [1] CIN[1] PD# = High, No load – 12 – mA Supply Current for CY25402/CY25482 PD# = High, No load – 14 – mA Standby Current PD# = Low – 3 – µA Input Capacitance SSON, PD#/OE/FS1 and FS0 pins – – 7 pF Notes 1. Guaranteed by design but not 100% tested 2. Configuration dependent Document #: 001-12565 Rev. *B Page 6 of 10 [+] Feedback CY25402/CY25422/CY25482 AC Electrical Specifications Parameter Description Conditions Min Typ Max Unit FIN (crystal) Crystal Frequency, XIN 8 – 48 MHz FIN (clock) Input Clock Frequency (EXCLKIN) 8 – 166 MHz FCLK Output Clock Frequency 3 – 166 MHz DC Output Duty Cycle, All Clocks except Ref Out Duty Cycle is defined in Figure 5 on page 8; t1/t2, measured at 50% of VDD 45 50 55 % DC Ref Out Duty Cycle Ref In Min 45%, Max 55% 40 – 60 % [1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [00] – 6.8 – ns TRF2[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [01] – 3.4 – ns TRF3[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [10] – 2.0 – ns TRF4[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [11] – 1.0 – ns TCCJ[1,2] Cycle-to-cycle Jitter (peak) Configuration dependent. See Table 5 – 100 – ps TLOCK[1] PLL Lock Time Measured from 90% of the applied power supply level – 1 3 ms TRF1 Table 5. Configuration Example for C-C Jitter Ref. Frequency (MHz) CLK1 Output CLK2 Output Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) 14.3181 8.0 134 48 92 19.2 74.25 99 8 91 27 48 67 166 103 48 48 93 166 137 Recommended Crystal Specification for SMD Package Parameter Fmin Description Minimum Frequency Range 1 Range 2 Range 3 8 14 Unit 28 MHz Fmax Maximum Frequency 14 28 48 MHz R1 Motional Resistance (ESR) 135 50 30 Ω C0 Shunt Capacitance 4 4 2 pF CL Parallel Load Capacitance 18 14 12 pF DL(max) Maximum Crystal Drive Level 300 300 300 µW Recommended Crystal Specification for Thru-Hole Package Parameter Description Range 1 Range 2 Range 3 Unit Fmin Minimum Frequency 8 14 24 MHz Fmax Maximum Frequency 14 24 32 MHz R1 Motional Resistance (ESR) 90 50 30 Ω C0 Shunt Capacitance 7 7 7 pF CL Parallel Load Capacitance DL(max) Maximum Crystal Drive Level Document #: 001-12565 Rev. *B 18 12 12 pF 1000 1000 1000 µW Page 7 of 10 [+] Feedback CY25402/CY25422/CY25482 Test and Measurement Setup Figure 4. Test and Measurement Setup V DD 0.1 μF Outputs C LOAD DUT GND Voltage and Timing Definitions Figure 5. Duty Cycle Definition t1 t2 V DD 50% of VDD Clock Output 0V Figure 6. Rise Time = TRF, Fall Time = TRF T RF T RF V DD 80% of V DD Clock Output Document #: 001-12565 Rev. *B 20% of VDD 0V Page 8 of 10 [+] Feedback CY25402/CY25422/CY25482 Ordering Information Part Number[3] Type VDD(V) Production Flow Pb-free CY25402SXC-xxx 8-pin SOIC Supply Voltage: 2.5V, 3.0V or 3.3V Commercial, 0°C to 70°C CY25402SXC-xxxT 8-pin SOIC -Tape & Reel Supply Voltage: 2.5V, 3.0V or 3.3V Commercial, 0°C to 70°C CY25482SXC-xxx 8-pin SOIC Supply Voltage: 2.5V, 3.0V or 3.3V Commercial, 0°C to 70°C CY25482SXC-xxxT 8-pin SOIC -Tape & Reel Supply Voltage: 2.5V, 3.0V or 3.3V Commercial, 0°C to 70°C CY25422SXC-xxx 8-pin SOIC Supply Voltage: 1.8V Commercial, 0°C to 70°C CY25422SXC-xxxT 8-pin SOIC -Tape & Reel Supply Voltage: 1.8V Commercial, 0°C to 70°C CY25402SXI-xxx 8-pin SOIC Supply Voltage: 2.5V, 3.0V or 3.3V Industrial, -40°C to +85°C CY25402SXI-xxxT 8-pin SOIC -Tape & Reel Supply Voltage: 2.5V, 3.0V or 3.3V Industrial, -40°C to +85°C CY25482SXI-xxx 8-pin SOIC Supply Voltage: 2.5V, 3.0V or 3.3V Industrial, -40°C to +85°C CY25482SXI-xxxT 8-pin SOIC -Tape & Reel Supply Voltage: 2.5V, 3.0V or 3.3V Industrial, -40°C to +85°C CY25422SXI-xxx 8-pin SOIC Supply Voltage: 1.8V Industrial, -40°C to +85°C CY25422SXI-xxxT 8-pin SOIC -Tape & Reel Supply Voltage: 1.8V Industrial, -40°C to +85°C Package Drawing and Dimensions Figure 7. 8-lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.0075[0.190] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 51-85066-*C 0.0138[0.350] 0.0192[0.487] Note 3. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document #: 001-12565 Rev. *B Page 9 of 10 [+] Feedback CY25402/CY25422/CY25482 Document History Page Document Title: CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12565 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 690296 See ECN RGL New Data Sheet *A 815788 See ECN RGL Minor Change: To post on web *B 1428744 See ECN RGL/AESA Changed data sheet format to match generic part, CY2544/46 Added new device and specification for high ref. input voltage part, CY25482 Removed Preliminary from Title page Replaced CLK2 with REFOUT © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-12565 Rev. *B Revised November 13, 2007 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback