IDT ICS251PMLF

DATASHEET
ICS251
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
Description
Features
The ICS251 is a low cost, single-output, field programmable
clock synthesizer. The ICS251 can generate an output
frequency from 314 kHz to 200 MHz and may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
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Using ICS’ VersaClock™software to configure the PLL and
output, the ICS251 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include 4 selectable configuration registers.
The device employs Phase-Locked Loop (PLL) techniques
to run from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
8-pin SOIC package
Four addressable registers
Input crystal frequency of 5 to 27 MHz
Clock input frequency of 3 to 150 MHz
Output clock frequencies up to 200 MHz
Configurable Spread Spectrum Modulation
Operating voltage of 3.3 V
Replaces multiple crystals and oscillators
Controllable output drive levels
Advanced, low-power CMOS process
Available in RoHS compliant packaging
The device also has a power-down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS251 is also available in factory programmed custom
versions for high-volume applications.
Block Diagram
VDD
S1:0
2
OTP ROM
with PLL
Divider
Values
Crystal or
clock input
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
CLK
X1/ICLK
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
GND
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 1
PDTS (output and PLL)
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Pin Assignment
EPROM CLOCK SYNTHESIZER
Output Clock Selection Table
S1
S0
CLK (MHz)
Spread
Percentage
GND
0
0
6
S1
0
1
5
CLK
1
0
1
1
User
Configurable
User
Configurable
User
Configurable
User
Configurable
User
Configurable
User
Configurable
User
Configurable
User
Configurable
S0
1
8
PDTS
VDD
2
7
X1/ICLK
3
X2
4
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
S0
Input
2
VDD
Power
3
X1/ICLK
XI
4
X2
XO
5
CLK
Output
Pin Description
Select pin 0 for frequency selection on CLK. Internal pull-up resistor.
Connect to +3.3 V.
Connect this pin to a crystal or external clock input.
Connect this pin to a crystal, or float for clock input.
Clock output. Weak internal pull-down when tri-state.
6
S1
Input
Select pin 1 for frequency selection on CLK. Internal pull-up resistor.
7
GND
Power
8
PDTS
Input
Connect this to Ground.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up
resistor.
External Components
The ICS251 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS251
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Crystal Load Capacitors
The device crystal connections should include pads for
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2
1) The 0.01µF decoupling capacitor should be mounted on
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the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS251. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
ICS251 Configuration Capabilities
The architecture of the ICS251 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS251 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented
as:
OutputFreq
=
REFFreq
-------------------------------------OutputDivide
----⋅M
N
Output Drive Control
The ICS251 has two output drive settings. Low drive should
be selected when outputs are less than 100 MHz. High drive
should be selected when outputs are greater than 100 MHz.
(Consult the AC Electrical Characteristics for output rise and
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 3
EPROM CLOCK SYNTHESIZER
fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS251 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electro-magnetic interference (EMI).
The modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS251 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between +/- 0.125% to +/-2.0%. For down
spread, the frequency can be modulated between -0.25% to
-4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
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Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
EPROM CLOCK SYNTHESIZER
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS251. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
Supply Voltage, VDD
Referenced to GND
Inputs
Clock Outputs
Max.
Units
-0.5
7
V
Referenced to GND
-0.5
VDD+ 0.5
V
Referenced to GND
-0.5
VDD+ 0.5
V
-65
150
°C
260
°C
125
°C
Storage Temperature
Soldering Temperature
Typ.
Max 10 seconds
Junction Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS251M)
0
+70
°C
Ambient Operating Temperature (ICS251MI)
-40
+85
°C
+3.45
V
4
ms
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 4
+3.15
+3.3
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EPROM CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
Conditions
VDD
Min.
Typ.
Max.
Units
3.15
3.3
3.45
V
Configuration Dependent
- See VersaClockTM
mA
33.3333 MHz output,
PDTS = 1, no load
Note 1
14
mA
500
µA
V
Operating Supply Current
Input High Voltage
IDD
Input High Voltage
VIH
PDTS = 0
S1:S0
Input Low Voltage
VIL
S1:S0
Input High Voltage, PDTS
VIH
Input Low Voltage, PDTS
VIL
Input High Voltage
VIH
ICLK
Input Low Voltage
VIL
ICLK
Output High Voltage
(CMOS High)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -8 mA (Low Drive);
IOH = -12 mA (High Drive)
2.4
VDD-0.4
V
Output Low Voltage
VOL
IOL = 8 mA (Low Drive);
IOL = 12 mA (High Drive)
Short Circuit Current
IOS
±70
mA
Nominal Output
Impedance
ZO
20
Ω
VDD/2+1
0.4
VDD-0.5
V
V
0.4
VDD/2+1
V
V
VDD/2-1
0.4
V
V
Internal pull-up resistor
RPUP
S1:S0, PDTS
190
kΩ
Internal pull-down resistor
RPD
CLK output
120
kΩ
Input Capacitance
CIN
inputs
4
pF
Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V.
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 5
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EPROM CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Symbol
FIN
Conditions
Min.
Typ.
Max. Units
Fundamental Crystal
5
27
MHz
Input Clock
3
150
MHz
0.314
200
MHz
Output Frequency
Output Rise Time
tOR
20% to 80%, Note 1
1
ns
Output Fall Time
tOF
80% to 20%, Note 1
1
ns
Duty Cycle
Note 2
Power-up time
One Sigma Clock Period Jitter
Maximum Absolute Jitter
tja
40
49-51
60
%
PLL lock time from
power-up
4
10
ms
PDTS goes high until
stable CLK output,
Spread Spectrum Off
.6
2
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
4
7
ms
Configuration Dependent
50
ps
Deviation from Mean.
Configuration Dependent
+200
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Thermal Resistance Junction to
Ambient
θJA
Still air
150
°C/W
θJA
1 m/s air flow
140
°C/W
θJA
3 m/s air flow
120
°C/W
Thermal Resistance Junction to Case
θJC
40
°C/W
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6
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Marking Diagram
EPROM CLOCK SYNTHESIZER
Marking Diagram (Pb free)
8
5
8
251PML
######
YYWW
251PM
######
YYWW
1
4
8
5
1
4
4
8
5
251PMIL
######
YYWW
251PMI
######
YYWW
1
5
1
4
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temp. range (if applicable).
4. “L” denotes RoHS compliant package.
5. Bottom marking: country of origin.
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 7
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EPROM CLOCK SYNTHESIZER
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
C
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 8
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EPROM CLOCK SYNTHESIZER
Ordering Information
Part / Order Number
ICS251PM
ICS251PMI
ICS251PMLF
ICS251PMILF
ICS251M-XX
ICS251MI-XX
ICS251M-XXLF
ICS251MI-XXLF
ICS251M-XXT
ICS251MI-XXT
ICS251M-XXLFT
ICS251MI-XXLFT
Marking
See Page 7 Above
251M-XX
251MIXX
251MXXL
251MIXXL
251M-XX
251MIXX
251MXXL
251MIXXL
Shipping Packaging
Package
Temperature
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS251M-XX, ICS251M-XXLF, ICS251MI-XX, and ICS251MI-XXLF are factory programmed versions of the ICS251PM,
ICS251PMLF, ICS251PMI, and ICS251PMILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and
a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact
your local IDT sales and marketing representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
VersaClockTM is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
IDT™ / ICS™ FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 9
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EPROM CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
<product line email>
<product line phone>
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Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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