TI XF28M35H52C1RFPT

F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Concerto Microcontrollers
1 F28M35x ( Concerto™) MCUs
1.1
Features
• Host Subsystem — ARM® Cortex™-M3
– 100 MHz
– Embedded Memory
• Up to 512KB Flash (ECC)
• Up to 32KB RAM (ECC/Parity)
• Up to 64KB Shared RAM
• 2KB IPC Message RAM
– 5 Universal Asynchronous
Receiver/Transmitters (UARTs)
– 4 Synchronous Serial Interfaces (SSIs)/
Serial Peripheral Interface (SPI)
– 2 Inter-integrated Circuits (I2Cs)
– Universal Serial Bus On-the-Go (USB-OTB) +
PHY
– 10/100 ENET 1588 MII
– 2 Controller Area Networks (CANs)
– 32-Channel Direct Memory Access (μDMA)
– Dual Security Zones (128-Bit Password per
Zone)
– External Peripheral Interface (EPI)
– Micro Cyclic Redundancy Check (µCRC)
Module
– 4 General-Purpose Timers
– 2 Watchdog Timer Modules
• Clocking
– On-chip Crystal Oscillator/External Clock
Input
– Dynamic PLL Ratio Changes Supported
• 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design
• Interprocessor Communications (IPC)
– 32 Handshaking Channels
– 4 Channels Generate IPC Interrupts
– Can be Used to Coordinate Transfer of Data
Through IPC Message RAMs
• Control Subsystem — TMS320C28x™ 32-Bit
CPU
– 150 MHz
– Embedded Memory
• Up to 512KB Flash (ECC)
• Up to 36KB RAM (ECC/Parity)
• 2KB IPC Message RAM
– IEEE-754 Single-Precision Floating-Point
Unit (FPU)
– Viterbi, Complex Math, CRC Unit (VCU)
– Serial Communications Interface (SCI)
– Serial Peripheral Interface (SPI)
– Inter-integrated Circuit (I2C)
– 6-Channel Direct Memory Access (DMA)
– 9 Enhanced Pulse Width Modulator (ePWM)
Modules
• 18 Outputs (16 High-Resolution)
– 6 32-Bit Enhanced Capture (eCAP) Modules
– 3 32-Bit Enhanced Quadrature Encoder
(eQEP) Modules
– Multi-Channel Buffered Serial Port (McBSP)
– One Security Zone (128-Bit Password)
– 3 32-Bit Timers
• Analog Subsystem
– Dual 12-Bit Analog-to-Digital Converters
(ADCs)
– Up to 2.88 MSPS
– Up to 20 Channels
– 4 Sample-and-Hold (S/H) Circuits
– Up to 6 Comparators With 10-Bit
Digital-to-Analog Converter (DAC)
– On-chip Temperature Sensor
• Up to 74 Individually Programmable,
Multiplexed GPIO Pins
• Package
– 144-Pin RFP PowerPAD™ Thermally
Enhanced Thin Quad Flatpack (HTQFP)
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Concerto, TMS320C28x, PowerPAD, C28x, C2000, Piccolo, Delfino are trademarks of Texas Instruments.
Cortex is a trademark of ARM Limited.
ARM is a registered trademark of ARM Ltd or its subsidiaries.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2011, Texas Instruments Incorporated
PRODUCT PREVIEW
12345
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
1.2
www.ti.com
Description
The Concerto™ family is a multi-core system-on-chip microcontroller with independent communication and
real-time control subsystems. The F28M35x is the first series in the Concerto family.
The communications subsystem is based on the industry-standard 32-bit ARM® Cortex™-M3 CPU and
features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, CAN,
UART, SSI, I2C, and an external interface.
The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x™ Floating-Point
CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault
protection, and encoders and captures—all as implemented by TI’s C2000™ Piccolo™ and Delfino™
families. In addition, the C28-CPU has been enhanced with the addition of the Viterbi, Complex Math,
CRC Unit (VCU) instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs
and CRC algorithms.
A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage
regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code
(ECC), Parity, and Code Secure Memory, as well as documentation to assist with system-level industrial
safety certification.
PRODUCT PREVIEW
2
F28M35x ( Concerto™) MCUs
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Functional Block Diagram
1.8V
VREG
GPIO_MUX1
SECURE
C3
C1
RAM
8 KB
(ECC)
RAM
8 KB
(parity)
1.2V
VREG
SECURE
WDOG (2)
uCRC
NMI WDOG
GP TIMER (4)
SSI (4)
DCAN (2)
UART (5)
2
I C (2)
EPI
USB+PHY
(OTG)
EMAC (MMI)
FLASH
BOOT
ROM
AIO_MUX
6
COMP
INPUTS
MPU
M3
BUS
BRIDGE
uDMA
M3 CPU
NVIC
I-CODE BUS
D-CODE BUS
M3 SYSTEM BUS
ANALOG COMMON INTERFACE BUS
10 PINS
TEMP
SENS
ADC_1
MODULE
COMPOUT
OUTPUTS
6
GPIO_MUX2
RAM
8 KB
(parity)
uDMA BUS
10
ADC
INPUTS
8 PINS
C2
C0
RAM
8 KB
(ECC)
CPU
ONLY
HERE
APB BUS
COMPARE
+ DAC
10
ADC
INPUTS
AIO_MUX
SECURE
64 KB
AHB BUS
10 PINS
512 KB
(ECC)
PRODUCT PREVIEW
1.3
INTER-PROCESSOR
COMMUNICATION
CLOCKS
RESETS
S0
S1
S2
S3
S4
S5
8 KB
8 KB
8 KB
8 KB
8 KB
8 KB
S6
S7
IPC
NMI
8 KB
8 KB
MTOC
MSG
RAM
(parity)
2 KB
CTOM
MSG
RAM
(parity)
2 KB
S0-S7 SHARED RAM (parity)
JTAG
INTER-PROCESSOR
COMMUNICATION
C28 DMA BUS
ADC_2
MODULE
6
COMP
INPUTS
C28
CPU
C28
VCU
C28
DMA
C28
FPU
PIE
C28 MEMORY BUS
ANALOG SUBSYSTEM
TIMER (3)
16/32-BIT
PF0
McBSP
ECAP (6)
EQEP (3)
EPWM (9)
32-BIT
PF3
32-BIT
PF1
SPI
SCI
I2C
XINT (3)
NMI WDOG
16-BIT
PF2
BOOT
ROM
64 KB
SECURE
FLASH
512 KB
(ECC)
GPIO_MUX1
66 PINS (TOTAL)
SECURE
L3
M1
L1
RAM
8 KB
(ECC)
RAM
8 KB
(parity)
RAM
2 KB
SECURE
L2
M0
L0
RAM
8 KB
(ECC)
RAM
8 KB
(parity)
RAM
2 KB
(ECC)
(ECC)
Figure 1-1. Functional Block Diagram
F28M35x ( Concerto™) MCUs
Copyright © 2011, Texas Instruments Incorporated
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3
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
1
2
www.ti.com
........................
1.1
Features ..............................................
1.2
Description ...........................................
1.3
Functional Block Diagram ............................
Device Overview ........................................
2.1
Device Characteristics ...............................
F28M35x ( Concerto™) MCUs
1
...............................................
Pin Assignments .....................................
Terminal Functions ...................................
Device Pins
8
1
3.1
8
2
3.2
3
5
5
3
4
9
Mechanical Packaging and Orderable
Information .............................................. 27
4.1
Packaging Information
..............................
27
PRODUCT PREVIEW
4
Contents
Copyright © 2011, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
2 Device Overview
2.1
Device Characteristics
PRODUCT PREVIEW
Table 2-1 lists the features of the F28M35Hx devices.
Device Overview
Copyright © 2011, Texas Instruments Incorporated
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5
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 2-1. Hardware Features
FEATURE
TYPE (1)
H20B1
H20C1
H22B1
H22C1
H32B1
H32C1
H50B1
H50C1
H52B1
H52C1
Host Subsystem — ARM® Cortex™-M3
PRODUCT PREVIEW
Speed (MHz)
–
100 (2)
100 (2)
100 (2)
100 (2)
100 (2)
100 (2)
100 (2)
100 (2)
100 (2)
100 (2)
Flash (KB)
–
256
256
256
256
256
512
512
512
512
512
RAM ECC (KB)
–
16
16
16
16
16
16
16
16
16
16
RAM Parity (KB)
–
16
16
16
16
16
16
16
16
16
16
IPC Message RAM Parity (KB)
–
2
2
2
2
2
2
2
2
2
2
Security Zones
–
2
2
2
2
2
2
2
2
2
2
10/100 ENET 1588 MII
0
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
USB OTG FS
0
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Synchronous Serial Interface (SSI)/
Serial Peripheral Interface (SPI)
0
4
4
4
4
4
4
4
4
4
4
Universal Asynchronous Receiver/Transmitter (UART)
0
5
5
5
5
5
5
5
5
5
5
Inter-integrated circuit (I2C)
0
2
2
2
2
2
2
2
2
2
2
Controller Area Network (CAN)
0
2
2
2
2
2
2
2
2
2
2
Direct Memory Access (µDMA)
0
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
External Peripheral Interface (EPI)
0
1
1
1
1
1
1
1
1
1
1
Micro Cyclic Redundancy Check (µCRC) Module
0
1
1
1
1
1
1
1
1
1
1
General-Purpose Timers
–
4
4
4
4
4
4
4
4
4
4
Watchdog Timer Modules
–
2
2
2
2
2
2
2
2
2
2
Control Subsystem — C28x Floating-Point Unit (FPU)/Viterbi, Complex Math, CRC Unit (VCU)
Speed (MHz)
150
150
150
150
150
150
150
150
150
150
Flash (KB)
256
256
256
256
512
256
512
512
512
512
RAM ECC (KB)
20
20
20
20
20
20
20
20
20
20
RAM Parity (KB)
16
16
16
16
16
16
16
16
16
16
IPC Message RAM Parity (KB)
2
2
2
2
2
2
2
2
2
2
Security Zones
1
1
1
1
1
1
1
1
1
1
Enhanced Pulse Width Modulator (ePWM) modules
2
9: 18 outputs
High-Resolution PWM outputs
2
16 outputs
Enhanced Capture (eCAP) modules/
PWM outputs
0
6 (32-bit)
Enhanced Quadrature Encoder (eQEP) modules
0
3 (32-bit)
Fault Trip Zones
–
12 on any of 64 GPIO pins
Multi-Channel Buffered Serial Port (McBSP)/
Serial Peripheral Interface (SPI)
1
1
1
1
1
1
1
1
1
1
1
Serial Communications Interface (SCI)
0
1
1
1
1
1
1
1
1
1
1
Serial Peripheral Interface (SPI)
0
1
1
1
1
1
1
1
1
1
1
(1)
(2)
6
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.
An integer divide ratio must be maintained between the C28x and M3 clock frequencies; thus, when the C28x is configured to run at maximum frequency of 150 MHz, the fastest allowable
frequency for the M3 will be 75 MHz.
Device Overview
Copyright © 2011, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 2-1. Hardware Features (continued)
TYPE (1)
H20B1
H20C1
H22B1
H22C1
H32B1
H32C1
H50B1
H50C1
H52B1
Inter-integrated circuit (I2C)
0
1
1
1
1
1
1
1
1
1
1
Direct Memory Access (DMA)
0
6-ch
6-ch
6-ch
6-ch
6-ch
6-ch
6-ch
6-ch
6-ch
6-ch
32-Bit Timers
–
3
3
3
3
3
3
3
3
3
3
FEATURE
H52C1
Supplemental RAM (KB)
0
0
64
64
64
64
0
0
64
64
2.88
2.88
2.88
2.88
2.88
2.88
2.88
2.88
2.88
2.88
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
10
10
10
10
10
10
10
10
10
10
Temperature Sensor
1
1
1
1
1
1
1
1
1
1
Sample-and-Hold (S/H)
2
2
2
2
2
2
2
2
2
2
2.88
2.88
2.88
2.88
2.88
2.88
2.88
2.88
2.88
2.88
MSPS
Conversion Time
12-Bit ADC 1
Channels
3
MSPS
Conversion Time
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
350 ns
Channels
10
10
10
10
10
10
10
10
10
10
Sample-and-Hold (S/H)
2
2
2
2
2
2
2
2
2
2
6
6
6
6
6
6
6
6
6
6
Yes
Yes
Yes
Yes
TMX
TMX
TMX
TMX
12-Bit ADC 2
PRODUCT PREVIEW
Shared
3
Comparators with Integrated DACs
0
Voltage Regulator and Monitor
3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC)
Clocking
4–20 MHz input, Clock fail or out-of-specification, 10-MHz/32-kHz Limp Mode
Additional Safety
Host Subsystem
2 Watchdogs, NMI Watchdog: CPU, Memory
Control Subsystem
NMI Watchdog: CPU, Memory
Shared
Critical Register and I/O Function Lock Protection; RAM Fetch Protection
Packaging
Package Type
Temperature options
144-Pin RFP PowerPAD™
HTQFP
T: –40°C to 105°C
–
S: –40°C to 125°C
–
Q: –40°C to 125°C (1)
–
Product status (2)
(1)
(2)
Available at Prototype Sampling
–
Yes
Yes
Yes
Yes
Yes
Yes
No 125ºC for ENET/USB
No 125ºC for ENET/USB
TMX
TMX
TMX
TMX
TMX
TMX
"Q" refers to Q100 qualification for automotive applications.
The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications.
Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
3 Device Pins
3.1
Pin Assignments
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD18
VDDIO
VDDIO
VDDIO
PF0_GPIO32
PF1_GPIO33
PD0_GPIO16
VREG12EN
VDDIO
VDD12
PD1_GPIO17
PJ7_GPIO63
VDDIO
X2
VSSOSC
X1
VDDIO
VDD12
VDD12
TCK
TDI
TMS
EMU1
TRST
TDO
EMU0
PF2_GPIO34
PF3_GPIO35
PH7_GPIO55
PH6_GPIO54
PG3_GPIO43
PE4_GPIO28
PE5_GPIO29
VDD12
VDDIO
PD6_GPIO22
Figure 3-1 shows the 144-pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) pin
assignments.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
PG5_GPIO45
PG2_GPIO42
PG6_GPIO46
PF6_GPIO38
PD7_GPIO23
VDDIO
VDD12
PD4_GPIO20
PD5_GPIO21
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
VDDIO
VDD12
PJ4_GPIO60
PJ5_GPIO61
VDD12
VDDIO
PJ6_GPIO62
PG7_GPIO47
PF5_GPIO37
PG1_GPIO41
PG0_GPIO40
PF4_GPIO36
PH5_GPIO53
PH4_GPIO52
PE1_GPIO25
VDDIO
PE0_GPIO24
PH1_GPIO49
PH0_GPIO48
PC7_GPIO71
PC6_GPIO70
PC5_GPIO69
PC4_GPIO68
VDD18
VDDIO
VDDIO
XRS
PA0_GPIO0
PA1_GPIO1
PA2_GPIO2
PA3_GPIO3
PA4_GPIO4
VDDIO
VDD12
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7
PB0_GPIO8
FLT1
VDDIO
PB1_GPIO9
PB2_GPIO10
PB3_GPIO11
FLT2
PE6_GPIO30
PE7_GPIO31
VDD12
VDDIO
PB6_GPIO14
PB7_GPIO15
PD2_GPIO18
PD3_GPIO19
PB4_GPIO12
PB5_GPIO13
PE2_GPIO26
PE3_GPIO27
VDDIO
PH3_GPIO51
PH2_GPIO50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PRODUCT PREVIEW
GPIO135/COMP5OUT
GPIO134
GPIO133/COMP4OUT
GPIO132/COMP3OUT
VREG18EN
ADC1INB7
ADC1INB4
ADC1INB3
ADC1INB0
ADC1VREFLO, VSSA1
VDDA1
ADC1VREFHI
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC2INA7
ADC2INA6
ADC2INA4
ADC2INA3
ADC2INA2
ADC2INA0
ADC2VREFHI
VDDA2
ADC2VREFLO
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
GPIO128
GPIO129/COMP1OUT
GPIO130/COMP6OUT
GPIO131/COMP2OUT
ARS
A.
See Table 3-1, Terminal Functions, for the complete multiplexed signal names.
Figure 3-1. 144-Pin RFP PowerPAD™ HTQFP (Top View)
8
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
3.2
Terminal Functions
Table 3-1 describes the signals.
Table 3-1. Terminal Functions (1)
TERMINAL
NAME
RFP
PIN #
I/O/Z
DESCRIPTION
ADC, Comparator + DAC, Analog I/O
ADC1VREFHI
120
I
ADC1 External High Reference – only used when in ADC external reference
mode.
ADC1VREFLO,
VSSA1
118
I
ADC1 External Low Reference – only used when in ADC external reference
mode.
ADC1INA0
121
I
ADC1 Group A, Channel 0 input
ADC1INA2
122
I
ADC1 Group A, Channel 2 input
I
Comparator Input A1
AIO2
I/O
Digital AIO2
ADC1INA3
123
I
ADC1 Group A, Channel 3 input
ADC1INA4
124
I
ADC1 Group A, Channel 4 input
I
Comparator Input A2
COMPA2
AIO4
ADC1INA6
I/O
125
COMPA3
AIO6
Digital AIO4
I
ADC1 Group A, Channel 6 input
I
Comparator Input A3
I/O
Digital AIO6
ADC1INA7
126
I
ADC1 Group A, Channel 7 input
ADC1INB0
117
I
ADC1 Group B, Channel 0 input
ADC1INB3
116
I
ADC1 Group B, Channel 3 input
ADC1INB4
115
I
ADC1 Group B, Channel 4 input
I
Comparator Input B2
COMPB2
AIO12
I/O
Digital AIO12
ADC1INB7
114
I
ADC1 Group B, Channel 7 input
ADC2VREFHI
133
I
ADC2 External High Reference – only used when in ADC external reference
mode.
ADC2VREFLO
135
I
ADC2 External Low Reference – only used when in ADC external reference
mode.
ADC2INA0
132
I
ADC2 Group A, Channel 0 input
ADC2INA2
131
I
ADC2 Group A, Channel 2 input
I
Comparator Input A4
COMPA4
AIO18
I/O
Digital AIO18
ADC2INA3
130
I
ADC2 Group A, Channel 3 input
ADC2INA6
128
I
ADC2 Group A, Channel 6 input
I
Comparator Input A6
COMPA6
AIO22
ADC2INA4
I/O
129
COMPA5
AIO20
(1)
Digital AIO22
I
ADC2 Group A, Channel 4 input
I
Comparator Input A5
I/O
PRODUCT PREVIEW
COMPA1
Digital AIO20
I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
RFP
PIN #
I/O/Z
ADC2INA7
127
I
ADC2 Group A, Channel 7 input
ADC2INB0
136
I
ADC2 Group B, Channel 0 input
ADC2INB3
137
I
ADC2 Group B, Channel 3 input
ADC2INB4
138
I
ADC2 Group B, Channel 4 input
I
Comparator Input B5
NAME
COMPB5
AIO28
I/O
ADC2INB7
139
DESCRIPTION
Digital AIO28
I
ADC2 Group B, Channel 7 input
Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only)
GPIO128
140
I/O
General-purpose input/output 128
GPIO129
141
I/O
General-purpose input/output 129
O
Compare result from Analog Comparator 1
142
I/O
General-purpose input/output 130
O
Compare result from Analog Comparator 6
143
I/O
General-purpose input/output 131
O
Compare result from Analog Comparator 2
I/O
General-purpose input/output 132
O
Compare result from Analog Comparator 3
I/O
General-purpose input/output 133
O
Compare result from Analog Comparator 4
COMP1OUT
GPIO130
COMP6OUT
GPIO131
PRODUCT PREVIEW
COMP2OUT
GPIO132
112
COMP3OUT
GPIO133
111
COMP4OUT
GPIO134
110
I/O
General-purpose input/output 134
GPIO135
109
I/O
General-purpose input/output 135
O
Compare result from Analog Comparator 5
COMP5OUT
GPIO Group 1 and Peripheral Signals
PA0_GPIO0
5
M3_U0RX
I/O/Z
I
M3_I2C1SCL
General-purpose input/output 0
UART-0 receive data
I/OD
I2C-1 clock open-drain bidirectional port
M3_U1RX
I
UART-1 receive data
C28_EPWM1A
O
Enhanced PWM-1 output A
PA1_GPIO1
6
M3_U0TX
I/O/Z
O
M3_I2C1SDA
General-purpose input/output 1
UART-0 transmit data
I/OD
I2C-1 data open-drain bidirectional port
M3_U1TX
O
UART-1 data transmit
M3_SSI1FSS
I/O
SSI-1 frame
C28_EPWM1B
O
Enhanced PWM-1 output B
C28_ECAP6
I/O
Enhanced Capture-6 input/output
PA2_GPIO2
7
I/O/Z
General-purpose input/output 2
M3_SSI0CLK
I/O
SSI-0 clock
M3_MIITXD2
O
EMAC MII transmit data bit 2
M3_U1CTS
I
UART-1 clear-to-send modem status
C28_EPWM2A
O
Enhanced PWM-2 output A
10
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PA3_GPIO3
RFP
PIN #
I/O/Z
8
I/O/Z
DESCRIPTION
General-purpose input/output 3
M3_SSI0FSS
I/O
SSI-0 frame
M3_MIITXD1
O
EMAC MII transmit data bit 1
M3_U1DCD
I
UART-1 data carrier detect
M3_SSI1CLK
I/O
SSI-1 clock
C28_EPWM2B
O
Enhanced PWM-2 output B
C28_ECAP5
I/O
Enhanced Capture-5 input/output
PA4_GPIO4
9
I/O/Z
General-purpose input/output 4
M3_SSI0RX
I/O
SSI-0 clock
M3_MIITXD0
O
EMAC MII transmit data bit 0
M3_CAN0RX
I
CAN-0 receive data
M3_U1DSR
I
UART-1 data set ready
O
Enhanced PWM-3 output A
C28_EPWM3A
PA5_GPIO5
12
M3_SSI0TX
I/O/Z
General-purpose input/output 5
O
SSI-0 transmit data
M3_MIIRXDV
I
EMAC MII receive data valid
M3_CAN0TX
O
CAN-0 transmit data
M3_U1RTS
O
UART-1 request-to-send
C28_EPWM3B
O
Enhanced PWM-3 output B
C28_MFSRA
I
McBSP-A receive frame sync
C28_ECAP1
I/O
PA6_GPIO6
13
M3_I2C1SCL
M3_CCP1
Enhanced Capture-1 input/output
I/O/Z
General-purpose input/output 6
I/OD
I2C-1 clock open-drain bidirectional port
I/O
M3_MIIRXCK
Capture/Compare/PWM-1 (General-purpose Timer)
I
EMAC MII receive clock
M3_CAN0RX
I
CAN-0 receive data
M3_USB0EPEN
O
USB-0 external power enable (optionally used in the host mode)
M3_U1CTS
I
UART-1 clear-to-send modem status
M3_U1DTR
O
UART-1 data terminal ready
C28_EPWM4A
O
Enhanced PWM-4 output A
C28_EPWMSYNCO
O
Enhanced PWM-4 external sync pulse
PA7_GPIO7
14
M3_I2C1SDA
M3_CCP4
M3_MIIRXER
I/O/Z
General-purpose input/output 7
I/OD
I2C-1 data open-drain bidirectional port
I/O
Capture/Compare/PWM-4 (General-purpose Timer)
I
EMAC MII receive error
M3_CAN0TX
O
CAN-0 transmit data
M3_CCP3
I/O
Capture/Compare/PWM-3 (General-purpose Timer)
M3_USB0PFLT
I
USB-0 external power error state (optionally used in the host mode)
M3_U1DCD
I
UART-1 data carrier detect
M3_MII_RXD1
I
EMAC MII receive data 1
M3_U1RI
I
UART-1 ring indicator status
C28_EPWM4B
O
Enhanced PWM-4 output B
I
McBSP-A receive clock
C28_MCLKRA
C28_ECAP2
I/O
PRODUCT PREVIEW
NAME
Enhanced Capture-1 input/output
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
PB0_GPIO8
RFP
PIN #
I/O/Z
15
I/O/Z
M3_CCP0
I/O
DESCRIPTION
General-purpose input/output 8
Capture/Compare/PWM-0 (General-purpose Timer)
M3_U1RX
I
UART-1 data receive data
M3_SSI2TX
O
SSI-2 transmit data
M3_CAN1TX
O
CAN-1 transmit data
M3_U4TX
O
UART-4 transmit data
C28_EPWM5A
O
Enhanced PWM-5 output A
C28_ADCSOCAO
O
ADC start-of-conversion A
PB1_GPIO9
18
I/O/Z
General-purpose input/output 9
PRODUCT PREVIEW
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_CCP1
I/O
Capture/Compare/PWM-1 (General-purpose Timer)
M3_U1TX
O
UART-1 transmit data
M3_SSI2RX
I
SSI-2 receive data
C28_EPWM5B
O
Enhanced PWM-5 output B
C28_ECAP3
I/O
Enhanced Capture-3 input/output
I/O/Z
General-purpose input/output 10
I/OD
I2C-0 clock open-drain bidirectional port
PB2_GPIO10
19
M3_I2C0SCL
M3_CCP3
I/O
Capture/Compare/PWM-3 (General-purpose Timer)
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_USB0EPEN
O
USB-0 external power enable (optionally used in the host mode)
M3_SSI2CLK
I/O
SSI-2 clock
M3_CAN1RX
I
CAN-1 receive data
M3_U4RX
I
UART-4 receive data
C28_EPWM6A
O
Enhanced PWM-6 output A
C28_ADCSOCBO
O
ADC start-of-conversion B
PB3_GPIO11
20
M3_I2C0SDA
M3_USB0PFLT
I/O/Z
General-purpose input/output 11
I/OD
I2C-0 data open-drain bidirectional port
I
M3_SSI2FSS
USB-0 external power error state (optionally used in the host mode)
I/O
SSI-2 frame
M3_U1RX
I
UART-1 receive data
C28_EPWM6B
O
Enhanced PWM-6 output B
C28_ECAP4
I/O
Enhanced Capture-4 input/output
I/O/Z
General-purpose input/output 12
PB4_GPIO12
30
M3_U2RX
I
UART-2 receive data
M3_CAN0RX
I
CAN-0 receive data
I
UART-1 receive data
M3_U1RX
M3_EPIOS23
I/O
EPI-0 signal 23
M3_CAN1TX
O
CAN-1 transmit data
M3_SSI1TX
O
SSI-1 transmit data
C28_EPWM7A
O
Enhanced PWM-7 output A
12
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PB5_GPIO13
RFP
PIN #
I/O/Z
31
I/O/Z
DESCRIPTION
General-purpose input/output 13
M3_CCP5
I/O
Capture/Compare/PWM-5 (General-purpose Timer)
M3_CCP6
I/O
Capture/Compare/PWM-6 (General-purpose Timer)
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_CAN0TX
O
CAN-0 transmit data
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_U1TX
O
UART-1 transmit data
M3_EPI0S22
I/O
EPI-0 signal 22
M3_CAN1RX
I
CAN-1 receive data
M3_SSI1RX
I
SSI-1 receive data
C28_EPWM7B
O
Enhanced PWM-7 output B
PB6_GPIO14
26
I/O/Z
General-purpose input/output 14
M3_CCP1
I/O
Capture/Compare/PWM-1 (General-purpose Timer)
M3_CCP7
I/O
Capture/Compare/PWM-7 (General-purpose Timer)
M3_CCP5
I/O
Capture/Compare/PWM-5 (General-purpose Timer)
M3_MIICRS
I
M3_I2C0SDA
EMAC MII carrier sense
I/OD
I2C-0 data open-drain bidirectional port
M3_U1TX
O
UART-1 transmit data
M3_SSI1CLK
I/O
EMAC MII carrier sense
O
Enhanced PWM-8 output A
C28_EPWM8A
PB7_GPIO15
27
M3_EXTNMI
I/O/Z
General-purpose input/output 15
I
M3 external non-maskable interrupt
M3_MIIRXD1
I
EMAC MII receive data 1
M3_I2C0SCL
I/OD
M3_U1RX
I
I2C-0 clock open-drain bidirectional port
UART-1 receive data
M3_SSI1FSS
I/O
SSI-1 frame
C28_EPWM8B
O
Enhanced PWM-8 output B
PD0_GPIO16
102
PRODUCT PREVIEW
NAME
I/O/Z
General-purpose input/output 16
M3_CAN0RX
I
CAN-0 receive data
M3_U2RX
I
UART-2 receive data
M3_U1RX
I
UART-1 receive data
M3_CCP6
I/O
Capture/Compare/PWM-6 (General-purpose Timer)
M3_MIIRXDV
I
EMAC MII receive data valid
M3_U1CTS
I
UART-1 clear-to-send modem status
M3_MIIRXD2
I
EMAC MII receive data 2
M3_SSI0TX
O
SSI-0 transmit data
M3_CAN1TX
O
CAN-1 transmit data
M3_USB0EPEN
O
USB-0 external power enable (optionally used in the host mode)
C28_SPISIMOA
I/O
SPI-A slave in, master out
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
PD1_GPIO17
RFP
PIN #
I/O/Z
98
I/O/Z
DESCRIPTION
General-purpose input/output 17
M3_CAN0TX
O
CAN-0 transmit data
M3_U2TX
O
UART-2 transmit data
M3_U1TX
O
UART-1 transmit data
M3_CCP7
I/O
Capture/Compare/PWM-7 (General-purpose Timer)
M3_MIITXER
O
EMAC MII transmit error
M3_U1DCD
I
UART-1 data carrier detect
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_MIICOL
I
EMAC MII collision detect
M3_SSI0RX
I
SSI-0 receive data
M3_CAN1RX
I
CAN-1 receive data
M3_USB0PFLT
I
USB-0 external power error state (optionally used in the host mode)
C28_SPISOMIA
PD2_GPIO18
I/O
28
SPI-A master in, slave out
I/O/Z
General-purpose input/output 18
PRODUCT PREVIEW
M3_U1RX
I
M3_CCP6
I/O
Capture/Compare/PWM-6 (General-purpose Timer)
M3_CCP5
I/O
Capture/Compare/PWM-5 (General-purpose Timer)
M3_EPI0S20
I/O
EPI-0 signal 20
M3_SSI0CLK
I/O
SSI-0 clock
M3_U1TX
O
UART-1 transmit data
M3_CAN0RX
I
CAN-0 receive data
C28_SPICLKA
PD3_GPIO19
UART-1 receive data
I/O
29
SPI-A clock
I/O/Z
General-purpose input/output 19
M3_U1TX
O
UART-1 transmit data
M3_CCP7
I/O
Capture/Compare/PWM-7 (General-purpose Timer)
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_EPI0S21
I/O
EPI-0 signal 21
M3_SSI0FSS
I/O
SSI-0 frame
M3_U1RX
I
UART-1 receive data
M3_CAN0TX
O
CAN-0 transmit data
C28_SPISTEA
I/O
SPI-A slave transmit enable
PD4_GPIO20
65
I/O/Z
General-purpose input/output 20
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_CCP3
I/O
Capture/Compare/PWM-3 (General-purpose Timer)
M3_MIITXD3
O
EMAC MII transmit data 3
I
UART-1 receive data
M3_U1RI
M3_EPI0S19
I/O
EPI-0 signal 19
M3_U3TX
O
UART-3 transmit data
M3_CAN1TX
O
CAN-1 transmit data
C28_EQEP1A
I
Enhanced QEP-1 input A
C28_MDXA
O
McBSP-A transmit data
14
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PD5_GPIO21
RFP
PIN #
I/O/Z
64
I/O/Z
DESCRIPTION
General-purpose input/output 21
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_CCP4
I/O
Capture/Compare/PWM-4 (General-purpose Timer)
M3_MIITXD2
O
EMAC MII transmit data 2
M3_U2RX
I
UART-2 receive data
M3_EPI0S28
I/O
EPI-0 signal 28
M3_U3RX
I
UART-3 receive data
M3_CAN1RX
I
CAN-1 receive data
C28_EQEP1B
I
Enhanced QEP-1 input B
I
McBSP-A receive data
C28_MDRA
PD6_GPIO22
73
M3_MIITXD1
I/O/Z
General-purpose input/output 22
O
EMAC MII transmit data 1
M3_U2TX
O
UART-2 transmit data
M3_EPI0S29
I/O
EPI-0 signal 29
M3_I2C1SDA
I/OD
I2C-0 data open-drain bidirectional port
M3_U1TX
O
UART-1 transmit data
C28_EQEP1S
I/O
Enhanced QEP-1 strobe
C28_MCLKXA
O
McBSP-A transmit clock
PD7_GPIO23
68
I/O/Z
General-purpose input/output 23
M3_CCP1
I/O
Capture/Compare/PWM-1 (General-purpose Timer)
M3_MIITXD0
O
EMAC MII transmit data 0
M3_U1DTR
O
UART-1 data terminal ready
M3_EPI0S30
I/O
EPI-0 signal 30
M3_I2C1SCL
I/OD
M3_U1RX
I
I2C-1 clock open-drain bidirectional port
UART-1 receive data
C28_EQEP1I
I/O
Enhanced QEP-1 index
C28_MFSXA
O
McBSP-A transmit frame sync
PE0_GPIO24
43
PRODUCT PREVIEW
NAME
I/O/Z
General-purpose input/output 24
M3_SSI1CLK
I/O
SSI-1 clock
M3_CCP3
I/O
Capture/Compare/PWM-3 (General-purpose Timer)
M3_EPI0S8
I/O
EPI-0 signal 8
M3_USB0PFLT
I
USB-0 external power error state (optionally used in the host mode)
M3_SSI3TX
O
SSI-3 transmit data
M3_CAN0RX
I
CAN-1 receive data
M3_SSI1TX
O
SSI-1 transmit data
C28_ECAP1
I/O
Enhanced Capture-1 input/output
C28_EQEP2A
I
Enhanced QEP-2 input A
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
PE1_GPIO25
RFP
PIN #
I/O/Z
45
I/O/Z
DESCRIPTION
General-purpose input/output 25
M3_SSI1FSS
I/O
SSI-1 frame
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_CCP6
I/O
Capture/Compare/PWM-6 (General-purpose Timer)
M3_EPI0S9
I/O
EPI-0 signal 9
M3_SSI3RX
I
SSI-3 receive data
M3_CAN0TX
O
CAN-1 transmit data
M3_SSI1RX
O
SSI-1 transmit data
C28_ECAP2
I/O
Enhanced Capture-2 input/output
C28_EQEP2B
PE2_GPIO26
I
32
M3_CCP4
Enhanced QEP-2 input B
I/O/Z
I/O
M3_SSI1RX
General-purpose input/output 26
Capture/Compare/PWM-4 (General-purpose Timer)
I
SSI-1 receive data
PRODUCT PREVIEW
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_EPI0S24
I/O
EPI-0 signal 24
M3_SSI3CLK
I/O
SSI-3 clock
M3_U2RX
I
UART-2 receive data
M3_SSI1CLK
I/O
SSI-1 clock
C28_ECAP3
I/O
Enhanced Capture-3 input/output
I/O
Enhanced QEP-2 index
C28_EQEP2I
PE3_GPIO27
33
M3_CCP1
I/O/Z
General-purpose input/output 27
I/O
Capture/Compare/PWM-1 (General-purpose Timer)
M3_SSI1TX
O
SSI-1 transmit data
M3_CCP7
I/O
Capture/Compare/PWM-7 (General-purpose Timer)
M3_EPI0S25
I/O
EPI-0 signal 25
M3_SSI3FSS
I/O
SSI-3 frame
M3_U2TX
O
UART-2 transmit data
M3_SSI1FSS
I/O
SSI-1 frame
C28_ECAP4
I/O
Enhanced Capture-4 input/output
I/O
Enhanced QEP-2 strobe
C28_EQEP2S
PE4_GPIO28
77
M3_CCP3
I/O/Z
General-purpose input/output 28
I/O
Capture/Compare/PWM-3 (General-purpose Timer)
M3_U2TX
O
UART-2 transmit data
M3_CCP2
I/O
Capture/Compare/PWM-2 (General-purpose Timer)
M3_MIIRXD0
I
EMAC MII receive data 0
M3_U0RX
I
UART-0 receive data
M3_USB0EPEN
O
USB-0 external power enable (optionally used in the host mode)
C28_SCIRXDA
I
SCI-A receive data
PE5_GPIO29
76
I/O/Z
General-purpose input/output 29
M3_CCP5
I/O
Capture/Compare/PWM-5 (General-purpose Timer)
M3_MIITXER
O
EMAC MII transmit error
M3_U0TX
O
UART-0 transmit data
M3_USB0PFLT
I
USB-0 external power error state (optionally used in the host mode)
C28_SCITXDA
O
SCI-A transmit data
16
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PE6_GPIO30
RFP
PIN #
I/O/Z
22
I/O/Z
M3_U1CTS
I
DESCRIPTION
General-purpose input/output 30
UART-1 clear-to-send modem status
M3_MIIMDIO
I/O
M3_CAN0RX
I
CAN-0 receive data
C28_EPWM9A
O
Enhanced PWM-9 output A
PE7_GPIO31
23
EMAC MII MDIO
I/O/Z
General-purpose input/output 31
M3_OFSD2N
O
USB PHY OFSD2N
M3_U1DCD
I
UART-1 data carrier detect
M3_MIIRXD3
I
EMAC MII receive data 3
M3_CAN0TX
O
CAN-0 transmit data
C28_EPWM9B
O
Enhanced PWM-9 output B
PF0_GPIO32
104
I/O/Z
General-purpose input/output 32
M3_CAN1RX
I
CAN-1 receive data
M3_MIIRXCK
I
EMAC MII receive clock
M3_IID
I
USB PHY IID
I
UART-1 data set ready
M3_U1DSR
M3_I2C0SDA
I/OD
M3_TRACED2
O
C28_SDAA
I2C-0 data open-drain bidirectional port
Emulation trace data 2 (EMU3)
I/OD
I2C-A data open-drain bidirectional port
C28_SCIRXDA
I
SCI-A receive data
C28_ADCSOCAO
O
ADC start-of-conversion A
PF1_GPIO33
103
I/O/Z
General-purpose input/output 33
M3_CAN1TX
O
CAN-1 transmit data
M3_MIIRXER
I
EMAC MII receive error
M3_ISESSEND
I
USB PHY ISESSEND
M3_U1RTS
O
UART-1 request-to-send
M3_CCP3
I/O
Capture/Compare/PWM-3 (General-purpose Timer)
M3_I2C0SCL
I/OD
M3_TRACED3
O
C28_SCLA
I2C-0 clock open-drain bidirectional port
Emulation trace data 3 (EMU4)
I/OD
I2C-A clock open-drain bidirectional port
C28_EPWMSYNCO
O
Enhanced PWM sync out
C28_ADCSOCBO
O
ADC start-of-conversion B
PF2_GPIO34
82
PRODUCT PREVIEW
NAME
I/O/Z
General-purpose input/output 34
M3_MIIPHYINTR
I
EMAC PHY MII interrupt
M3_IAVALID
I
USB PHY IAVALID
M3_SSI1CLK
I/O
SSI-1 clock
M3_TRACECLK
O
Emulation trace clock (EMU2)
M3_XCLKOUT
O
Main PLL clock (divided by 1, 2 or 4)
C28_ECAP1
I/O
Enhanced Capture-1 input/output
C28_SCIRXDA
I
SCI-A receive data
C28_XCLKOUT
O
Main PLL clock (divided by 1, 2 or 4)
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
PF3_GPIO35
RFP
PIN #
I/O/Z
81
I/O/Z
M3_MIIMDC
M3_IVBUSVALID
DESCRIPTION
General-purpose input/output 35
I
EMAC PHY MII MDC
I
USB PHY IVBUSVALID
M3_SSI1FSS
I/O
SSI-1 frame
M3_U0TX
O
UART-0 transmit data
M3_TRACED0
O
Emulation trace data 0 (EMU0)
C28_SCITXDA
O
SCI-A transmit data
PF4_GPIO36
48
I/O/Z
General-purpose input/output 36
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_MIIMDIO
I/O
EMAC MII MDIO
I
USB PHY IXRCV
M3_IXRCV
PRODUCT PREVIEW
M3_EPI0S12
I/O
M3_SSI1RX
I
SSI-1 receive data
M3_U0RX
I
UART-0 receive data
C28_SCIRXDA
I
SCI-A receive data
PF5_GPIO37
51
M3_CCP2
EPI-0 signal 12
I/O/Z
I/O
General-purpose input/output 37
Capture/Compare/PWM-2 (General-purpose Timer)
M3_MIIRXD3
I
EMAC MII receive data 3
M3_IDM
I
USB PHY IDM
M3_EPI0S15
I/O
EPI-0 signal 15
M3_SSI1TX
O
SSI-1 transmit data
C28_ECAP2
I/O
Enhanced Capture-2 input/output
I/O/Z
General-purpose input/output 38
PF6_GPIO38
69
M3_USB0VBUS
Analog
M3_CCP1
I/O
USB0 VBUS power
Capture/Compare/PWM-1 (General-purpose Timer)
M3_MIIRXD2
I
EMAC MII receive data 2
M3_IDP
I
USB PHY IDP
M3_U1RTS
O
UART-1 request-to-send
PF7_GPIO39
No Pin
No Pin
PG0_GPIO40
49
I/O/Z
M3_U2RX
I
M3_I2C1SCL
General-purpose input/output 39 is not pinned out.
General-purpose input/output 40
UART-2 receive data
I/OD
I2C-1 clock open-drain bidirectional port
M3_USB0EPEN
O
USB-0 external power enable (optionally used in the host mode)
M3_EPI0S13
I/O
EPI-0 signal 13
M3_MIIRXD2
I
EMAC MII receive data 2
I
UART-4 receive data
M3_U4RX
PG1_GPIO41
M3_U2TX
M3_I2C1SDA
50
I/O/Z
O
General-purpose input/output 41
UART-2 transmit data
I/OD
I2C-1 data open-drain bidirectional port
M3_ODISCHRGVBUS
O
USB PHY ODISCHRGVBUS
M3_EPI0S14
I/O
EPI-0 signal 14
M3_MIIRXD1
I
EMAC MII receive data 1
M3_U4TX
O
UART-4 transmit data
18
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PG2_GPIO42
RFP
PIN #
71
M3_USB0DM
I/O/Z
I/O/Z
Analog
DESCRIPTION
General-purpose input/output 42
USB0 data minus
M3_MIICOL
I
EMAC MII collision detect
M3_OCHRGVBUS
O
USB PHY OCHRGVBUS
PG3_GPIO43
78
I/O/Z
General-purpose input/output 43
M3_MIICRS
I
EMAC MII carrier sense
M3_ODMPULLDN
O
USB PHY ODISCHRGVBUS
M3_MIIRXDV
I
EMAC MII receive data valid
M3_TRACED1
O
Emulation trace data 1 (EMU1)
PF7_GPIO44
No Pin
No Pin
PG5_GPIO45
72
I/O/Z
M3_USB0DP
Analog
General-purpose input/output 44 is not pinned out.
General-purpose input/output 45
USB0 data plus
M3_CCP5
I/O
Capture/Compare/PWM-5 (General-purpose Timer)
M3_MIITXEN
O
EMAC MII transmit enable
M3_OLSD2N
O
USB PHY OLSD2N
O
UART-1 data terminal ready
M3_U1DTR
PG6_GPIO46
70
I/O/Z
General-purpose input/output 46
M3_USB0ID
Analog
M3_MIITCK
I
EMAC MII transmit clock
M3_OLSD1N
O
USB PHY OLSD1N
M3_U1RI
I
UART-1 receive data
PG7_GPIO47
52
I/O/Z
USB0 ID
General-purpose input/output 47
M3_MIITXER
O
EMAC MII transmit error
M3_OIDPULLUP
O
USB PHY OIDPULLUP
M3_EPI0S31
I/O
EPI-0 signal 31
PH0_GPIO48
41
I/O/Z
General-purpose input/output 48
M3_CCP6
I/O
Capture/Compare/PWM-6 (General-purpose Timer)
M3_MIIPHYRST
O
EMAC PHY MII reset
M3_OSPEED
O
USB PHY OSPEED
M3_EPI0S6
I/O
EPI-0 signal 6
M3_SSI3TX
O
SSI-3 transmit data
C28_ECAP5
I/O
Enhanced Capture-5 input/output
I/O/Z
General-purpose input/output 49
PH1_GPIO49
42
M3_CCP7
I/O
Capture/Compare/PWM-7 (General-purpose Timer)
M3_OSUSPEND
O
USB PHY OSUSPEND
M3_EPI0S7
I/O
EPI-0 signal 7
M3_MIIRXD0
I
EMAC MII receive data 0
M3_SSI3RX
I
SSI-3 receive data
C28_ECAP6
I/O
Enhanced Capture-6 input/output
I/O/Z
General-purpose input/output 50
PH2_GPIO50
36
PRODUCT PREVIEW
NAME
M3_OOE
O
USB PHY OSUSPEND
M3_EPI0S1
I/O
EPI-0 signal 1
M3_MIITXD3
O
EMAC MII transmit data 3
M3_SSI3CLK
I/O
SSI-3 clock
C28_EQEP1A
I
Enhanced QEP-2 input B
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
PH3_GPIO51
RFP
PIN #
I/O/Z
35
I/O/Z
M3_USB0EPEN
DESCRIPTION
General-purpose input/output 51
O
USB-0 external power enable (optionally used in the host mode)
M3_ODMSE0
O
USB PHY ODMSE0
M3_EPI0S0
I/O
EPI-0 signal 0
M3_MIITXD2
O
EMAC MII transmit data 2
M3_SSI3FSS
I/O
SSI-3 frame
C28_EQEP1B
I
PH4_GPIO52
46
M3_USB0FLT
Enhanced QEP-1 input B
I/O/Z
General-purpose input/output 52
PRODUCT PREVIEW
I
USB-0 external power error state (optionally used in the host mode)
M3_ODPDAT
O
USB PHY ODPDAT
M3_EPI0S10
I/O
EPI-0 signal 10
M3_MIITXD1
O
EMAC MII transmit data 1
M3_SSI1CLK
I/O
SSI-1 clock
M3_U3TX
O
UART-3 transmit data
C28_EQEP1S
I/O
Enhanced QEP-1 strobe
PH5_GPIO53
47
I/O/Z
General-purpose input/output 53
M3_EPI0S11
I/O
EPI-0 signal 11
M3_MIITXD0
O
EMAC MII transmit data 0
M3_SSI1FSS
I/O
SSI-1 frame
M3_U3RX
I
C28_EQEP1I
PH6_GPIO54
UART-3 receive data
I/O
79
Enhanced QEP-1 index
I/O/Z
General-purpose input/output 54
M3_EPI0S26
I/O
M3_MIIRXDV
I
EMAC MII receive data valid
M3_SSI1RX
I
SSI-1 receive data
M3_MIITXEN
O
EMAC MII transmit enable
M3_SSI0TX
O
SSI-0 transmit data
C28_SPISIMOA
I/O
SPI-A slave in, master out
I
Enhanced QEP-1 input A
C28_EQEP3A
PH7_GPIO55
80
EPI-0 signal 26
I/O/Z
General-purpose input/output 55
M3_MIIRXCK
I
M3_EPI0S27
I/O
EPI-0 signal 27
M3_SSI1TX
O
SSI-1 transmit data
M3_MIITXCK
I
EMAC MII transmit clock
M3_SSI0RX
I
SSI-0 receive data
C28_SPISOMIA
C28_EQEP3B
PJ0_GPIO56
M3_MIIRXER
M3_EPI016
63
EMAC MII receive clock
I/O
SPI-A master in, slave out
I
Enhanced QEP-3 input B
I/O/Z
I
General-purpose input/output 56
EMAC MII receive error
I/O
EPI-0 signal 16
M3_I2C1SCL
I/OD
M3_SSI0CLK
I/O
SSI-0 clock
C28_SPICLKA
I/O
SPI-A clock
C28_EQEP3S
I/O
Enhanced QEP-3 strobe
20
I2C-1 clock open-drain bidirectional port
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PJ1_GPIO57
RFP
PIN #
I/O/Z
62
I/O/Z
M3_EPI0S17
I/O
M3_USB0PFLT
DESCRIPTION
General-purpose input/output 57
EPI-0 signal 17
I
USB-0 external power error state (optionally used in the host mode)
M3_I2C1SDA
I/OD
M3_MIIRXDV
I
M3_SSI0FSS
I/O
SSI-0 frame
C28_SPISTEA
I/O
SPI-A slave transmit enable
C28_EQEP3I
I/O
Enhanced QEP-3 index
PJ2_GPIO58
61
I2C-1 data open-drain bidirectional port
EMAC MII receive data valid
I/O/Z
General-purpose input/output 58
M3_EPI0S18
I/O
EPI-0 signal 18
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_MIIRXCK
I
M3_SSI0CLK
I/O
SSI-0 clock
M3_U0TX
O
UART-0 transmit data
C28_MCLKRA
I
McBSP-A receive clock
O
Enhanced PWM-7 output A
C28_EPWM7A
PJ3_GPIO59
60
M3_EPI0S19
EMAC MII receive clock
I/O/Z
I/O
M3_U1CTS
General-purpose input/output 59
EPI-0 signal 19
I
UART-1 clear-to-send
M3_CCP6
I/O
Capture/Compare/PWM-6 (General-purpose Timer)
M3_MIIMDC
O
EMAC PHY MII MDC
M3_SSI0FSS
I/O
SSI-0 frame
M3_U0RX
I
UART-0 receive data
C28_MFSRA
I
McBSP-A receive frame sync
C28_EPWM7B
O
Enhanced PWM-7 output B
PJ4_GPIO60
57
I/O/Z
M3_EPI0S28
I/O
M3_U1DCD
I
M3_CCP4
General-purpose input/output 60
EPI-0 signal 28
UART-1 data carrier detect
I/O
M3_MIICOL
Capture/Compare/PWM-4 (General-purpose Timer)
I
EMAC MII collision detect
M3_SSI1CLK
I/O
SSI-1 clock
C28_EPWM8A
O
Enhanced PWM-8 output A
PJ5_GPIO61
56
I/O/Z
M3_EPI0S29
I/O
M3_U1DSR
I
M3_CCP2
General-purpose input/output 61
EPI-0 signal 29
UART-1 data set ready
I/O
M3_MIICRS
Capture/Compare/PWM-2 (General-purpose Timer)
I
EMAC PHY MII CRS
M3_SSI1FSS
I/O
SSI-1 frame
C28_EPWM8B
O
Enhanced PWM-8 output B
PJ6_GPIO62
53
PRODUCT PREVIEW
NAME
I/O/Z
General-purpose input/output 62
M3_EPI0S30
I/O
EPI-0 signal 30
M3_U1RTS
O
UART-1 request-to-send
M3_CCP1
I/O
Capture/Compare/PWM-1 (General-purpose Timer)
M3_MIIPHYINTR
I
EMAC PHY MII interrupt
M3_U2RX
I
UART-2 receive data
C28_EPWM9A
O
Enhanced PWM-9 output A
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
PJ7_GPIO63
RFP
PIN #
I/O/Z
97
I/O/Z
DESCRIPTION
General-purpose input/output 63
M3_U1DTR
O
UART-1 data terminal ready
M3_CCP0
I/O
Capture/Compare/PWM-0 (General-purpose Timer)
M3_MIIPHYRST
O
EMAC PHY MII reset
M3_U2TX
O
UART-2 transmit data
O
Enhanced PWM-9 output B
C28_EPWM9B
PC0_GPIO64
No Pin
No Pin
General-purpose input/output 64 is not pinned out
PC1_GPIO65
No Pin
No Pin
General-purpose input/output 65 is not pinned out
PC2_GPIO66
No Pin
No Pin
General-purpose input/output 66 is not pinned out
PC3_GPIO67
No Pin
No Pin
General-purpose input/output 67 is not pinned out
PC4_GPIO68
37
I/O/Z
General-purpose input/output 68
PRODUCT PREVIEW
M3_CCP5
I
Capture/Compare/PWM-5 (General-purpose Timer)
M3_MIITXD3
O
EMAC MII transmit data 3
M3_CCP2
I
Capture/Compare/PWM-2 (General-purpose Timer)
M3_CCP4
I
Capture/Compare/PWM-4 (General-purpose Timer)
M3_EPI0S2
I/O
M3_CCP1
PC5_GPIO69
EPI-0 signal 2
I
38
M3_CCP1
Capture/Compare/PWM-1 (General-purpose Timer)
I/O/Z
General-purpose input/output 69
I
Capture/Compare/PWM-1 (General-purpose Timer)
M3_CCP3
I
Capture/Compare/PWM-3 (General-purpose Timer)
M3_USB0EPEN
O
USB-0 external power enable (optionally used in the host mode)
M3_EPI0S3
I/O
EPI-0 signal 3
PC6_GPIO70
39
I/O/Z
General-purpose input/output 70
M3_CCP3
I
Capture/Compare/PWM-3 (General-purpose Timer)
M3_U1RX
I
UART-1 receive data
M3_CCP0
I
Capture/Compare/PWM-0 (General-purpose Timer)
M3_USB0PFLT
I
USB-0 external power error state (optionally used in the host mode)
M3_EPI0S4
PC7_GPIO71
I/O
40
EPI-0 signal 4
I/O/Z
General-purpose input/output 71
M3_CCP4
I
Capture/Compare/PWM-4 (General-purpose Timer)
M3_CCP0
I
Capture/Compare/PWM-0 (General-purpose Timer)
M3_U1TX
O
UART-1 transmit data
I
USB-0 external power error state (optionally used in the host mode)
M3_USB0PFLT
M3_EPI0S5
22
I/O
EPI-0 signal 5
Device Pins
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
RFP
PIN #
I/O/Z
DESCRIPTION
I/OD
Digital Subsystem Reset (in) and Watchdog/Brown-out Reset (out). In most
applications, it is recommended that the XRS pin be tied with the ARS pin. The
Digital Subsystem has a built-in power-on-reset (POR) and brown-out-reset
(BOR) circuitry. As such, no external circuitry is needed to generate a reset
pulse. During a power-on or brown-out condition, this pin is driven low by the
Digital Subsystem. This pin is also driven low by the Digital Subsystem when a
watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry
may also drive this pin to assert device reset. In this case, it is recommended
that this pin be driven by an open-drain device. An R-C circuit must be
connected to this pin for noise immunity reasons. Regardless of the source, a
device reset causes the Digital Subsystem to terminate execution. The M3
program counter points to the address contained at the location 0x00000004.
The C28 program counter points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution begins at the location
designated by the program counter. The output buffer of this pin is an
open-drain with an internal pullup.
I/OD
Analog Subsystem Reset (in) and Brown-out Reset (out).In most applications, it
is recommended that the ARS pin be tied with the XRS pin. The Digital
Subsystem has a built-in brown-out-reset (BOR) circuitry. As such, no external
circuitry is needed to generate a reset pulse. During a power-on or brown-out
condition, this pin is driven low by the Analog Subsystem. If need be, an
external circuitry may also drive this pin to assert a device reset. In this case, it
is recommended that this pin be driven by an open-drain device. An R-C circuit
must be connected to this pin for noise immunity reasons. Regardless of the
source, the Analog Subsystem reset causes the digital logic associated with the
Analog Subsystem, to enter reset state. The output buffer of this pin is an
open-drain with an internal pullup.
XRS
ARS
4
144
Clocks
X1
93
I
On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a
ceramic resonator must be connected across X1 and X2. In this case, the
XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not
used, it must be tied to GND.
X2
95
O
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must
be connected across X1 and X2. If X2 is not used, it must be left unconnected.
XCLKIN
see
PJ7_GPIO63
I
External oscillator input. This pin feeds a clock from an external 3.3-V oscillator
to internal USB PLL module and to the CAN peripherals.
XCLKOUT
see
PF2_GPIO34
O/Z
External oscillator output. This pin outputs a clock divided-down from the
internal PLL System Clock. The divide ratio is defined in the XCLKCFG register.
Device Pins
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PRODUCT PREVIEW
Reset
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
RFP
PIN #
I/O/Z
DESCRIPTION
JTAG
PRODUCT PREVIEW
TRST
85
I
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or
driven low, the device operates in its functional mode, and the test reset signals
are ignored. NOTE: TRST is an active-high test pin and must be maintained low
during normal device operation. An external pull-down resistor is required on
this pin. The value of this resistor should be based on drive strength of the
debugger pods applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is recommended that
each target board be validated for proper operation of the debugger and the
application. (↓)
TCK
89
I
JTAG test clock with internal pullup (↑)
TMS
87
I
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK. (↑)
TDI
88
I
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK. (↑)
TDO
84
O/Z
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. (8-mA
drive)
O/Z
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or
from the emulator system and is defined as input/output through the JTAG scan.
This pin is also used to put the device into boundary-scan mode. With the
EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising
edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z,
8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this
resistor should be based on the drive strength of the debugger pods applicable
to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is
application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application.
86
O/Z
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or
from the emulator system and is defined as input/output through the JTAG scan.
This pin is also used to put the device into boundary-scan mode. With the
EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising
edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z,
8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this
resistor should be based on the drive strength of the debugger pods applicable
to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is
application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application.
TRACE_D0
see
PF3_GPIO35
O/Z
Emulation Trace D0 (EMU0) – requires 20-pin JTAG header
TRACE_D1
see
PG3_GPIO43
O/Z
Emulation Trace D1 (EMU1) – requires 20-pin JTAG header
TRACE_CLK
see
PF2_GPIO34
O/Z
Emulation Trace CLK (EMU2) – requires 20-pin JTAG header
TRACE_D2
see
PF0_GPIO32
O/Z
Emulation Trace D2 (EMU3) – requires 20-pin JTAG header
TRACE_D3
see
PF1_GPIO33
O/Z
Emulation Trace D3 (EMU4) – requires 20-pin JTAG header
EMU0
83
EMU1
FLASH and Reserved Pins
RSV
140
RSV
110
FLT1
16
I/O
FLASH Test Pin 1. Reserved for TI. Must be left unconnected.
FLT2
21
I/O
FLASH Test Pin 2. Reserved for TI. Must be left unconnected.
24
Reserved for TI. Must be left unconnected.
Reserved for TI. Must be left unconnected.
Device Pins
Copyright © 2011, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
RFP
PIN #
I/O/Z
DESCRIPTION
Internal Voltage Regulator Control
VREG18EN
113
Internal 1.8-V VREG Enable/Disable for VDD18. Pull low to enable the internal
1.8-V voltage regulator (VREG18), pull high to disable VREG18.
VREG12EN
101
Internal 1.2-V VREG Enable/Disable for VDD12. Pull low to enable the internal
1.2-V voltage regulator (VREG12), pull high to disable VREG12.
Analog, Digital, and I/O Power
119
3.3-V Analog Module 1 Power Pin. Tie with a 2.2-µF capacitor (typical) close to
the pin.
VDDA2
134
3.3-V Analog Module 2 Power Pin. Tie with a 2.2-µF capacitor (typical) close to
the pin.
VDDIO
107
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
10
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
25
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
34
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
44
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
54
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
59
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
105
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
3
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
67
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
74
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
92
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
100
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
96
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
17
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
2
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDDIO
106
3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)
close to the pin.
VDD18
VDD18
PRODUCT PREVIEW
VDDA1
1
1.8-V Digital Logic Power Pins (associated with the Analog Subsytem) - no
supply needed when using internal VREG18. Tie with 1.2-µF (minimum)
ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher
value capacitors may be used but could impact supply-rail ramp-up time.
108
1.8-V Digital Logic Power Pins (associated with the Analog Subsytem) - no
supply needed when using internal VREG18. Tie with 1.2-µF (minimum)
ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher
value capacitors may be used but could impact supply-rail ramp-up time.
Device Pins
Copyright © 2011, Texas Instruments Incorporated
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25
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
NAME
RFP
PIN #
I/O/Z
DESCRIPTION
VDD12
24
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
VDD12
55
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
VDD12
66
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
99
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
75
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
58
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
11
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
91
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
90
1.2-V Digital Logic Power Pins - no supply needed when using internal
VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value capacitors may be used but
could impact supply-rail ramp-up time.
VDD12
VDD12
PRODUCT PREVIEW
VDD12
VDD12
VDD12
VDD12
VSS
PWR PAD
VSSOSC
26
94
Analog and Digital Ground Power Pad (located on the bottom of the chip).
Clock Oscillator Ground Pin
Device Pins
Copyright © 2011, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742 – JUNE 2011
www.ti.com
4 Mechanical Packaging and Orderable Information
4.1
Packaging Information
PRODUCT PREVIEW
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Copyright © 2011, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
27
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
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F28M35H20B1RFPS
PREVIEW
HTQFP
RFP
144
1000
TBD
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1000
TBD
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TBD
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F28M35H20B1RFPT
PREVIEW
HTQFP
RFP
144
F28M35H20C1RFPS
PREVIEW
HTQFP
RFP
144
F28M35H20C1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H22B1RFPQ
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H22B1RFPS
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H22B1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H22C1RFPS
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H22C1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H32B1RFPQ
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H32B1RFPS
PREVIEW
HTQFP
RFP
144
TBD
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F28M35H32B1RFPT
PREVIEW
HTQFP
RFP
144
TBD
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F28M35H32C1RFPS
PREVIEW
HTQFP
RFP
144
TBD
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F28M35H32C1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
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F28M35H50B1RFPQ
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H50B1RFPS
PREVIEW
HTQFP
RFP
144
1000
TBD
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F28M35H50B1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
Call TI
F28M35H50C1RFPS
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
Call TI
F28M35H50C1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
Call TI
F28M35H52B1RFPQ
PREVIEW
HTQFP
RFP
144
TBD
Call TI
Call TI
F28M35H52B1RFPS
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
Call TI
F28M35H52B1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
Call TI
F28M35H52C1RFPS
PREVIEW
HTQFP
RFP
144
TBD
Call TI
Call TI
F28M35H52C1RFPT
PREVIEW
HTQFP
RFP
144
1000
TBD
Call TI
Call TI
XF28M35H52C1RFPT
ACTIVE
HTQFP
RFP
144
1
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
(Requires Login)
F28M35H20B1RFPQ
1000
(3)
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2011
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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