UTC-IC UPS703

UNISONIC TECHNOLOGIES CO., LTD
UPS703
LINEAR INTEGRATED CIRCUIT
HIGH PERFORMANCE
CURRENT MODE POWER
SWITCH
„
DESCRIPTION
The UTC UPS703 is designed for several special
enhancements to satisfy the demands, for example, Power-Saving
mode for low standby power (<0.3W), Frequency Hopping ,
Constant Output Power Limiting , Slope Compensation ,Over
Current Protection (OCP), Over Voltage Protection (OVP), Over
Load Protection (OLP), Under Voltage Lock Out (UVLO), Short
Circuit Protection (SCP) , Over Temperature Protection (OTP) etc.
IC will be shutdown or can auto-restart in relative situations.
„
DIP-8
FEATURE
* Low Startup Current (About 22μA)
* Fixed Switching Frequency(Norm. is 68KHz)
* Frequency Hopping For Improved EMI Performance.
* Lower Than 0.3W Standby Power Design
* Linearly Decreasing Frequency to 26KHz During Light Load
* Soft Start
* Internal Slope Compensation
* Constant Power Limiting For Universal AC Input Range
* Gate Output Maximum Voltage Clamp(15V)
* Max Duty Cycle 74%
* Over Temperature Protection
* Overload Protection
* Over Voltage Protection
* Leading Edge Blanking
* Cycle-by-Cycle Current Limiting
* Under Voltage Lock Out
* Short Circuit Protection
„
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UPS703L-D08-T
UPS703G-D08-T
www.unisonic.com.tw
Copyright © 2011 Unisonic Technologies Co., Ltd
Package
Packing
DIP-8
Tube
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QW-R119-015.C
UPS703
„
„
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
DRAIN
1
8
DRAIN
VIN
2
7
CS
VCC
3
6
FB
GND
4
5
SS
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
NAME
DRAIN
VIN
VCC
GND
SS
FB
CS
DRAIN
FUNCTION
Power MOSFET drain
For startup and constant power limit, this pin is pulled to the line input via resistor
Supply voltage
Ground
Soft-start
Feedback
Controller current sense input
Power MOSFET drain
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LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
Notes: OLP (Over Load Protection)
OVP (Over Voltage Protection)
OTP (Over Temperature Protection)
OCP (Over Current Protection)
UVLO (Under Voltage Latch-Out)
LEB (Led Edge Blanking)
SS (Soft Start)
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LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
30
V
Input Voltage to Vin Pin
Vin
30
V
Input Voltage to FB Pin
VFB
-0.3 ~ 6.2
V
Input Voltage to CS Pin
VCS
-0.3 ~ 2.8
V
Junction Temperature
TJ
150
°C
Operating Temperature
TOPR
-40 ~ +125
°C
Storage Temperature
TSTG
-50 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
„
SYMBOL
VCC
RATINGS
8.6 ~ 22
UNIT
V
ELECTRICAL CHARACTERISTICS (Ta=25°C, VCC=15V, unless otherwise specified)
PARAMETER
SUPPLY SECTION
Start Up Current
Supply Current with Switch
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold Voltage
Min. Operating Voltage
Hysteresis
INTERNAL VOLTAGE REFERENCE
Reference Voltage
CONTROL SECTION
VFB Operating Level
Burst-Mode Out FB Voltage
Reduce-Frequency end FB Voltage
Burst-Mode Enter FB Voltage
Normal
Switch Frequency
Power-Saving
Duty Cycle
Frequency Hopping
Frequency Variation VS VCC Deviation
Frequency Variation VS Temperature
Deviation
Feedback Resistor
Soft-Start Time
PROTECTION SECTION
OVP Threshold
OLP Threshold
Delay Time Of OLP
OTP Threshold
OVP Disable Threshold
OLP Enable Threshold
SYMBOL
ISTR
IOFF
ION
VREF
VMIN
VMAX
VFB(OUT)
VFB(END)
VFB(IN)
MIN
TYP
MAX
UNIT
22
7
7
45
9
9
μA
mA
mA
13.5
7.5
14.2
8.2
6
15
9
V
V
V
6.3
6.5
6.7
V
VCC = VCC(ON)-0.1V
VSS = 0, IFB = 0
VSS = 4.8V, IFB = 0
VTHD(ON)
VCC(MIN)
VCC(HY)
measured at pin VFB
VCC=10 to 20V
±4.5
5
V
V
V
V
V
kHz
kHz
%
%
kHz
%
FDT
T=-40 to 105°C
5
%
RFB
TSS
VFB=0V
CSS=0.47μF
26
12.6
kΩ
ms
5.1
70
150
4.3
5.7
V
V
V
ms
°C
V
V
F(SW)
DMAX
DMIN
FJ(SW)
FDV
VOVP1
VOVP2
VFB(OLP)
TD-OLP
T(THR)
VSS(DEACT)
VSS(ACT)
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TEST CONDITIONS
0.5
4.4
VCS =0
VCS =0
VCS =0
VFB = 4V
Before enter burst mode
VFB=4.4V, VCS =0
VFB<0.5V
VSS<3.5V,VFB>5V
VSS=4.8V, VFB=3V
VCS=0, SS OPEN
CSS=0.47μF
VFB>5V, VCC = 22V
VFB>5V
61
20
68
0
±1.5
1.7
1.6
1.5
68
74
±3
16
9.9
21
11.2
4.7
55
120
3.9
5.1
19
28
4.9
62
135
4.1
5.4
75
40
80
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LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
CURRENT LIMITING SECTION
Peak Current Limitation
VCS
VFB=4.4V
Threshold Voltage For IVIN =60μA
VSENSE-L
IVIN=60μA
POWER MOS-TRANSISTOR SECTION
Drain-Source Breakdown Voltage
VDSS
VGS=0V, ID=250μA
Turn-On Voltage between Gate and Source
VTH
VDS=VGS, ID=250μA
Drain-Source Diode Continuous Source
IS
Current
Static Drain-Source On-State Resistance
RDS(ON)
VGS=10V,ID=1.5A
VDD =30V, ID =1.0A
Rise Time
tR
RG=25Ω (Note 1,2)
Fall Time
tF
Notes: 1. Pulse Test: Pulse width≤300μs, Duty cycle≤2%
2. Essentially independent of operating temperature
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MIN
TYP
MAX
UNIT
0.86
0.77
1
V
V
700
2
2.8
30
30
4
V
V
3
A
4
70
70
Ω
ns
ns
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
The internal reference voltages and bias circuit work at VCC> VTHD (ON), and shutdown at VCC<VCC (MIN).
(1) Soft-Start
When every IC power on, driver output duty cycle will be decided by voltage VSS on soft-start capacitor and VCS
on current sense resistor at beginning. After VSS reach 4.2V, the whole soft-start phase end, and driver duty cycle
depend on VFB and VCS. The relation among VSS, VFB and VOUT as followed FIG.3.
Furthermore, soft-start phase should end before VCC reach VCC (MIN) during VCC power on. Otherwise, if soft-start
phase remain not end before VCC reach VCC (MIN) during VCC power on, IC will enter auto-restart phase and not set up
VOUT. So the value of CSS should be between 0.1μFand 4.7μF.
Finally soft-start also set OVP1 active phase. OVP1 active phase between 0 and VSS(DEACT), OVP1 will not be
sensed after VSS reach VSS(DEACT).The Soft-start phase TSS:TSS = 23.8×CSS (ms) (Example: CSS=0.47μF, then
TSS=23.8×0.47=11.2ms).
VSS
4.2V
TSOFT-START
t
VFB
4.8V
t
VOUT
TSTRAT-UP
t
Driver
t
Fig.3 Soft-start phase
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
fsw (kHz)
(2) Switch Frequency Set
The maximum switch frequency is set to 68kHz. Switch frequency is modulated by output power POUT during IC
operating. At no load or light load condition, most of the power dissipation in a switching mode power supply is from
switching loss on the MOSFET transistor, the core loss of the transformer and the loss on the subber circuit. The
magnitude of power loss is in proportion to the number of switching events within a fixed period of time. So lower
switch frequency at lower load, which more and more improve IC’s efficiency at light load. At from no load to light
load condition, The IC will operate at from Burst mode to Reducing Frequency Mode. The relation curve between fSW
and POUT/POUT (MAX) as followed FIG.4.
FIG.4 The relation curve between fSW and relative output power POUT/ POUT (MAX)
(3) Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM
generation, this greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus
reduces the output ripple voltage.
(4) Frequency Hopping For EMI Improvement
The Frequency hopping is implemented in the IC; there are two oscillators built-in the IC. The first oscillator
is to set the normal switching frequency; the switching frequency is modulated with a period signal generated by the
2nd oscillator. The relation between the first oscillator and the 2nd oscillator as followed FIG.5. So the tone energy is
evenly spread out, the spread spectrum minimizes the conduction band EMI and therefore eases the system design
in meeting stringent EMI requirement.
Fosc
(kHz)
FSW_MAX
FSW_TYP
FSW_MIN
THopping
t(ms)
FIG.5 Frequency Hopping
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
(5) Constant Output Power Limit
When the SENSE voltage, across the sense resistor RS, reaches the threshold voltage, around 0.8V, the output
GATE drive will be turned off after a small propagation delay tD. This propagation delay will introduce an additional
current proportional to tD×VIN/Lp. Since the propagation delay is nearly constant regardless of the input line voltage
VIN. Higher input line voltage will result in a larger additional current and hence the output power limit is also higher
than that under low input line voltage. To compensate this variation for wide AC input range, the threshold voltage is
adjusted by the VIN current. Since VIN pin is connected to the rectified input line voltage through a resistor RVIN, a
higher line voltage will generate higher VIN current into the VIN pin. The threshold voltage is decreased if the VIN
current is increased. Smaller threshold voltage, forces the output GATE drive to terminate earlier, thus reduce the
total PWM turn-on time and make the output power equal to that of low line input. This proprietary internal
compensation ensures a constant output power limit for wide AC input voltage from 90VAC to 264VAC.
(6) Protection section
The IC takes on more protection functions such as OLP, OVP and OTP etc. In case of those failure modes for
continual blanking time, the driver is shut down. At the same time, IC enters auto-restart, VCC power on and driver is
reset after VCC power on again.
OLP
After soft-start phase end, IC will shutdown driver if over load state occurs for continual TD-OLP. OLP function will
not inactive during soft-start phase. OLP case as followed FIG. 6. The test circuit as followed FIG.8. TD-OLP=5.53×TSS.
OVP
There are two kinds of OVP circuits, the first OVP function are enabled only when VSS<VSS (DEACT) & VFB>VFB
(OLP) during soft-start phase. During above condition, driver will be shutdown if over voltage state occurs (VCC>VOVP1)
for continual a blanking time. The first OVP function will not inactive after soft-start phase. The second OVP will
shutdown the switching of the power MOSFET whenever VCC>VOVP2. The first OVP case as followed FIG.7. The test
circuit as followed FIG.9.
FIG.6 OLP case
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FIG.7 OVP case
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LINEAR INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION(Cont.)
FIG.8 OLP test circuit
FIG.9 OVP test circuit
OTP
OTP will shut down driver when junction temperature TJ>T (THR) for continual a blanking time.
(7) Driver Output Section
The driver-stage drives the gate of the MOSFET and is optimized to minimize EMI and to provide high circuit
efficiency. This is done by reducing the switch on slope when reaching the MOSFET threshold. This is achieved by a
slope control of the rising edge at the driver’s output. The output driver is clamped by an internal 15V Zener diode in
order to protect power MOSFET transistors against undesirable gate over voltage.
(8) Inside power switch MOS transistor
Specific power MOS transistor parameter is as “POWER MOS TRANSISTOR SECTION” in ELECTRICAL
CHARACTERISTICS table.
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LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION CIRCUIT
YC3
C8
R8
F1
LINE
R4
XC1
ZNR1
R3
2 44
1
3
10 T1 1
BD1
3
L1
+1
R2
C1
2
L2
D2
2
C2
C4
9
3
R5
NEUT
LD2
VIN
FB
SS
GND
4
C6
2
3
4
12W
7
R9
R14
R6
3
VCC DRAIN 1
DRAIN
5
12V/1A
1
GND
6
R15
2
C10
8
D3
C3
L3
4
D1
IC1
C5
R13
R12
8
R7
6
CS 7
R1
IC2
4
1
3
2
C9
R10
C7
IC3
R11
FIG.10 UPS703 Typical Application Circuit
Table1. Components reference description for UPS703 application circuit
DESIGNATOR
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
PART TYPE
22μF
102P
22μF
470μF
470μF
104P
103P
102
104
220μF
DESIGNATOR PART TYPE
R1
1.3Ω
R2
68KΩ
R3
2.2MΩ
R4
2.2MΩ
R5
1MΩ
R6
0Ω
R7
0Ω
R8
15Ω
R9
560Ω
R10
1KΩ
R11
3.9KΩ
R12
15KΩ
R13
5.1KΩ
R14
1.8KΩ
R15
1.5MΩ~4.0 MΩ
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DESIGNATOR
D1
D2
D3
IC1
IC2
IC3
T1
L1
L2
L3
LD2
F1
ZNR1
XC1
BD1
YC3
PART TYPE
FR107
SB3100
US1D
UPS703
PC-817
TL431
EE22
UU9.8
2μH
Ring Choke
LED
1.0A/250V
7D471K
154P/275V
B6S
222
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LINEAR INTEGRATED CIRCUIT
TYPICAL CHARACTERISTICS
12V
Feedback Voltage During Loadjump From
10% Up To 100% Load (VAC=90V)
12V
10V
10V
8V
8V
6V
6V
4V
4V
2V
2V
0
0
-2V
-2V
0
2000
Time (400μs/div)
4000
Startup With Full Load Condition at
VAC=90V, VSS and VOUT
8V
0
6V
4V
4V
2V
VSS
0
4000
2000
Time (400μs/div)
Startup With Full Load Condition at
VAC=264V, VSS and VOUT
8V
6V
2V
Feedback Voltage During Loadjump From
10% Up To 100% Load (VAC=264V)
VSS
0
10V
10V
5V
5V
VOUT
0
0
50
Time (10ms/div)
100
Startup Behavior At Nominal Load
Condition VAC=90V
8V
0
6V
4V
4V
100
2V
VSS
0
50
Time (10ms/div)
Startup Behavior At Nominal Load
Condition VAC=264V
8V
6V
2V
VOUT
0
0
4V
4V
2V
2V
VFB
0
0
20
Time (4ms/div)
0
40
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0
20
Time (4ms/div)
40
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LINEAR INTEGRATED CIRCUIT
TYPICAL CHARACTERISTICS(Cont.)
Input Power (W)
Frequency(KHz)
„
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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