PJESDZ6V8-2G E.S.D. Dual Protection Diode Array This Dual Unidirectional ESD Protector Array family have been designed to protect sensitive equipment against ESD in high speed transmission buses, operating at 5V. This dual array offers an integrated solution to protect up to 2 data lines in a unidirectional mode or, 1 data line in a bi-directional mode, in application where the board space is a premium, in our SOT523 package version. PANJIT SOT523 3 SPECIFICATION FEATURES 1 IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance Low Leakage Current, Maximum of 0.5µA at rated voltage 2 Maximum Capacitance of 10pF per device at 0Vdc 1MHz Peak Power Dissipation of 20W 8/20µs Waveform 3 Pin to pin compatible with standard SOT523 Lead Free Package 100% Tin Plating, Matte finish Low profile, Max height of 0.55mm APPLICATIONS 1 2 Mobile Phones Digital Cameras Notebooks PC's MAXIMUM RATINGS (Per Device) Symbol Value Units Peak Pulse Power (8/20µs Waveform) P PP 20 W Peak Pulse Current (8/20µs Waveform) I PPM 2 A ESD Voltage (HBM Per MIL STD883C - Method 3015-6) V ESD 20 kV Operating Temperature Range TJ -55 to +125 °C Storage Temperature Range Tstg -55 to +150 °C Typical Max Units 5.0 V 7.2 V Rating ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C Parameter Reverse Stand-Off Voltage Conditions Symbol Min V WRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 5V 0.5 µA Clamping Voltage (8/20µs) Vc I pp = 2A 10 V Off State Junction Capacitance* Cj 0 Vdc Bias f = 1MHz between pin 1, 2 to 3 (Gnd) 10 pF 6.2 9 * Capacitance between pins 1 and 2 is half of the value, in a bi-directional configuration. 12/9/2008 Page 1 www.panjit.com PJESDZ6V8-2G TYPICAL CHARACTERISTIC CURVES (Per Device) Clamping Voltage vs 8/20µs Ipp Pulse Waveform 9.5 110 100 90 Clamping Voltage, V 9 80 Percent of Ipp Tj = 25°C 50% of Ipp @ 20µs 70 60 50 40 30 Rise time 10-90% - 8µs 20 10 8.5 8 7.5 7 6.5 0 0 5 10 15 time, µsec 20 25 30 0 0.5 1 1.5 Peak Current, A 8/20µs 2 Off-State Capacitance vs DC Bias Junction Capacitnace, pF 10 9 8 7 6 5 4 0 12/9/2008 1 2 3 Vdc Bias, V 4 5 Page 2 www.panjit.com PJESDZ6V8-2G PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT 12/9/2008 Page 3 www.panjit.com