PJQA5V6 QUAD TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION PRELIMINARY This Quad TVS/Zener Array family have been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating in the 3.0Vdc. This TVS array offers an integrated solution to protect up to 4 data lines where the board space is a premium. SPECIFICATION FEATURES 150W (8/20µs), 24W (10/1000µs) Power Dissipation Low Leakage Current, Maximum of 2µA at rated voltage Very Low Clamping Voltage 1 IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance 6 5 4 1 2 3 Industry Standard Surface Mount Package SOT23-6L 100% Tin Matte Finish (RoHS Compliance) APPLICATIONS Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) SOT23-6L Portable Instrumentation Mobile Phones and Accessories Memory Card Port Protection MAXIMUM RATINGS (Per Device) Symbol Value Units Peak Pulse Power (8/20µs Waveform) P pp 150 W ESD Voltage (HBM) V ESD 25 kV Operating Temperature Range TJ -55 to +150 °C Storage Temperature Range Tstg -55 to +150 °C Typical Max Units 3.0 V 5.88 V 2 µA 8 V 9.5 V Rating ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C Parameter Reverse Stand-Off Voltage Conditions Symbol Min VWRM Reverse Breakdown Voltage VBR I BR = 1 mA Reverse Leakage Current IR VR = 3.0V Clamping Voltage (8/20µs) Vc I pp = 5 Amps Clamping Voltage (8/20µs) Vc I pp = 10 Amps Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and pin 2,5 250 pF Off State Junction Capacitance Cj 3 Vdc Bias f = 1MHz Between I/O pins and pin 2,5 160 pF 3/28/2006 Page 1 5.3 5.6 www.panjit.com PJQA5V6 TYPICAL APPLICATION EXAMPLE AND PACKAGE DIMENSIONS PRELIMINARY Data Line 1 Data Line 2 Data Line 3 Data Line 4 PJSMSxx Ground (Pins 2 and 5) 3/28/2006 Page 4 www.panjit.com