FEDL6722-05
OKI Semiconductor
MSM6722
FEDL6722-05
Issue Date: Feb. 27, 2002
OKI Semiconductor
MSM6722
Pitch Control IC for The Speech Signal
GENERAL DESCRIPTION
The MSM6722 converts in real-time the pitch of the speech signal in a range of one octave upward
or downward.
Two pitch control methods can be selected. One is to change the pitch in 17 steps by two switch
inputs, and the other is to select one of 16 steps by four binary input lines.
Since a microphone preamplifier and a low-pass filter are built in, the pitch conversion set can
easily be configured by connecting a microphone, amplifier, and speaker in the peripheral
circuit. The MSM6722 is functionally compared to the MSM6322, as described below.
1. Method of reseting the speech pitch step (UP/DW mode)
MSM6322 ·············· PRST pin only
MSM6722 .............. Two methods are available. One is to reset by the PRST pin only, and
the other is to reset using the UPC and DWC pins coneurrently.
2. Change in pitch
MSM6322 ·············· Speech pitch is changeable in 17 steps.
Pitch step 16
DW
Pitch step 8
UP
Pitch step 0
MSM6722 ·············· The pitch step does not change if a signal is input to the UPC (DWC) pin
when the pitch step is 16 or 0.
Pitch step 16
Pitch step 8
UP, DW
Pitch step 0
3. Additional THR/CHA pin
This pin outputs a voice signal without passing the pitch conversion circuit including
ADC•DAC.
1/21
FEDL6722-05
OKI Semiconductor
MSM6722
FEATURES
• Built-in microphone preamplifier
• Built-in low-pass filters
• Built-in 8-bit AD converter
• Built-in 9-bit DA converter
• Speech pitch alterable in 17 steps (including the no pitch change step)
• Master clock frequency at 4 MHz
• 5 V single power supply
• Package
: 24-pin plastic SOP (SOP24-P-430-1.27-K) (MSM6722GS-K)
Chip
2/21
FEDL6722-05
OKI Semiconductor
MSM6722
BLOCK DIAGRAM
DVDD
SG
–
+
SG
–
+
MIN
AVDD
DGND AGND
TEST
MOUT
LIN
LPF
ADC
8
LOUT
FOUT
VOICE
CHANGER
CIRCUIT
ADIN
AOUT
–
+
LPF
DAC
9
DAO
PD (P3)
UPC (P2)
DWC (P1)
PRST (P0)
TIMING
&
CONTROL
MS
THR/CHG
RESET
SG
CIRCUIT
XT
XT
OSC
SGC
SG
PIN CONFIGURATION (TOP VIEW)
PD (P3) 1
UPC (P2) 2
DWC (P1) 3
PRST (P0) 4
MS 5
THR/CHG 6
TEST 7
DAO 8
AOUT 9
ADIN 10
FOUT 11
AVDD 12
24
23
22
21
20
19
18
17
16
15
14
13
DVDD
XT
XT
RESET
DGND
SG
AGND
SGC
MIN
MOUT
LIN
LOUT
24-Pin Plastic SOP
3/21
FEDL6722-05
OKI Semiconductor
MSM6722
PIN DESCRIPTIONS
Common to UP/DOWN Mode and BINARY Mode
Pin
Symbol
Type
24
DVDD
—
20
DGND
—
12
AVDD
—
18
AGND
—
16
MIN
14
LIN
15
MOUT
13
LOUT
10
ADIN
I
Input pin for the built-in 8-bit AD converter.
11
FOUT
O
Output pin from the built-in LPF. Connect to ADIN Pin.
9
AOUT
O
8
DAO
O
I
O
Description
Digital power supply pin. Insert a bypass capacitor of 0.1 mF or more
between this pin and DGND.
Digital ground pin.
Analog power supply pin. Insert a bypass capacitor of 0.1mF or more
between this pin and AGND.
Analog ground pin.
Inverting input pins for the built-in OP amplifier. The non-inverting
input pin is connected internally to SG.
MOUT and LOUT are output pins of the built-in OP amplifier for MIN
and LIN respectively.
Output pin from built-in LPF. This pin is used to output speech signals
and to connect the amplifier for driving speaker.
Output pin from built-in 9-bit DA converter.
The IC enters the initial state when this pin is at the "L" level.
At this time, the oscillation stops and the DA converter output (DAO)
and audio output (AOUT) fall to the GND level. Then the IC returns to
21
RESET
I
the initial state. The IC has a built-in power-on-reset circuit.
For normal power-on reset operation, supply the power within 1 msec.
If power cannot be supplied within 1 msec, apply a RESET pulse after
the power is switched on.
Select pin for the pitch control or non-pitch control.
6
THR/CHG
I
With a "H" level input, the IC outputs a normal speech signal from the
AOUT pin through the built-in OP amplifier. With a "L" level input, the
IC outputs a pitch controlled speech signal from the AOUT pin.
7
TEST
I
23
XT
I
22
XT
O
19
SG
17
SGC
O
Test pin to be fixed to "L" level.
Crystal oscillator connecting pin. When using the external clock, use
this pin as the input.
Crystal oscillator connecting pin. When using the external clock, this
pin must be left OPEN.
These pins output the reference voltage (signal ground (SG)) of the
analog circuit. The output is approximately 1/2 the AVDD level.
4/21
FEDL6722-05
OKI Semiconductor
MSM6722
UP/DOWN Mode Only
Pin
Symbol
Type
5
MS
I
Mode select pin. This pin must always be tied low.
2
UPC
I
Pins for raising or lowering the pitch by one step at a time.
The pitch changes by one step upward (or downward) each time
a "H" level pulse is input to the UPC (or DWC) pin. The circuit enters
the "no pitch change" state when an "H" level pulse is input to these
pins simultaneously.
3
DWC
1
PD
I
4
PRST
I
Description
Power-down pin. All clocks, including the internal oscillator circuit, are
stopped when the PD pin is set to the "H" level.
Pitch reset pin. The circuit enters the "no pitch change" state when
this pin is set to the "H" level.
Binary Mode Only
Pin
Symbol
Type
5
MS
I
1
P3
2
P2
3
P1
4
P0
Description
Mode select pin. This pin must always be tied high.
The pitch step is directly set by 4 pins (bits) of P3 (MSB) to P0 (LSB).
I
One of the 16 steps from step 0 (P3=P2=P1=P0="L") to step 15(P3=P2=
P1=P0="H") can be set.
5/21
FEDL6722-05
OKI Semiconductor
MSM6722
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power-supply voltage
VDD
Ta = 25°C
–0.3 to +7.0
V
Input voltage
VIN
Ta = 25°C
–0.3 to VDD + 0.3
V
Storage temperature
TSTG
—
–55 to +150
°C
Range
Unit
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Power-supply voltage
VDD
DGND = AGND = 0 V
4.5 to 5.5
V
Operating temperature
Top
—
–10 to +70
°C
Master clock frequency
fOSC
—
4 to 4.5
MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = –10 to +70°C, DVDD = AVDD = 4.5 V to 5.5 V, DGND = AGND = 0 V)
Symbol
Condition
Min
Typ
"H" input voltage
VIH
—
0.8 x VDD
"L" input voltage
VIL
—
—
Parameter
Max
Unit
—
—
V
—
0.2 x VDD
V
10
mA
"H" input current
*1
IIH1
VIH = VDD
—
—
"H" input current
*2
IIH2
VIH = VDD
—
—
20
mA
"H" input current
*4
IIH3
VIH = VDD
20
—
650
mA
"L" input current
*3
IIL1
VIL = GND
–10
—
—
mA
"L" input current
*2
IIL2
VIL = GND
–20
—
—
mA
Operating current consumption
(1)
IDD
fOSC = 4 MHz, no load
—
6
12
mA
—
—
10
mA
—
—
50
mA
At power down, no load
Operating current consumption
(2)
IPD
Ta=–40 to +70°C
At power down, no load
Ta=–40 to +85°C
*1 Applies to all input pins excluding the XT pin.
*2 Applies to the XT pin.
*3 Applies to all the input pins without pull-down resistors, excluding the XT pin (i.e., pins 1,
5-7, 10, 14, 16, 21; however pin 1 is applied only during UP/DOWN mode).
*4 Applies to the input pins with pull-down resistors, excluding the XT pin (i.e., pins 1, 2, 3, 4;
however, pin 1 is applied only during BINARY mode).
6/21
FEDL6722-05
OKI Semiconductor
MSM6722
Analog Characteristics
(Ta = –10 to +70°C, DVDD = AVDD = 4.5 V to 5.5 V, DGND = AGND = 0 V)
Symbol
Condition
Min
Typ
Max
Unit
DA output relative error
| VDAE |
No load
—
—
40
mV
AD output relative error
Parameter
| VADE |
No load
—
—
40
mV
SCF allowable input voltage
range
VFIN
—
1
—
VDD–1
V
SCF input impedance
RFIN
—
1
—
—
MW
OP amplifier open loop gain
GOP
fIN = 0 to 4 kHz
40
—
—
dB
OP amplifier input impedance
RINA
—
1
—
—
MW
OP amplifier load resistance
ROUTA
—
200
—
—
kW
AOUT load resistance
RAOUT
—
50
—
—
kW
AC Characteristics
(Ta = –10 to +70°C, fOSC = 4 MHz, DVDD = AVDD = 4.5 V to 5.5 V, DGND = AGND = 0 V)
Parameter
Symbol
Condition
Min
Max
Unit
DAO output delay from falling edge of PD
tPDD
fOSC = 4 MHz
—
16
ms
tUDPW
fOSC = 4 MHz
62
—
ms
tRUD
fOSC = 4 MHz
31
—
ms
tCHG1
fOSC = 4 MHz
62
—
ms
tCHG2
fOSC = 4 MHz
31
—
ms
Pulse width of PRST, UPC, and DWC
pulses
Time between UPC and DWC pulses
Pitch change delay from rising edge of
PRST
Pitch change delay from rising edge of
UPC and DWC
7/21
FEDL6722-05
OKI Semiconductor
MSM6722
TIMING DIAGRAM
PD(I)
tPDD
1/2 AVDD
DAO(O)
tUDPW
PRST(I)
tUDPW
tRUD
UPC(I)
DWC(I)
tCHG1
Pitch change
timing
tCHG2
Pitch step is 8 ("no pitch
change" state) by PRST
Raise/lower a pitch by one step
(pitch steps 0 to 15)
8/21
FEDL6722-05
OKI Semiconductor
MSM6722
FUNCTIONAL DESCRIPTION
Power Supply Wiring
As shown in the diagram below, supply the power to this IC from the same power source, but
separate the wiring for the analog and the logic sections.
To improve the electrical characteristics, insert a bypass capacitor of 0.1 mF or more between
DVDD and DGND and between AVDD and AGND.
+5 V
DVDD
AVDD
MSM6722
DGND
AGND
Do not supply the power to the analog section and the logic section from separate power sources;
otherwise latch-up may occur.
No good
No good
Analog power supply
+5 V
Digital power supply
DVDD
AVDD
DVDD
AVDD
9/21
FEDL6722-05
OKI Semiconductor
MSM6722
Connecting an Oscillator
Connect ceramic or crystal oscillators to the XT and XT pins as shown below.
The characteristics of recommended ceramic oscillators of MURATA MFG. and KYOCERA
CORPORATION are shown below for reference.
MSM6722
XT
XT
C1
Ceramic oscillator
KYOCERA
CORPORATION
MURATA MFG.
Maker
C2
Optimal load Capacity
Supply voltage Operating
temperature
range(V)
range(°C)
Type
Frequency
(MHz)
C1(pF)
C2(pF)
CSTLS4M00G53-B0
(with capacitor)
CSTCR4M00G53-R0
(with capacitor)
4.0
—
—
4.5 to 5.5
–10 to +70
KBR-4.0MSA
KBR-4.0MKS
PBRC4.00B
4.0
33
33
4.5 to 5.5
–10 to +70
10/21
FEDL6722-05
OKI Semiconductor
MSM6722
Analog Input Amplifier Circuit
The MSM6722 has two built-in operational amplifiers for amplifying the microphone output.
Each output amplifier is provided with an inverting input pin and output pin. The analog circuit
reference voltage SG (signal ground) is connected internally to the non-inverting input of each
output amplifier. For amplification, form an inverting amplifier circuit and adjust the amplification ratio by using external resistors, as shown below.
VIN
–
+
VMO
R1
VLO
R3
R2
MIN
MOUT
VLO
LIN
–
+
R4
LOUT
–
OP amplifier 1
+
OP amplifier 2
SG
VLO =
R4
R3
VMO =
R2 • R4
R1 • R3
VDD
VDD–1
1/2 VDD
1
GND
VIN (V)
The output VLO of output amplifier 2 is connected to the input FIN of the built-in LPF. The FIN
allowable input voltage (VFIN) ranges from 1 V to (VDD–1) V. Therefore, the amplification ratio
must be adjusted so that the VLO amplitude can be within the FIN allowable input voltage range.
For example, if VDD = 5 V, VLO becomes 3 Vp-p max. If VLO exceeds the FIN allowable input
voltage range, the output of the LPF will be a clipped waveform. The load resistance ROUTA of
the OP amplifier is 200 kW or more. Therefore, the feedback resistors R2 and R4 of the inverting
amplifier circuit must be 200 kW or more.
11/21
FEDL6722-05
OKI Semiconductor
MSM6722
Analog Input Amplifer Circuit
The output VLO of OP amplifer 2 is connected to the input FIN of the built-in LPF.
The allowable FIN input voltage VFIN ranges from 1 V to (VDD – 1) V.
Therefore, the amplification factor must be adjusted so that the VFIN amplitude can be within the
allowable FIN input voltage range. For example, if VDD = 5 V, VLO becomes 3 VP–P max.
If VLO exceeds the allowable FIN input voltage range, the output of the LPF will be a clipped
waveform. The load resistance ROUTA of the OP amplifier is 200 kW or more.
Therefore, the feedback resistors R2 and R4 must be 200 kW or more.
When OP amplifier 1 is not used and OP amplifier 2 is used, the MIN pin must be connected to
AGND or AVDD, and the MOUT pin must be open.
Even if amplification is unnecessary, OP amplifier 2 must be always used.
Below is an example of an analog input amplifier circuit when the amplification factor is 1.
Input signal
(200kW)
R3
(200kW)
R4
AGND
MIN
MOUT
–
+
SG
OP amplifier 1
LIN
LOUT
–
+
OP amplifier 2
MSM6722
12/21
FEDL6722-05
OKI Semiconductor
MSM6722
Configuring SGC and SG pins
The internal equivalent circuit around the SGC and SG pins is shown below.
AVDD
MSM6722
50kW
(TYP)
+
–
SGC
50kW
(TYP)
AGND
To OP amplifier LPF
SG
20kW
(TYP)
AGND
Power-down signal
Switch is open
during power-down
mode
AGND
The SG signal is reference voltage (signal ground) for internal OP amplifiers and LPF.
Install a capacitor between the SGC pin and AGND and between the SG pin and AGND
respectively in order to make the SG signal noiseless. It is recommended to install an approx.
1m capacitor, which should be determined after evaluating the tone quality.
It takes several ten msec until the DC levels such as the SG level of the analog circuit is stabilized
after the power-down mode is cancelled. The larger capacitance of a capacitor connected to SGC
or SG requires the longer time for stabilizing.
After the power-down mode is cancelled, enter voices after the DC levels for the analog circuit
has been stabilized.
When the device is in power-down mode, the output voltage of the SG pin becomes unstable.
Therefore, SG must not be supplied to external circuits.
Otherwise, power suppluy current may be leaked via the internal SG circuit.
Same is true for the SGC pin.
13/21
FEDL6722-05
OKI Semiconductor
MSM6722
Pitch-Control Circuit
[BINARY mode] (P3, P2, P1, P0)
As shown in the diagram below, this IC has an internal prevention circuit for approximately 62
ms of chattering . Therefore, hold these pins at "H" level for 62 ms or more. P3, P2, P1, and P0 pins
are used to directly set the pitch steps.
Sixteen pitch steps are provided, but step 16 cannot be set.
[UP/DOWN mode] (UPC, DWC, PRST)
As shown in the diagram below, this IC has an internal prevention circuit for approximately 62
ms of chattering . Therefore, hold these pins at "H" level for 62 ms or more.
[BINARY mode]
P3
Valid
data
P2
P1
Chattering
prevention
circuit
To pitch register
Chattering
prevention
circuit
To pitch register
P0
[UP/DOWN mode]
UPC
Pulse
input
DWC
PRST
Pitch-Control Circuit
Inputting a "H" level pulse to the UPC pin raises the pitch by one step, and inputting a "H" level
pulse to the DWC pin lowers the pitch by one step. Inputting a "H" level pulse to the PRST pin
or to the UPC and DWC pins at the same time sets the no-pitch change state (pitch step 8).
14/21
FEDL6722-05
OKI Semiconductor
MSM6722
A pitch shifts in a range of about one octave upward or downward, centered at pitch step 8. The
pitch shift is illustrated in the following keyboard diagram and the following table via corresponding frequencies.
Pitch Conversion Diagram
0
1
5
2
3
4
9
6
7
8
10
14
11
12
13
15
16
Pitch Conversion Table
Pitch step
DA sampling cycle (µs)/
frequency (kHz)
16
60/16.6
15
71/14.0
14
76/13.1
13
80/12.5
12
90/11.1
11
90/10.5
10
101/9.90
9
113/8.84
8
120/8.33
7
127/7.87
6
143/6.99
5
151/6.62
4
160/6.25
3
180/5.55
2
190/5.26
1
202/4.95
0
227/4.40
15/21
PRST
UPC (P2)
XT
DWC (P1)
XT
PRST (P0)
RESET
MS
DGND
THR/CHG
30 pF
DVDD
SG
TEST
AGND
DAO
SGC
AOUT
MIN
ADIN
MOUT
FOUT
LIN
AVDD
LOUT
4.0 MHz
100 kW
RST
OKI Semiconductor
PD (P3)
APPLICATION CIRCUITS
0.1 mF
MSM6722
DW
UP/DOWN Mode
UP
30 pF
+
1 mF
+
1 mF
10 kW
51 pF
+
0.47 mF
100 kW
0.1 mF
0.4 mF
10 kW
51 pF
330 kW
16/21
FEDL6722-05
SP
MSM6722
Speaker drive amplifier
MSC1157
XT
DWC (P1)
XT
PRST (P0)
RESET
MS
DGND
THR/CHG
30 pF
DVDD
UPC (P2)
SG
TEST
AGND
DAO
SGC
AOUT
MIN
ADIN
MOUT
FOUT
LIN
AVDD
LOUT
OKI Semiconductor
PD (P3)
HEX switch
BINARY Mode
0.1 mF
MSM6722
4.0 MHz
100 kW
RST
30 pF
+
1 mF
+
1 mF
10 kW
51 pF
+
0.47 mF
100 kW
0.1 mF
0.4 mF
10 kW
51 pF
330 kW
17/21
FEDL6722-05
SP
MSM6722
Speaker drive amplifier
MSC1157
FEDL6722-05
OKI Semiconductor
MSM6722
PAD CONFIGURATION
Pad Layout (Top View)
View from the side cofiguring the pads
Chip Size
Chip Thickness
Pad Size
Chip Substrate Voltage
:
:
:
:
3.99 mm ¥ 3.08 mm
350 mm ±30 mm
110 mm ¥ 110 mm
VDD
Y
21
20
19
18
17
16
22
15
23
14
13
24
X
12
1
11
2
10
3
5
4
6
7
8
9
Pad Coordinates
(Chip center is located at X=0 and Y=0.)
Pad No
PAD name
X (mm)
Y (mm)
Pad No
PAD Name
X (mm)
Y (mm)
1
PD
–1784
–602
13
LOUT
1782
356
2
UPC
–1784
–955
14
LIN
1782
780
3
DWC
–1784
–1310
15
MOUT
1782
1193
4
PRST
–1314
–1391
16
MIN
1351
1359
5
MS
–736
–1397
17
SGC
938
1359
6
THR/CHG
–275
–1397
18
AGND
598
1295
7
TEST
53
–1397
19
SG
–127
1359
8
DAO
912
–1396
20
DGND
–650
1359
9
AOUT
1447
–1396
21
RESET
–1198
1359
10
ADIN
1783
–974
22
XT
–1787
1053
11
FOUT
1783
–561
23
XT
–1786
703
12
AVDD
1733
–238
24
DVDD
–1736
84
18/21
FEDL6722-05
OKI Semiconductor
MSM6722
PACKAGE DIMENSIONS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
0.58 TYP.
5/Oct. 13, 1998
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/21
FEDL6722-05
OKI Semiconductor
MSM6722
REVISION HISTORY
Page
Document
No.
Date
FEDL6722-04
Jul. 2001
FEDL6722-05
Feb. 27, 2002
Description
Previous Current
Edition Edition
—
—
Fourth edition
9
10
Changed contents of the table for ceramic
oscillators
—
20
Addition of Revision History
20/21
FEDL6722-05
OKI Semiconductor
MSM6722
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
Printed in Japan
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