TOSHIBA TC94A39FAG/FB

TC94A39FAG/FB
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A39FAG, TC94A39FB
Single-Chip CD Processor with Built-in Controller (CD-DX)
The TC94A39FAG/FB is a single-chip CD processor for digital
servo, which incorporates a 4-bit microcontroller.
The controller features an LCD driver, 4-channel 6-bit AD
converter, 1 port 2-channel 2/3-line or UART serial interface
module, a buzzer, 20-bit general-purpose counter function,
interrupt function, and 8-bit timer/counter. The CPU can select
one of four operating clocks (16.9344-MHz, 75-kHz or 32.768-kHz
crystal oscillator and CR oscillator), facilitating interface with the
CD processor.
The CD processor incorporates sync separation protection and
interpolation, EFM demodulator, error correction, digital
equalizer for servo, and servo controller. The CD processor also
incorporates a 1-bit DA converter. In combination with the
TA2157F/FN digital servo head amplifier, the TC94A39FAG/FB
can very simply configure an adjustment-free CD player.
Thus, the IC is suitable for CD systems for automobiles and
radio-cassette players.
TC94A39FAG
TC94A39FB
Features
·
Single-chip CD processor with on-chip CMOS LCD driver and
4-bit microcontroller
·
Operating supply voltage:
CD in operation: VDD = 3.0 to 3.6 V (3.3 V typ.)
CD stopped: VDD = 1.8 to 3.6 V (only CPU in operation)
·
Weight
LQFP64-P-1010-0.50: 0.32 g (typ.)
QFP64-P-1212-0.65: 0.45 g (typ.)
Supply current:
CD in operation: IDD = 30 mA (typ.)
CD stopped: IDD = 1.5 mA (CD standby mode, with 16.9344-MHz crystal oscillator, CPU in operation)
CD stopped: IDD = 50 µA (CD standby mode, with 75-kHz crystal oscillator, CPU in operation)
·
Operating temperature range: Ta = −40 to 85°C
·
Package: LQFP/QFP-64 (0.5/0.65-mm pitch, 1.4 mm thick)
·
E2PROM: TC94AE29FAG/FB
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TC94A39FAG/FB
4-bit Microcontroller
· Program memory (ROM): 16 bits ´ 8 Ksteps
· Data memory (RAM): 4 bits ´ 512 words
· Instruction execution time: 1.42 ms, 40 ms, 91.6 ms, TOSC ´ 3 (Every instruction consists of a single word.)
· Crystal oscillator frequency: 16.9344 MHz, 75 kHz, 32.768 kHz, CR oscillation frequency
· Stack levels: 6
· AD converter: 6 bits ´ 4 channels
· LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 64 segments (max.)
· I/O ports: CMOS I/O ports: 26 (max.)
N-channel open-drain I/O ports (for up to 5.5 V): 3 (max.)
· Timer/counter: 8 bits (timer mode, pulse width detector and measure function)
· General-purpose counter: 20 bits, 0.1 MHz to 20 MHz, Vin = 0.2 Vpp (min.), input amplifier incorporated
· Serial interface module: 1 port 2 channel supporting 2/3-line method or UART
(two input channels)
· Four buzzer types: 0.75 kHz, 1 kHz, 1.5 kHz, and 3 kHz
· Four modes: continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz intervals
· Interrupts: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer)
· Back-up mode: Four types: CD standby (CD processor stopped)
Clock stop (oscillator stopped)
Hardware wait (only crystal oscillator in operation)
Software wait (CPU in intermittent operation)
· Reset function: Power-on reset circuit, supply voltage detector (detection voltage = 1.5 V typ.)
CD Processor
· Reliable sync pattern detection, sync signal protection and interpolation
· Built-in EFM demodulator and subcode decoder
· High-correction capability using Cross Interleave Read Solomon Code (CIRC) logical equation
C1 correction: dual
C2 correction: quadruple
· Jitter absorption capability of ± 6 frames
· Built-in 16 KB RAM
· Built-in digital output circuit
· Built-in L/R independent digital attenuator
· Bilingual audio output
· Audio output: 32fs, 48fs or 64fs selectable
· Subcode Q data is read-timing free and can be driven out in sync with audio data.
· Built-in data slicer and analog PLL (adjustment-free VCO used) circuit
· Automatic adjustment of loop gain, offset, and balance at focus servo and tracking servo
· Built-in RF gain auto-adjusting circuit
· Built-in digital equalizer for phase compensation
· Supports different pickups using on-chip digital equalizer coefficient RAM.
· Built-in focus and tracking servo control circuit
· Search control supports all modes and realizes high-speed, stable search.
· Lens kick and feed kick use speed control method.
· Built-in AFC and APC circuits for disc motor CLV servo
· Built-in defect/shock detector
· Built-in 8 times over-sampling digital filter and 1-bit DA converter
· Built-in analog filter for 1-bit DA converter
· Built-in zero-data detection output circuit
· Supports double-speed operation.
Note:
Output pins for subcode Q data and audio data have multiplexed functions for controller-dedicated pins. The
function of each pin can be switched by program.
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TC94A39FAG/FB
DVR
LO
DVSS
RO
DVDD
CVSS
XI
XO
CVDD
DMO
FMO
SEL
TEBC
RFGC
TRO
FOO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RESET
49
1-bit DAC
P8-0/MXI/OSC (BRK1)
50
P8-1/MXO (BRK2)
51
75-kHz /
32.768-kHz/CR
P2-0/COM1
52
P2-1/COM2
53
P2-2/COM3
54
P2-3/COM4
55
TEST/P3-0/S1
56
P3-1/S2
57
P3-2/S3
58
P3-3/S4
59
P4-0/S5
60
P4-1/S6
61
P4-2/S7
62
P4-3/S8
63
P5-0/S9
64
CD processor-dedicated control input/output pins
LCD driver (4 ´ 16 = 64 segments max.)
16.9344-MHz
oscillator
LQFP/QFP-64
(0.5/0.65-mm pitch)
Top view
AD converter
Serial interface 1
6
7
8
9
10
11
12
13
P6-2/S15/ADin3/SBOK (BRK8)
P6-3/S16/ADin4/CLCK (BRK9)
MVDD
MVSS
P1-0/SCK1/RX1/CTin/DATA (BRK10)
P1-1/SDIO1/TX1/SFSY (BRK11)
P1-2/SI1/SBSY (BRK12)
P1-3/BUZR (BRK13)
Pull-up/pull-down can be specified.
14
15
32
TEZI
31
TEI
30
SBAD
29
FEI
28
RFRP
27
RFZI
26
VREF
25
AVDD
24
RFI
23
SLCO
22
AVSS
21
VCOF
20
LPFO
19
LPFN
18
TMAX
17
PDO
16
P7-2/INTR/SI2 (BRK16)
5
P7-1/SDIO2/TX2 (BRK15)
4
P6-1/S14/ADin2/IPF (BRK7)
P5-2/S11/LRCK (BRK4)
3
P6-0/S13/ADin1/DOUT (BRK6)
2
P5-3/S12/AOUT (BRK5)
1
P5-1/S10/BCK (BRK3)
Controller-dedicated pins
P7-0/SCK2/RX2 (BRK14)
Reset input
Test mode input
Pull-up/pull-down can be specified.
Pin Connections
CMOS I/O ports (up to 26 ports)
3
Buzzer output
Note: The TEST pin (pin 56) is pulled down during a reset, thus accepting
test mode input. Therefore, it should be applied low or left open
during a reset.
Frequency counter input
Note: For BRK1 to BRK16, the backup state can be set to be released in
port units.
Interrupt input
N-ch open-drain I/O
(3 pins, 5.5 V max.)
Serial interface 2
Also used for CD function
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TC94A39FAG/FB
AVSS
AVDD
RFZI
RFRP
FEI
SBAD
TEI
TEZI
FOO
TRO
VREF
RFGC
TEBC
FMO
SEL
DMO
Block Diagram
VREF
VREF
Clock gene.
PWM
XI
Crystal
OSC
XO
DA
VREF
CD clock
ZDET
SLCO
TMAX
PLL
TMAX
Servo
control
DVDD
RFI
Data
slicer
PDO
AD
VREF
LPF
1-bit DAC
RO
DVSS
LO
VCOF
ROM
Digital equalizer
RAM
Automatic adjustment
circuit
DVR
VCO
VREF
CLV
servo
LPFO
Synchronous
guarantee EFM
decoder
Sub code decoder
VREF
Audio out
16-k SRAM
Digital out
CVSS
CD Reset
MPX
Address
CVDD
LPFN
Correction circuit
Microcontroller interface
Reset
SBSY
CPU clock
BCK, LRCK, AOUT, DOUT
IPF, SBOK, CLCK, DATA, SFSY
CR
OSC
P8-0/MX1/OSC (BRK1)
Crystal
OSC
P8-1/MXO (BRK2)
Data Reg (16 bits)
G-Reg.
R/W Buf.
Port 8
Mask ROM
(16 ´ 8192 Steps)
Timer
SBSY
INTR
ALU
RAM
(4 ´ 512 words)
Interrupt
cont.
F/F
Serial
interface
(SIO)
Reset
Instruction
Decoder
Program
Counter
RESET
Power on Reset
P7-0/SCK2/RX2 (BRK14)
P7-1/SDIO2/TX2 (BRK15)
MVDD
Stack Reg.
(16 Levels)
Port 7
MVSS
P7-2/INTR/SI2 (BRK16)
AD
conv.
BCK, LRCK, AOUT, DOUT, IPF, SBOK,
CLCK, DATA, SFSY, SBSY
20-bit
counter
4
Buzzer
SIO
P1-3/BUZR (BRK13)
P1-2/SI1/SBSY (BRK12)
P1-0/SCK1/RX1/CTin/DATA (BRK10)
P6-3/S16/ADin4/CLCK (BRK9)
P6-2/S15/ADin3/SBOK (BRK8)
P6-1/S14/ADin2/IPF (BRK7)
P6-0/S13/ADin1/DOUT (BRK6)
Port 1
P5-3/S12/AOUT (BRK5)
P5-2/S11/LRCK (BRK4)
P5-1/S10/BCK (BRK3)
P5-0/S9
P3-1/S2
TEST/P3-0/S1
P2-3/COM4
P2-2/COM3
P2-1/COM2
P2-0/COM1
LCD Driver/IO Port 2, 3, 4, 5, 6
P1-1/SDIO1/TX1/SFSY (BRK11)
Bias
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TC94A39FAG/FB
Pin Functions
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
System reset input pin for the device.
49
RESET
Reset input
A reset is applied while the RESET signal is low.
When it is high, the 16.9344-MHz crystal
oscillator (XI, XO) starts operating. The
controller counts clock pulses from this oscillator
and waits a specified standby time
(approximately 50 ms) before starting the
controller program from address 0. The CD
processor is placed in the standby state at this
time.
MVDD
MVSS
Normally, raising the voltage on MVDD from 0
to 1.8 V or higher triggers a system reset
(power-on reset) so that the RESET pin should
be held at high.
MVDD
2-bit CMOS I/O port.
Input/output can be specified for each bit. When
the pins are used as I/O port input, each pin can
be pulled up or down by program. When backup
release for clock stop mode or wait mode is
enabled for the pins, a change in a pin can
release the backup state.
50
51
P8-0
/MXI
/OSC
(BRK1)
P8-1
/MXO
(BRK2)
I/O port 8-0
/crystal oscillator
/CR oscillator
I/O port 8-1
/crystal oscillator
The program can set these pins to be used for a
75-kHz or 32.768-kHz dedicated crystal
oscillator. The P8-0 pin can also be used for a
CR oscillator. These clocks are used for the
operation of the controller and peripheral
devices. Upon a system reset, the 16.9344-MHz
crystal oscillator (XI, XO) is selected as the
clock for controller and peripheral device
operation. The program can subsequently set
the pins to oscillator pins and switch the clock
generated from the oscillator to the controller
clock. When the pins are used for an oscillator,
executing the CKSTP instruction causes its
oscillation to stop.
(Note) When the P8-0 pin is used for a CR
oscillator, the P8-1 pin can used as an
I/O port pin.
MVDD
Input
instructio
RIN1
MVDD
MVSS
(When used for I/O port)
Rout2
RfXT2
MXO
MVDD
MXI
MVSS
(Note) Backup release is enabled for both pins (When used for crystal oscillator)
simultaneously.
(Note) Use a crystal oscillator having a good
startup characteristic.
MVDD
(Note) Upon a system reset, the pins are set to
I/O port input.
MVDD
(Note) After setting the pins to oscillator pins,
wait until oscillation settles before
switching the controller clock.
OSC
R
C
MVSS
(When P8-0 is used
for CR oscillator)
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TC94A39FAG/FB
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
24-bit CMOS I/O port and 3-bit N-channel
open-drain I/O port.
52
P2-0/COM1
53
P2-1/COM2
54
P2-2/COM3
55
P2-3/COM4
Input/output can be specified for each bit. When
the P6-0 to P6-3 pins are used as I/O port input,
each pin can be pulled up or down by program.
When the P5-1 (BRK3) to P7-2 (BRK16) pins
I/O port 2
are used as I/O port input and backup release
/LCD common output
for clock stop mode or wait mode is enabled for
those pins (enabled/disabled in port units), a
change in any of the pins can release the
backup state. The P7-0 to P7-2 pins constitute
an N-channel open-drain I/O port, to which a
voltage of up to 5.5 V can be applied.
LCD
voltage
MVDD
MVDD
Input
instruction
I/O ports 2 to 6 can be set to LCD driver output
pins by program. The COM1 to COM4 pins
drive common signals to the LCD panel while
the S1 to S16 pins drive segment signals. The
COM1 to COM4 signals configure a matrix with
the S1 to S16 signals to display up to 64
segments.
56
TEST
/P3-0/S1
57
P3-1/S2
58
P3-2/S3
59
P3-3/S4
60
P4-0/S5
61
P4-1/S6
62
P4-2/S7
63
P4-3/S8
LCD
voltage
MVDD
When the LCDoff bit is set to 0, the COM1 to
COM4 and S1 to S4 pins are collectively set to
LCD output. For S5 to S16, the program can
specify either I/O port or segment output
individually for each pin.
Test input
/I/O port 3-0
The LCD can be driven by the 1/4-duty, 1/2-bias
/LCD segment output
method (frame frequency: 62.5 Hz) or the
1/4-duty, 1/3-bias method (frame frequency: 125
Input
Hz). When the 1/2 bias method is set, three
instruction
common output levels (MVDD, 1/2MVDD and
RIN2
GND) and two segment output levels (MVDD
and GND) appear on the pins. When the 1/3
bias method is set, four common and segment
output levels (MVDD, 1/3MVDD, 2/3MVDD and
GND) appear on the pins.
I/O port 3
/LCD segment output
Upon a system reset or after clock stop mode is
released, a non-select waveform (bias voltage)
is driven and the DISP OFF bit is set to 0, after
which the common signals are driven.
During a system reset ( RESET = low), the
TEST/P3-0/S1 pin is pulled down and accepts
test mode input. This pin should be left open or
applied low level during a reset.
The P5-1 to P6-3 and P1-0 to P1-2 pins can be
set to CD processor-dedicated pins on a per pin
basis. The CD processor functions are as
I/O port 4
/LCD segment output follows:
MVDD
Reset signal
MVSS
LCD
voltage
MVDD
MVDD
Input
(Continued on next page) instruction
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2003-04-01
TC94A39FAG/FB
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
●BCK: Bit clock output pin. One of three
frequencies, 32, 48 or 64 can be
specified using a CD command.
LCD
voltage
At normal speed: 32 fs = 1.4112 MHz
64
P5-0/S9
MVDD
●LRCK: LR channel clock output pin. For the L
channel, this pin drives a low level. For
the R channel, it drives a high level.
I/O port 5-0
The polarity can be inverted using a
/LCD segment output
CD command.
At normal speed: 44.1 kHz
●AOUT: Audio data output pin. Either MSB first
or LSB first can be specified using a
Input
CD command.
instruction
MVDD
●DOUT: Digital data output pin. It drives data at
up to double speed (complying with
CP-1201).
●IPF:
1
P5-1/S10
/BCK
(BRK3)
2
P5-2/S11
/LRCK
(BRK4)
3
P5-3/S12
/AOUT
(BRK5)
LCD
voltage
Correction flag output pin. If the AOUT
output is C2 error detection/correction,
a high level appears to indicate an
uncorrectable symbol. (Also called
C2PO)
MVDD
I/O port 5
/LCD segment output ●SBOK: CRCC test result output pin for
subcode Q data. A high level appears
/CD processor
when the data has passed the test.
function
●CLCK: Clock input/output pin for reading
subcode P to W data. The input/output
Input
polarity can be inverted using a CD
instruction
command.
Release
enable
●DATA: Subcode P to W data output pin.
MVDD
●SFSY: Frame sync signal output pin for
playback.
4
5
6
7
●SBSY: Block sync signal output pin for
subcode. When a subcode sync is
detected, a high level appears at S1.
The controller enables CD interrupts.
When an interrupt occurs on the falling
edge of the SBSY signal, the program
jumps to address 2.
P6-0/S13
/ADin1
/DOUT
(BRK6)
P6-1/S14
/ADin2
/IPF
(BRK7)
P6-2/S15
/ADin3
/SBOK
(BRK8)
P6-3/S16
/ADin4
/CLCK
(BRK9)
AD input
LCD
voltage
MVDD
(Note) Interrupts should not be enabled when
CD processor operation is undefined.
I/O port 6
/LCD segment output
/CD processor
function
P6-0 to P6-3 pins have multiplexed functions for
the on-chip 6-bit 4-channel AD converter analog
input. The on-chip AD converter uses
Input
successive approximation. The conversion time
instruction
is 242 ms when the 16.9344-MHz crystal
Release
oscillator is used and 7 instruction cycles
enable
(280 ms) when the 75-kHz crystal oscillator is
RIN1
used. The program can specify necessary pins
for AD analog input on a per bit basis. The
internal power supply (MVDD) is used as the
reference voltage. When the P6-0 to P6-3 pins
are used as I/O port input, each pin can be
MVDD
pulled up or down by program.
MVDD
MVSS
(Continued on next page)
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2003-04-01
TC94A39FAG/FB
Pin
No.
Symbol
Pin Name
Function and Operation
10
P1-0/SCK1
/RX1
/CTin
/DATA
(BRK10)
I/O port 1-0
/serial clock
input/output 1
/serial receive data 1
/counter clock input
/CD processor
function
11
P1-1/SDIO1
/TX1
/SFSY
(BRK11)
The P1-0 pin has multiplexed functions for
general-purpose counter input. The input
frequency is 0.1 MHz to 20 MHz. The counter
incorporates an input amplifier and operates
with capacitance-coupled small amplitudes. The
counter is a 20-bit counter and can store 20-bit
data directly in memory. The gate time can be
selected from among 1 ms, 4 ms, 16 ms and 64
ms (when the 75-kHz crystal oscillator is used).
In manual mode, the gate can be turned on and
off within the specified time using instructions.
12
P1-2/SI1
/SBSY
(BRK12)
13
P1-3/BUZR
(BRK13)
14
P7-0/SCK2
/RX2
(BRK14)
15
P7-1/SDIO2
/TX2
(BRK15)
16
P7-2/INTR
/SI2
(BRK16)
I/O port 1-1
/serial data
input/output 1
/serial transmit data 1
The P1-0 to P1-2 and P7-0 to P7-2 pins have
/CD processor
multiplexed functions for serial interface (SIO)
function
circuit input/output pins.
I/O port 1-2
The SIO is a serial interface supporting 2-line
/serial data input 1
and 3-line methods as well as UART. The
/CD processor
TC94A39FAG/FB has CMOS input/output pins
function
(SCK1/RX1, SDIO1/TX1, SI1) and N-channel
open-drain (supporting up to 5.5 V) input/output
pins (SCK2/RX2, SDIO2/TX2, SI2). One of the
two sets of pins can be selected as serial
interface. The serial interface circuit supports
various options, including the number of the
I/O port 1-3
clock edge to be used, the serial clock
/buzzer output
input/output, and the clock frequency. These
options facilitate controlling the LSI and
communications between the controllers. When
SIO interrupts are enabled, an interrupt is
generated as soon as execution of the SIO
completes, causing the program to jump to
I/O port 7-0
address 4.
/serial clock
The P1-3 pin has multiplexed functions for a
input/output 2
/serial receive data 2 buzzer output pin. One of four frequencies
within the range from 0.75 kHz, 1 kHz, 1.5 kHz
I/O port 7-1
and 3 kHz can be selected for buzzer output
/serial data
(when the 75-kHz clock is used). The buzzer is
input/output 2
driven at the selected frequency in one of four
/serial transmit data 2 modes: continuous, single-shot, 10-Hz
intermittent, and 10-Hz intermittent at 1-Hz
intervals.
I/O port 7-2
/interrupt input
/serial data input 2
Remarks
MVDD
MVSS
MVDD
Input
instruction
Release
enable
(When used for I/O port)
RfIN
MVDD
CTin
MVSS
(When P1-0 is used for
general-purpose counter)
The P7-2 pin has multiplexed functions for an
external interrupt input pin. When interrupts are
enabled and a pulse of 1.65 ms to 4.96 ms or
more (13.3 ms to 40 ms when the 75-kHz clock is
Input
instruction
used) is applied to this pin, an interrupt is
Release
generated and the program jumps to address 1.
enable
The input logic and rising/falling edge can be
selected for interrupt inputs. This input can be
applied as the clock gate signal to the internal
8-bit timer/counter, which allows input pulse
width to be detected and measured.
MVSS
MVDD
(Note) Backup release is enabled or disabled
in port units.
(Note) Upon a system reset, the pins are set to
I/O port input.
(Note) When the 32.768-kHz crystal oscillator
or the CR oscillator is used, the
general-purpose counter is used as a
timer.
8
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TC94A39FAG/FB
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
Power supply pins for the controller block.
8
Normally, VDD = 3.0 to 3.6 V.
When only the CPU operates (when the
75-kHz/32.768-kHz oscillator is used), it can
operate at
VDD = 1.8 to 3.6 V.
MVDD
MVDD
In the backup state (when the CKSTP
instruction is executed), current dissipation
decreases (10 mA or below), allowing the power
Power supply pins for supply voltage to be reduced to 1.0 V.
controller block
Raising the voltage on MVDD pin from 0 V to
1.8 V or higher triggers a system reset, causing
the program to start from address 0 (power-on
reset).
9
MVSS
MVSS
(Note) At power-on reset operation, allow 1 ms
to 50 ms while the device power supply
voltage rises.
(Note) The backup current is the total of
currents for CVDD, MVDD and DVDD.
AVDD
Output pin for a phase error signal between the
EFM and PLCK signals.
17
PDO
Rout4
Drives one of four values: AVDD, Hi-Z,
VREF, AVSS
AVSS
VREF
AVDD
TMAX detection result output pin.
18
19
TMAX
LPFN
CD processor control
input/output pin
Longer than specified cycle: Drives a high
level (AVDD)
Shorter than specified cycle: Drives a low
level (AVSS)
Within specified cycle: Hi-Z
AVSS
Inverted input pin for PLL low-pass filter
amplifier.
AVDD
VREF
LPFN
20
LPFO
Output pin for PLL low-pass filter amplifier.
LPFO
VREF
VCO
21
VCOF
VCO filter pin
22
AVSS
Ground pin for analog block
VCOF
9
¾
2003-04-01
TC94A39FAG/FB
Pin
No.
Symbol
23
SLCO
Pin Name
Function and Operation
Remarks
Zin1
DAC output pin for generating data slice level.
VREF
RFI
AVDD
SLCO
24
RFI
RF signal input pin. The value of Zin1 can be
selected using a CD command.
25
AVDD
Power supply pin for analog block. Normally,
VDD = 3.0 to 3.6 V. In CD standby mode, turn
this power supply off.
¾
26
VREF
Analog reference voltage pin. Normally, a
voltage of 1/2 AVDD is supplied
(when VDD = 3.3 V, VREF = 1.65 V).
¾
DAC
AVDD
RFZI
27
RFZI
RFRP zero-cross signal input pin
Zin2
VREF
28
RFRP
1 kW typ. 32 kW typ.
CD processor control
input/output pin
RF ripple signal input pin
AVDD
RFRP
29
FEI
Focus error signal input pin
FEI
30
SBAD
31
TEI
Subbeam addition signal input pin
Tracking error input pin. The pin is read when
tracking servo is turned on.
SBAD
TEI
AVDD
TEZI
32
TEZI
Tracking error/zero-cross signal input pin
Zin2
VREF
33
FOO
Focus equalizer output pin
AVDD
Rout3
34
TRO
1 kW typ. 32 kW typ.
A VDD
to
AVSS
Tracking equalizer output pin
10
2003-04-01
TC94A39FAG/FB
Pin
No.
Symbol
35
RFGC
36
Pin Name
Function and Operation
Remarks
Control signal output pin for adjusting RF
amplitude. Drives three-level PWM signal
(PWM carrier = 88.2 kHz).
AVDD
Rout3
Tracking balance control signal output pin.
Drives three-level PWM signal
(PWM carrier = 88.2 kHz).
TEBC
VREF
AVDD
37
SEL
CD processor control APC circuit ON/OFF signal output pin. When
laser is turned on, this pin will be in a
input/output pin
high-impedance state.
38
FMO
Feed equalizer output pin. Drives three-level
PWM signal (PWM carrier = 88.2 kHz).
AVDD
Rout3
39
Disc equalizer output pin. Drives three-level
PWM signal (PWM carrier = 88.2 kHz).
DMO
VREF
CVDD
40
CVDD
Power supply pins
43
Logic power supply pins for the CD processor
block and 16.9344-MHz dedicated crystal
oscillator. Normally, the same power supply as
that for the MVDD and MVSS pins is connected.
In CD standby mode, current dissipation
decreases.
CVSS
CVSS
41
XO
Input/output pins for the CD
processor-dedicated crystal oscillator. Connect
a 16.9344-MHz crystal oscillator. This clock is
used as the CD processor system clock and
controller system clock. Upon a system reset,
this clock is supplied as the controller system
clock and starts the CPU.
The crystal oscillator can be stopped by
Crystal oscillator pins program. If the 75/32.768-kHz or CR oscillator is
selected as the controller system clock, the CD
processor oscillator is stopped by program
when the CD processor is turned off.
42
XI
Rout1
XO
RfXT1
CVDD
XI
CVSS
(Note) When switching the controller system
clock from the controller oscillator to the
CD crystal oscillator, make sure that the
CD crystal oscillator is sufficiently
stable.
11
2003-04-01
TC94A39FAG/FB
Pin
No.
Symbol
44
DVDD
Pin Name
Function and Operation
Remarks
DA converter block power supply pin
45
RO
46
DVSS
The TC94A39FAG/FB consumes less current in
CD standby mode.
R-channel data forward rotation output pin
Audio DAC output
DVDD
DVR
DVDD
DA converter block ground pin
RO/LO
47
LO
L-channel data forward rotation output pin
DVSS
48
DVR
VSS
Reference voltage pin
12
2003-04-01
TC94A39FAG/FB
Maximum Ratings (Ta = 25°C, CVDD = DVDD = AVDD = MVDD)
Characteristic
Symbol
Rating
Units
VDD
-0.3 to 4.0
V
CVDD pin
VIN1
-0.3 to CVDD + 0.3
AVDD pin
VIN2
-0.3 to AVDD + 0.3
DVDD pin
VIN3
-0.3 to DVDD + 0.3
MVDD pin
VIN4
-0.3 to MVDD + 0.3
VIN5
-0.3 to 6.0
Supply voltage
Input voltage
(Note 1)
TC94A39FAG
Power dissipation
TC94A39FB
V
400
PD
mW
500
Operating temperature
Topr
-40 to 85
°C
Storage temperature
Tstg
-65 to 150
°C
Note 1: VIN1; Pins 41 and 42
VIN2; Pins 17 to 39 (excluding power supply pins)
VIN3; Pins 45, 47 and 48
VIN4; Pins 1 to 13 and 49 to 64 (excluding power supply pins)
VIN5; Pins 14, 15 and 16
13
2003-04-01
TC94A39FAG/FB
Electrical Characteristics
(Ta = 25°C, CVDD = MVDD = DVDD = AVDD = 3.3 V, VREF = 1.65 V unless otherwise stated)
Parameter
Symbol
Test
Circuit
Min
Typ.
Max
3.0
~
3.6
CPU in operation (CD standby,
16.9344-MHz crystal oscillator/CR oscillator
used)
(Note 4)
3.0
~
3.6
Only CPU in operation (CD standby,
75-kHz/32.768-kHz crystal oscillator used)
(Note 5)
1.8
~
3.6
Crystal oscillator stopped (CKSTP
(Note 4)
instruction executed)
1.0
~
3.6
IDD1
CPU and CD in operation
(XI = 16.9344-MHz crystal oscillator used)
¾
30
50
IDD2
Only CPU in operation
(XI = 16.9344-MHz crystal oscillator used)
¾
1.5
¾
CPU in operation
(MXI = 75-kHz crystal oscillator connected)
¾
50
100
mA
IDD4
CPU in operation
(OSC = 0.5-MHz oscillation)
¾
2.0
¾
mA
IDD5
Standby mode
(only crystal oscillator in operation,
MXI = 75 kHz)
¾
40
80
mA
(CVDD/MVDD/AVDD/DVDD) Crystal
oscillator stopped
(CKSTP instruction executed)
¾
0.1
10
mA
(MXI-MXO) Crystal oscillator selected
(Note 3) (Note 5)
30
~
100
kHz
(XI-XO)
¾
16.9344
¾
(OSC) CR oscillator selected
0.01
~
0.75
CPU and CD in operation
MVDD = CVDD >
= DVDD = AVDD
VDD1
Operating supply voltage
range
VDD2
¾
VDD3
Memory hold voltage range
Operating power supply
current
MVHD
IDD3
¾
¾
(Note 2)
Memory hold current
MIHD
¾
fMXT
Oscillation frequency
fXT
Test Condition
¾
fOSC
Units
(Note 4)
(Note 4)
V
V
mA
MHz
Oscillating frequency error
DfOSC
¾
(OSC) CR oscillator selected
¾
¾
15
%
Crystal oscillator start time
tst
¾
(MXI-MXO)
Crystal oscillator fmxt = 75 kHz/32.768 kHz
¾
¾
1.0
s
Crystal oscillator amplifier
feedback resistance
RfXT1
(XI-XO)
0.5
1.0
2.0
(MXI-MXO)
¾
16
¾
0.25
0.5
1.0
50
100
200
1.4
1.5
1.6
V
¾
100
¾
mA
Crystal oscillator output
resistance
Dropout voltage detect
voltage
Dropout voltage detector
operating current
RfXT2
Rout1
Rout2
VDET
¾
¾
(XO)
MW
kW
(MXO)
¾
(MVDD) Dropout voltage detector enabled
IDD-VD
¾
Note 2: The operating power supply current includes the total current through all CVDD, MVDD, DVDD and AVDD
power supply pins.
Note 3: Design and specify constants according to the crystal oscillator to be connected.
Note 4: The values are guaranteed when CVDD = MVDD = DVDD = AVDD = 3.0 to 3.6 V, Ta = -40 to 85°C.
Note 5: The values are guaranteed when CVDD = MVDD = DVDD = AVDD = 1.8 to 3.6 V, Ta = -30 to 75°C.
14
2003-04-01
TC94A39FAG/FB
General-purpose counter (CTin)
Symbol
Test
Circuit
Frequency range
fCT
¾
Input amplitude range
VCT
¾
Operating power supply
current
IDD-CT
¾
General-purpose counter operating current,
fin = 20 MHz
Input amplifier feedback
resistance
RfIN
¾
(CTin)
Parameter
Test Condition
VIN = 0.2 VP-P
Min
Typ.
Max
Units
(Note 4)
0.1
¾
20
MHz
(Note 4)
0.2
¾
2.0
VP-P
¾
0.7
¾
mA
200
350
1000
kW
Note 4: The values are guaranteed when CVDD = MVDD = DVDD = AVDD = 3.0 to 3.6 V, Ta = -40 to 85°C.
LCD common and segment outputs (COM1 to COM4, S1 to S16)
Parameter
Output current
Bias current
Symbol
High level
IOH1
Low level
IOL1
1/2 level
VBS2
1/3 level
VBS1
2/3 level
LCD operating power supply
current
Test
Circuit
¾
¾
Test Condition
Min
Typ.
Max
VOH = 2.9 V (LCD output)
¾
-300
¾
VOL = 0.4 V (LCD output)
¾
450
¾
No load (common output, 1/2 bias method)
2.3
2.5
2.7
1.47
1.67
1.87
3.13
3.33
3.53
¾
¾
50
¾
mA
Min
Typ.
Max
Units
VOH = 2.9 V (P1-0~P6-3, P8-0, P8-1)
-1.0
-2.0
¾
VOL = 0.4 V (P1-0~P6-3, P8-0, P8-1)
1.0
2.0
¾
VOL = 0.4 V (P7-0 to P7-3)
5
15
¾
VIH = 3.3 V,
VIL = 0 V (P1-0 to P6-3, P8-0, P8-1)
¾
¾
±1.0
VIH = 5.5 V, VIL = 0 V (P7-0 to P7-3)
¾
¾
±1.0
¾
VDD ´
0.8
~
MVDD
¾
0
~
MVDD
´ 0.2
(P6-0 to P6-3, P8-0, P8-1)
Pull-down/up specified
25
50
120
(P3-0) Test input pulled down
¾
10
¾
Min
Typ.
Max
Units
0
~
MVDD
V
¾
¾
6
¾
bit
MVDD = 1.8 to 3.6 V, Ta = -30 to 75°C
(Note 6)
¾
¾
±2.0
MVDD = 2.0 to 3.6 V, Ta = -40 to 85°C
(Note 6)
¾
¾
±1.0
VIH = 3.3 V, VIL = 0 V (ADin1 to ADin4)
¾
¾
±1.0
mA
V
No load (LCD output, 1/3 bias method)
VBS3
IDD-LCD
Units
LCD driver operating current
I/O ports (P1-0 to P6-3, P8-0, P8-1, P7-0 to P7-3)
Parameter
High level
Output current
Low level
Symbol
Test
Circuit
IOH2
¾
IOL2
IOL3
Input leakage current
High level
¾
ILI
Test Condition
VIH
¾
Input voltage
Low level
Input pull-up/down resistance
¾
RIN2
mA
V
VIL
RIN1
mA
kW
AD converter (ADin1 to ADin4)
Symbol
Test
Circuit
Analog input voltage range
VAD
¾
Resolution
VRES
¾
Parameter
Total conversion error
Analog input leakage current
¾
ILI
¾
¾
Test Condition
ADin1 to ADin4
LSB
mA
Note 6: The values are guaranteed when CVDD = DVDD = AVDD = 3.0 to 3.6 V.
15
2003-04-01
TC94A39FAG/FB
PDO, TMAX, RFGC, TEBC, FMO, DMO, TRO, FOO, and SEL output
Parameter
Output current
Symbol
High level
IOH6
Low level
IOL4
Test
Circuit
¾
Rout3
Output resistance
¾
Rout4
VREF output ON resistance
¾
Ron
Test Condition
Min
Typ.
Max
VOH = 2.9 V (SEL, TMAX)
-2.0
¾
¾
VOL = 0.4 V (SEL, TMAX)
2.0
¾
¾
(RFGC, TEBC, FMO, DMO, TRO, FOO)
¾
3.0
¾
(PDO)
¾
5.0
¾
(RFGC, TEBC, FMO, DMO, PDO)
¾
¾
500
Units
mA
kW
W
Transfer delay time (BCK, LRCK, AOUT, DOUT, IPF, SBOK, CLCK, DATA, SFSY, SBSY)
Parameter
Transfer delay
time
Symbol
High level
tpLH
Low level
tpHL
Test
Circuit
Test Condition
Min
Typ.
Max
¾
¾
10
¾
¾
¾
10
¾
Min
Typ.
Max
Units
(FEI, TEI, RFRP, SBAD)
¾
8
¾
bit
(FEI, TEI, RFRP)
¾
176.4
¾
(SBAD)
¾
88.2
¾
0.15 ´
AVDD
¾
0.85 ´
AVDD
V
Min
Typ.
Max
Units
¾
5
¾
bit
¾
Units
ns
CD processor AD conversion block (FEI, TEI, RFRP, SBAD)
Symbol
Test
Circuit
Resolution
¾
¾
Sampling frequency
¾
¾
¾
¾
Parameter
Conversion input range
Test Condition
AVDD = 3.3 V (FEI, TEI, RFRP, SBAD)
kHz
CD processor DA conversion block (focus tracking system)
Symbol
Test
Circuit
Number of bits
¾
¾
(FOO, TRO)
Sampling frequency
¾
¾
(FOO, TRO)
Conversion output range
¾
¾
AVDD = 3.3 V (FOO, TRO)
Parameter
Test Condition
¾
2.8
¾
MHz
AVSS
¾
AVDD
V
Min
Typ.
Max
Units
AVSS
¾
AVDD
V
CD processor PLL/VCO block
Symbol
Test
Circuit
Input/output signal range
¾
¾
(LPFN, LPFO)
Frequency characteristic
¾
¾
(LPFN-LPFO) -3dB point (Gain = 1)
¾
8
¾
MHz
Oscillation center frequency
¾
¾
LPFO = VREF
¾
34
¾
MHz
Frequency variable range
¾
¾
[VCOGSL] bit = Low
-30
¾
+30
[VCOGSL] bit = High”
-40
¾
+40
Min
Typ.
Max
Units
AVSS
¾
AVDD
V
-50
¾
+50
mV
¾
10
¾
kW
Parameter
Test Condition
%
CD processor comparator (TEZI, RFZI)
Symbol
Test
Circuit
Input range
¾
¾
(TEZI, RFZI)
Hysteresis voltage
¾
¾
(TEZI, RFZI) VREF reference
Zin2
¾
(TEZI, RFZI)
Parameter
Input resistance
Test Condition
16
2003-04-01
TC94A39FAG/FB
CD processor data slicer (RFI/SLCO)
Symbol
Test
Circuit
Input amplitude
¾
¾
(RFI) VREF reference
Input resistance
Zin1
¾
(RFI) Set resistance by CD command
DAC resolution
¾
¾
DAC output conversion range
¾
DAC output impedance
Parameter
Test Condition
Min
Typ.
Max
Units
0.6
1.2
2.0
VP-P
¾
20
¾
¾
10
¾
(SLCO) R-2R DAC
¾
6
¾
bit
¾
(SLCO) R-2R DAC
0.75 ´
VREF
¾
1.25 ´
VREF
V
¾
¾
(SLCO) R-2R DAC
¾
2.5
¾
kW
Symbol
Test
Circuit
Min
Typ.
Max
Units
THD + N
¾
1-kHz sine wave, full-scale input
¾
-85
-77
dB
Internal Zero detect = OFF
85
91
¾
Internal Zero detect = ON
95
100
¾
kW
1-bit DA converter
Parameter
Total harmony distortion
S/N (1)
S/N ratio
S/N (2)
¾
Test Condition
dB
Dynamic range
DR
¾
1-kHz sine wave, input reduction of -60dB
83
90
¾
dB
Crosstalk
CT
¾
1-kHz sine wave, full-scale input
¾
-90
-83
dB
DACout
¾
1-kHz sine wave, full-scale input
790
825
860
mVrms
Analog output level
17
2003-04-01
TC94A39FAG/FB
Package Dimensions
Weight: 0.32 g (typ.)
18
2003-04-01
TC94A39FAG/FB
Package Dimensions
Weight: 0.45 g (typ.)
19
2003-04-01
TC94A39FAG/FB
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
20
2003-04-01
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