19-5770; Rev 4/11 DS1339 I C Serial Real-Time Clock 2 GENERAL DESCRIPTION FEATURES The DS1339 serial real-time clock (RTC) is a lowpower clock/date device with two programmable timeof-day alarms and a programmable square-wave output. Address and data are transferred serially 2 through an I C bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in powersense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with LeapYear Compensation Valid Up to 2100 Available in a Surface-Mount Package with an Integrated Crystal (DS1339C) I2C Serial Interface Two Time-of-Day Alarms Programmable Square-Wave Output Oscillator Stop Flag Automatic Power-Fail Detect and Switch Circuitry Trickle-Charge Capability Underwriters Laboratories (UL) Recognized Pin Configurations appear at end of data sheet. APPLICATIONS Handhelds (GPS, POS Terminals) Consumer Electronics (Set-Top Box, Digital Recording, Network Appliance) Office Equipment (Fax/Printers, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Routers, Switches, Servers) Other (Utility Meter, Vending Machine, Thermostat, Modem) ORDERING INFORMATION PART DS1339C-2# DS1339C-3# DS1339C-33# DS1339U-2+ DS1339U-3+ DS1339U-33+ TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C VOLTAGE (V) 2.0 3.0 3.3 2.0 3.0 3.3 PIN-PACKAGE 16 SO (300 mils) 16 SO (300 mils) 16 SO (300 mils) 8 µSOP 8 µSOP 8 µSOP TOP MARK† DS1339C-2 DS1339C-3 DS1339C-33 1339 rr-2 1339 rr-3 1339 rr-33 +Denotes a lead(Pb)-free/RoHS-compliant package. #Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and lead-free soldering processes. †A “+” anywhere on the top mark indicates a lead(Pb)-free device. A “#” denotes a RoHS-compliant device. rr = second line, revision code 1 of 20 2 DS1339 I C Serial Real-Time Clock ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………-0.3V to +6.0V Operating Temperature Range (Noncondensing)………………………………………………………….-40°C to +85°C Storage Temperature Range………………………………………………………………………………..-55°C to +125°C Lead Temperature (soldering, 10s)...…………………………………………………………………………………+260°C Soldering Temperature (reflow).……………………………………………………………………………………….+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) µSOP Junction-to-Ambient Thermal Resistance (θJA).…………………...……………………………………….206.3°C/W Junction-to-Case Thermal Resistance (θJC)……………………………………………………………………42°C/W SO Junction-to-Ambient Thermal Resistance (θJA).……………………………………………………………….73°C/W Junction-to-Case Thermal Resistance (θJC)……………………………………………………………………23°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) (Note 2) PARAMETER MIN TYP MAX DS1339-2 1.8 2.0 5.5 DS1339-3 2.7 3.0 5.5 DS1339-33 2.97 3.3 5.5 VBACKUP 1.3 3.0 3.7 V Logic 1 VIH 0.7 x VCC VCC + 0.3 V Logic 0 VIL -0.3 +0.3 x VCC V Supply Voltage Backup Supply Voltage Power-Fail Voltage SYMBOL VCC VPF CONDITIONS DS1339-2 1.58 1.70 1.80 DS1339-3 2.45 2.59 2.70 DS1339-33 2.70 2.85 2.97 2 of 20 UNITS V V 2 DS1339 I C Serial Real-Time Clock DC ELECTRICAL CHARACTERISTICS (VCC = MIN to MAX, TA = -40°C to +85°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage ILI (Note 3) 1 µA I/O Leakage ILO (Note 4) 1 µA Logic 0 Out VOL = 0.4V; VCC > VCC MIN (-3, -33); VCC ≥ 2.0V (-2) IOL (Note 4) 3 mA Logic 0 Out VOL = 0.2 (VCC); 1.8V < VCC < 2.0V (DS1339-2) IOL (Note 4) 3 mA Logic 0 Out VOL = 0.2 (VCC); 1.3V < VCC < 1.8V (DS1339-2) IOL (Note 4) 250 µA VCC Active Current ICCA (Note 5) 450 µA VCC Standby Current (Note 6) ICCS -2: VCC = 2.2V 60 100 -3: VCC = 3.3V 80 150 -33: VCC = 5.5V Trickle-Charger Resistor Register 10h = A5h, VCC = Typ, VBACKUP = 0V R1 Trickle-Charger Resistor Register 10h = A6h, VCC = Typ, VBACKUP = 0V Trickle-Charger Resistor Register 10h = A7h, VCC = Typ, VBACKUP = 0V VBACKUP Leakage Current µA 200 250 Ω R2 2000 Ω R3 4000 Ω IBKLKG 25 100 nA TYP MAX UNITS (Note 7) DC ELECTRICAL CHARACTERISTICS (VCC = 0V, T A = -40°C to +85°C.) (Note 2) PARAMETER SYMBOL VBACKUP Current EOSC = 0, SQW Off IBKOSC (Note 8) 400 700 nA VBACKUP Current EOSC = 0, SQW On IBKSQW (Note 8) 600 1000 nA 10 100 nA VBACKUP Current EOSC = 1 CONDITIONS IBKDR 3 of 20 MIN 2 DS1339 I C Serial Real-Time Clock AC ELECTRICAL CHARACTERISTICS (VCC = MIN to MAX, TA = -40°C to +85°C.) (Note 9) PARAMETER SYMBOL CONDITION Fast mode SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition (Note 10) f SCL tBUF tHD:STA LOW Period of SCL Clock tLOW HIGH Period of SCL Clock tHIGH Setup Time for a Repeated START Condition tSU:STA Data Hold Time (Notes 11, 12) tHD:DAT Data Setup Time (Note 13) tSU:DAT Rise Time of Both SDA and SCL Signals (Note 14) tR Fall Time of Both SDA and SCL Signals (Note 14) tF Setup Time for STOP Condition tSU:STO MIN TYP 100 MAX UNITS 400 kHz Standard mode 100 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 0.6 Standard mode 4.7 Fast mode 0 Standard mode 0 Fast mode 100 Standard mode 250 µs µs µs µs µs 0.9 ns Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 300 Fast mode 0.6 Standard mode 4.0 Capacitive Load for Each Bus Line (Note 14) CB I/O Capacitance (SDA, SCL) CI/O (Note 9) Oscillator Stop Flag (OSF) Delay tOSF (Note 15) 4 of 20 µs ns ns µs 100 400 pF 10 pF ms 2 DS1339 I C Serial Real-Time Clock POWER-UP/DOWN CHARACTERISTICS (TA = -40°C to +85°C) (Note 2, Figure 1) PARAMETER SYMBOL CONDITIONS MIN (Note 16) TYP MAX UNITS 2 ms Recovery at Power-Up tREC VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 µs WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. Note 2: Limits at -40°C are guaranteed by design and are not production tested. Note 3: SCL only. Note 4: SDA and SQW/INT. Note 5: ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled. Note 6: Specified with the I C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled. Note 7: VCC must be less than 3.63V if the 250Ω resistor is selected. Note 8: Using recommended crystal on X1 and X2. Note 9: Guaranteed by design; not production tested. 2 Note 10: After this period, the first clock pulse is generated. Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 12: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW ) of the SCL signal. Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 14: CB—total capacitance of one bus line in pF. Note 15: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCCMAX and 1.3V ≤ VBACKUP ≤ 3.7V. Note 16: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs. Figure 1. Power-Up/Down Timing VCC VPF(MAX) VPF(MIN) t VCCR t VCCF tREC INPUTS DON'T CARE RECOGNIZED RECOGNIZED HIGH-Z OUTPUTS VALID VALID 5 of 20 2 DS1339 I C Serial Real-Time Clock Figure 2. Timing Diagram Figure 3. Block Diagram X 1 X 2 SQW/INT 1Hz/4.096kHz/8.192kHz/32.768kHz CL 1Hz CL Oscillator and divider "C" version only VCC VBACKUP MUX/ BUFFER Power Control CONTROL LOGIC ALARM, TRICKLE CHARGE, AND CONTROL REGISTERS CLOCK AND CALENDAR REGISTERS GND DS1339 SCL SDA SERIAL BUS INTERFACE AND ADDRESS REGISTER USER BUFFER (7 BYTES) 6 of 20 N 2 DS1339 I C Serial Real-Time Clock TYPICAL OPERATING CHARACTERISTICS (VCC = 3.3v, TA = +25°C, unless otherwise noted.) IBACKUP vs. VBACKUP ICC vs. VCC V CC=0V RS1=RS0=1 250 900 SCL=400kHz ICCA 850 200 IBAT OSC2 1) 750 (SQWE = SUPPLY CURRENT (uA SUPPLY CURRENT (nA 800 700 650 IBAT OSC1 (SQWE = 0) 600 550 500 450 150 SCL=SDA=0Hz ICCS 100 400 350 300 1.3 1.8 2.3 2.8 3.3 3.8 VBACKUP (V) 4.3 4.8 IBACKUP vs. Temperature 50 5.3 1.8 V CC=0V 2.3 2.8 3.3 3.8 VCC (V) 4.3 4.8 5.3 Oscillator Frequency vs. Supply Voltage VBACKUP = 3.0V 650 32768.5 32768.4 INTCN = 0 RS2 = RS1 = 1 550 FREQUENCY (Hz) SUPPLY CURRENT (nA 600 500 450 INTCN = 0 400 32768.3 32768.2 32768.1 350 32768.0 1.0 300 -40 -20 0 20 40 TEMPERATURE (°C) 60 1.5 2.0 2.5 3.0 3.5 4.0 Oscillator Supply Voltage (V) 80 7 of 20 4.5 5.0 2 DS1339 I C Serial Real-Time Clock PIN DESCRIPTION PIN SO µSOP NAME FUNCTION Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. An external 32.768kHz oscillator can also drive the DS1339. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left unconnected. 1 — X1 2 — X2 3 14 VBACKUP 4 15 GND 5 16 SDA 6 1 SCL 7 2 SQW/INT 8 3 VCC — 4–13 N.C. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. Secondary Power Supply. Supply voltage must be held between 1.3V and 3.7V for proper operation. This pin can be connected to a primary cell, such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used in conjunction with the trickle-charge feature. Diodes should not be placed in series between the backup source and the VBACKUP input, or improper operation will result. If a backup supply is not required, VBACKUP must be grounded. UL recognized to ensure against reverse charging current when used with a lithium cell. For more information, visit www.maxim-ic.com/qa/info/ul. Ground. DC power is provided to the device on these pins. Serial Data Input/Output. SDA is the input/output pin for the I2C serial interface. The SDA pin is an open-drain output and requires an external pullup resistor. The pull up voltage may be up to 5.5V regardless of the voltage on VCC. Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. The pull up voltage may be up to 5.5V regardless of the voltage on VCC. Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. The SQW/INT pin is an open-drain output and requires an external pullup resistor. The pull up voltage may be up to 5.5V regardless of the voltage on VCC. If not used, this pin may be left unconnected. Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected and VCC is below VPF, reads and writes are inhibited. The timekeeping and alarm functions operate when the device is powered by VCC or VBACKUP. No Connection. These pins are unused and must be connected to ground. TYPICAL OPERATING CIRCUIT VCC VCC CRYSTAL VCC RPU RPU 1 2 X1 X2 6 SCL CPU 8 VCC SQW/INT 7 i DS1339 5 SDA VBACKUP GND 3 4 8 of 20 2 DS1339 I C Serial Real-Time Clock DETAILED DESCRIPTION The DS1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day 2 alarms and a programmable square-wave output. Address and data are transferred serially through an I C bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in powersense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. OPERATION The DS1339 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The block diagram in Figure 3 shows the main elements of the serial real-time clock. POWER CONTROL The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed after tREC (Figure 1). On the first application of power to the device the time and date registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). Table 1. Power Control SUPPLY CONDITION READ/WRITE ACCESS POWERED BY VCC < VPF, VCC < VBACKUP VCC < VPF, VCC > VBACKUP VCC > VPF, VCC < VBACKUP VCC > VPF, VCC > VBACKUP No No Yes Yes VBACKUP VCC VCC VCC OSCILLATOR CIRCUIT The DS1339 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics. 9 of 20 2 DS1339 I C Serial Real-Time Clock Table 2. Crystal Specifications* PARAMETER SYMBOL Nominal Frequency fO Series Resistance ESR Load Capacitance CL MIN TYP MAX 32.768 kHz 50 6 UNITS kΩ pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information DS1339C ONLY The DS1339C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25°C is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature. Figure 4. Typical PC Board Layout for Crystal LOCAL GROUND PLANE (LAYER 2) X1 CRYSTAL X2 NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE. GND 10 of 20 2 DS1339 I C Serial Real-Time Clock ADDRESS MAP Table 3 shows the address map for the DS1339 registers. During a multibyte access, when the address pointer 2 reaches the end of the register space (10h), it wraps around to location 00h. On an I C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. Table 3. Timekeeper Registers ADDRESS BIT 7 00h 0 10 Seconds 01h 0 10 Minutes 02h 0 12/24 03h 04h 0 0 0 0 05h Century 06h BIT 6 BIT 5 AM/PM BIT 4 BIT 3 BIT 2 FUNCTION RANGE Seconds Seconds 00–59 Minutes Minutes 00–59 Hour Hours 10 Hour 20 Hour 0 0 10 Date 10 0 0 Month 10 Year BIT 1 0 Day Month Year A1M1 10 Seconds Seconds 08h A1M2 10 Minutes Minutes 09h A1M3 0Ah A1M4 0Bh A2M2 0Ch A2M3 AM/PM 20 Hour DY/DT 10 Hour 10 Date AM/PM 20 Hour Alarm 1 Hours Hour Alarm 1 Day, Alarm 1 Date Alarm 2 Minutes Day, Date 10 Minutes 12/24 Day Date Month/ Century Year Alarm 1 Seconds Alarm 1 Minutes Date 07h 12/24 BIT 0 Minutes 00–59 00–59 1–12 + AM/PM 00–23 1-7, 1-31 00–59 Hour Alarm 2 Hours 1–12 + AM/PM 00–23 Day, Date Alarm 2 Day, Alarm 2 Date 1–7, 1–31 10 Hour 10 Date 1–12 +AM/PM 00–23 1–7 01–31 01–12 + Century 00–99 0Dh A2M4 DY/DT 0Eh EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Control — 0Fh OSF 0 0 0 0 0 A2F A1F — 10h TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 Status Trickle Charger — Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC and VBACKUP falls below the VBACKUP(MIN). 11 of 20 2 DS1339 I C Serial Real-Time Clock TIME AND DATE OPERATION The time and date information is obtained by reading the appropriate register bytes. Table 3 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the BCD format. The DS1339 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the 20-hour bit (20 to 23 hours). All hours values, including the alarms, must be re-entered whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START or STOP, and when the address pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. If enabled, the 1Hz square-wave output transitions high 500ms after the seconds data transfer, provided the oscillator is already running. ALARMS The DS1339 contains two time of day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the Alarm Enable and INTCN bits of the Control Register) to activate the SQW/INT output on an alarm match condition. Bit 7 of each of the time of day/date alarm registers are mask bits (Table 4). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 4 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to a logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to a logic 1, the alarm is the result of a match with day of the week. The device checks for an alarm match once per second. When the RTC register values match alarm register settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is set to logic 1. If the corresponding Alarm Interrupt Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the SQW/INT) signal. If the BBSQI bit is set to 1, the INT output activates while the part is being powered by VBACKUP. The alarm output remains active until the alarm flag is cleared by the user. 12 of 20 2 DS1339 I C Serial Real-Time Clock Table 4. Alarm Mask Bits DY/DT X X X X ALARM 1 REGISTER MASK BITS (Bit 7) A1M4 A1M3 A1M2 A1M1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 ALARM 2 REGISTER MASK BITS (Bit 7) A2M4 A2M3 A2M2 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 DY/DT X X X 0 1 ALARM RATE Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes, and seconds match Alarm when date, hours, minutes, and seconds match Alarm when day, hours, minutes, and seconds match ALARM RATE Alarm once per minute (00 sec. of every min.) Alarm when minutes match Alarm when hours and minutes match Alarm when date, hours, and minutes match Alarm when day, hours, and minutes match SPECIAL-PURPOSE REGISTERS The DS1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave output. CONTROL REGISTER (0Eh) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Bit 7: Enable Oscillator (EOSC). This bit when set to logic 0 starts the oscillator. When this bit is set to a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied. Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the square wave or interrupt output when VCC is absent and the DS1339 is being powered by the VBACKUP pin. When BBSQI is a logic 0, the SQW/INT pin goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. Table 5 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied. Table 5. SQW/INT Output INTCN RS2 RS1 0 0 0 0 1 1 1 0 0 1 1 X X X 0 1 0 1 X X X SQW/INT OUTPUT 1Hz 4.096kHz 8.192kHz 32.768kHz A1F A2F A2F + A1F A2IE A1IE X X X X 0 1 1 X X X X 1 0 1 13 of 20 2 DS1339 I C Serial Real-Time Clock Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied. STATUS REGISTER (0Fh) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 0 0 A2F A1F Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) 2) 3) 4) The first time power is applied. The voltage on both VCC and VBACKUP are insufficient to support oscillation. The EOSC bit is turned off. External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. 14 of 20 2 DS1339 I C Serial Real-Time Clock TRICKLE CHARGER REGISTER (10h) The simplified schematic in Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode-select (DS) bits (bits 2 and 3) select whether or not a diode is connected between VCC and VBACKUP. The ROUT bits (bits 0 and 1) select the value of the resistor connected between VCC and VBACKUP. Table 6 shows the bit values. Table 6. Trickle Charger Register (10h) BIT 7 TCS3 X X X 1 1 1 1 1 1 0 BIT 6 TCS2 X X X 0 0 0 0 0 0 0 BIT 5 TCS1 X X X 1 1 1 1 1 1 0 BIT 4 TCS0 X X X 0 0 0 0 0 0 0 BIT 3 DS1 0 1 X 0 1 0 1 0 1 0 BIT 2 DS0 0 1 X 1 0 1 0 1 0 0 BIT 1 ROUT1 X X 0 0 0 1 1 1 1 0 BIT 0 ROUT0 X X 0 1 1 0 0 1 1 0 FUNCTION Disabled Disabled Disabled No diode, 250Ω resistor One diode, 250Ω resistor No diode, 2kΩ resistor One diode, 2kΩ resistor No diode, 4kΩ resistor One diode, 4kΩ resistor Initial power-up values Warning: The ROUT value of 250Ω must not be selected whenever VCC is greater than 3.63V. The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3V system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) / 2kΩ ≈ 1.3mA As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases. 15 of 20 2 DS1339 I C Serial Real-Time Clock Figure 5. Programmable Trickle Charger R1 VCC 250Ω VBACKUP R2 2kΩ R3 4kΩ 1 OF 16 SELECT NOTE: ONLY 1010 ENABLES CHARGER TCS3 BIT 7 TCS2 BIT 6 TCS1 BIT 5 TCS0 BIT 4 1 OF 2 SELECT DS1 BIT 3 1 OF 3 SELECT DS0 BIT 2 ROUT1 BIT 1 ROUT0 BIT 0 TCS0-3 = TRICKLE CHARGER SELECT DS0-1 = DIODE SELECT ROUT0-1 = RESISTOR SELECT TRICKLE CHARGE REGISTER I2C SERIAL DATA BUS The DS1339 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339 2 operates as a slave on the I C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast mode (400kHz cycle rate) are defined. The DS1339 works in both modes. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 6): Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. START data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. STOP data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. 16 of 20 2 DS1339 I C Serial Real-Time Clock Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figure 6. Data Transfer on I2C Serial Bus Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The DS1339 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (Figure 7). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1339 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. After the DS1339 acknowledges the slave address + write bit, the master transmits a register address to the DS1339. This 17 of 20 2 DS1339 I C Serial Real-Time Clock sets the register pointer on the DS1339, with the DS1339 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS1339 acknowledging each byte received. The address pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1339 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 8). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1339 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The DS1339 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The DS1339 must receive a “not acknowledge” to end a read. <Slave Address> 1101000 S <R/W> Figure 7. Data Write—Slave Receiver Mode <Word Address (n)> <Data(n)> 0 A XXXXXXXX A XXXXXXXX A S - Start A - Acknowledge (ACK) P - Stop <Data(n+1)> <Data(n+X)> XXXXXXXX A ... XXXXXXXX A P Master to slave DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) Slave to master <Slave Address> S 1101000 <RW> Figure 8. Data Read (from Current Pointer Location)—Slave Transmitter Mode <Data(n)> <Data(n+1)> 1 A XXXXXXXX A XXXXXXXX S - Start A - Acknowledge (ACK) P - Stop A - Not Acknowledge (NACK) Master to slave <Data(n+2)> A XXXXXXXX <Data(n+X)> A ... XXXXXXXX A P DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK Slave to master S 1101000 <Word Address (n)> 0 A XXXXXXXX A Sr <Data(n)> XXXXXXXX A <Data(n+1)> XXXXXXXX A S - Start Sr - Repeated Start A - Acknowledge (ACK) P - Stop A - Not Acknowledge (NACK) <RW> <RW> Figure 9. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit <Slave Address> 1101000 <Data(n+2)> <Data(n+X)> XXXXXXXX A ... Master to slave Slave to master 1 A XXXXXXXX A P DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK 18 of 20 2 DS1339 I C Serial Real-Time Clock HANDLING, PCB LAYOUT, AND ASSEMBLY The DS1339C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for moisture-sensitive device (MSD) classifications. PIN CONFIGURATIONS TOP VIEW TOP VIEW SCL SDA SQW/INT VCC X1 DS1339 X2 SQW/INT VBACKUP SCL GND SDA µSOP DS1339C GND VCC VBACKUP N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SO (300 mils) CHIP INFORMATION PROCESS: CMOS PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 µSOP U8+1 21-0036 90-0092 16 SO W16#H2 21-0042 90-0107 19 of 20 2 DS1339 I C Serial Real-Time Clock REVISION HISTORY REVISION DATE 100108 4/11 DESCRIPTION Removed leaded part numbers from the Ordering Information table. Removed the pullup resistor voltage spec from the Recommended DC Operating Conditions table and added it to the pin descriptions. Removed Note 7 from the IBKDR specification in the DC Electrical Characteristics table. Updated the block diagram (Figure 3) to show that SQW/INT is open drain. Added the UL link to the VBACKUP description in the Pin Description table. Removed the duplicate Oscillator Circuit section. Added the initial POR state for time and date registers in the Power Control section. Changed the series resistance (ESR) value in Table 2 from 45kΩ to 50kΩ. Added the overbar to the “A” legend for NACK in Figure 8. Updated the soldering temperature and added lead temperature information to the Absolute Maximum Ratings section; added the Package Thermal Characteristics section and updated the µSOP θJA and θJC numbers; changed the VCC max numbers from 2.2V to 5.5V for DS1339-2 and 3.3V to 5.5V for DS1339-3 in the Recommended DC Operating Conditions table. Updated the ICCS parameter in the DC Electrical Characteristics table. Changed the 10 Hour bit to 20 Hour bit for 02h, 09h, and 0Ch in Table 1 and the Time and Date Operation section. Updated the Handling, PCB Layout, and Assembly section; removed the transistor count from the Chip Information section; added the land pattern numbers to the Package Information table. PAGES CHANGED 1 2, 8 3 6 8 9 9 10 18 2 3 11, 12 19 20 of 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.