CY62148E MoBL® 4-Mbit (512 K × 8) Static RAM 4-Mbit (512 K × 8) Static RAM Features advanced circuit design to provide ultra low standby current. This is ideal for providing More Battery Life™ (MoBL) in portable applications. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), Outputs are disabled (OE HIGH), or during an active Write operation (CE LOW and WE LOW). ■ Very high speed: 45 ns ■ Voltage range: 4.5 V to 5.5 V ■ Pin compatible with CY62148B ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 7 µA (Industrial) ■ Ultra low active power ❐ Typical active current: 2.0 mA at f = 1 MHz ■ Easy memory expansion with CE, and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 32-pin thin small outline package (TSOP) II and 32-pin small-outline integrated circuit (SOIC)[1] packages To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Functional Description The CY62148E is a high performance CMOS static RAM organized as 512 K words by 8-bits. This device features To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The CY62148E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. Logic Block Diagram I/O00 IO INPUT BUFFER I/O1 IO 1 I/O2 IO 2 SENSE AMPS ROW DECODER 512K x 8 ARRAY I/O3 IO 3 I/O4 IO 4 I/O5 IO 5 I/O6 IO 6 CE I/O IO77 POWER DOWN A17 A18 A13 A14 OE A15 COLUMN DECODER WE A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Note 1. SOIC package is available only in 55 ns speed bin. Cypress Semiconductor Corporation Document Number: 38-05442 Rev. *L • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 6, 2013 CY62148E MoBL® Contents Pin Configurations ........................................................... 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Document Number: 38-05442 Rev. *L Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 Page 2 of 17 CY62148E MoBL® Pin Configurations Figure 1. 32-pin SOIC/TSOP II pinout Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Product Portfolio Power Dissipation VCC Range (V) Product CY62148ELL TSOP II CY62148ELL SOIC Range Min Typ [2] Max Industrial 4.5 5.0 5.5 Industrial / Automotive-A 4.5 5.0 5.5 Speed (ns) Operating ICC (mA) f = 1 MHz f = fmax Standby ISB2 (µA) Typ [2] Max Typ [2] Max Typ [2] Max 45 2 2.5 15 20 1 7 55 2 2.5 15 20 1 7 Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 38-05442 Rev. *L Page 3 of 17 CY62148E MoBL® DC input voltage [3, 4] ......... –0.5 V to 6.0 V (VCCmax + 0.5 V) Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential ................. –0.5 V to 6.0 V (VCCmax + 0.5 V) DC voltage applied to outputs in high Z state [3, 4] ............. –0.5 V to 6.0 V (VCCmax + 0.5 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Device Ambient Temperature Range CY62148E VCC[5] Industrial / –40 °C to +85 °C 4.5 V to 5.5 V Automotive-A Electrical Characteristics Over the operating range Parameter VOH[8] Description Output HIGH voltage Test Conditions VCC = 4.5 V, IOH = –1 mA 55 ns [6] 45 ns Min Typ [7] Max Min Typ [7] Max Unit 2.4 – – 2.4 – – V VCC = 5.5 V, IOH = –0.1 mA – – 3.4 [8] – – 3.4 [8] V – – 0.4 – – 0.4 V – VCC + 0.5 V V VOL Output LOW voltage IOL = 2.1 mA VIH Input HIGH voltage VCC = 4.5 V to 5.5 V 2.2 – VIL Input LOW voltage VCC = 4.5 V to 5.5 V For TSOPII package –0.5 – 0.8 – – – – – – –0.5 – 0.6 [9] –1 – +1 –1 – +1 µA +1 –1 – +1 µA mA For SOIC package IIX Input leakage current IOZ Output leakage current GND < VO < VCC, output disabled –1 – ICC VCC operating supply current f = fmax = 1/tRC – 15 20 – 15 20 – 2 2.5 – 2 2.5 Automatic CE power-down current – CMOS inputs CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max) – 1 7 – 1 7 ISB2 [10] GND < VI < VCC VCC + 0.5 2.2 f = 1 MHz VCC = VCC(max), IOUT = 0 mA CMOS levels µA Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 6. SOIC package is available only in 55 ns speed bin. 7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 8. Please note that the maximum VOH limit for this device does not exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5 V legacy processors that require a minimumVIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. 9. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This is applicable to SOIC package only. 10. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05442 Rev. *L Page 4 of 17 CY62148E MoBL® Capacitance Parameter [11] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(Typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [11] Test Conditions 32-pin SOIC Package Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 75 77 C/W 10 13 C/W Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 32-pin TSOP II Unit Package AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES 3.0 V 30 pF INCLUDING JIG AND SCOPE 90% 10% R2 GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT V Parameter [11] 5.0 V Unit R1 1800 R2 990 RTH 639 VTH 1.77 V Note 11. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05442 Rev. *L Page 5 of 17 CY62148E MoBL® Data Retention Characteristics Over the operating range Parameter Description VDR VCC for data retention ICCDR[13] Data retention current Min Typ [12] Max Unit 2 – – V – 1 7 µA 0 – – ns TSOP II 45 – – ns SOIC 55 – – ns Conditions VCC = VDR, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V tCDR Chip deselect to data retention time tR[14] Operation recovery time Industrial / Automotive-A Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 2.0 V VCC(min) tR CE Notes 12. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 13. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document Number: 38-05442 Rev. *L Page 6 of 17 CY62148E MoBL® Switching Characteristics Over the operating range Parameter [15] Description 55 ns [16] 45 ns Min Max Min Max Unit Read Cycle tRC Read cycle time 45 – 55 – ns tAA Address to data valid – 45 – 55 ns tOHA Data hold from address change 10 – 10 – ns tACE CE LOW to data valid – 45 – 55 ns tDOE OE LOW to data valid – 22 – 25 ns tLZOE OE LOW to low Z [17] 5 – 5 – ns – 18 – 20 ns [17, 18] tHZOE OE HIGH to high Z tLZCE CE LOW to low Z [17] 10 – 10 – ns tHZCE CE HIGH to high Z [17, 18] – 18 – 20 ns tPU CE LOW to power-up 0 – 0 – ns CE HIGH to power-down – 45 – 55 ns tWC Write cycle time 45 – 55 – ns tSCE CE LOW to write end 35 – 40 – ns tAW Address setup to write end 35 – 40 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35 – 40 – ns tSD Data setup to write end 25 – 25 – ns tHD Data hold from write end 0 – 0 – ns tHZWE WE LOW to high Z [17, 18] – 18 – 20 ns tLZWE WE HIGH to low Z [17] 10 – 10 – ns tPD Write Cycle [19] Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 16. SOIC package is available only in 55 ns speed bin. 17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 18. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 19. The internal wre.ite time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document Number: 38-05442 Rev. *L Page 7 of 17 CY62148E MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [23, 24] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O NOTE 25 tHD DATA VALID tHZOE Notes 20. Device is continuously selected. OE, CE = VIL. 21. WE is HIGH for read cycles. 22. Address valid before or similar to CE transition LOW. 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05442 Rev. *L Page 8 of 17 CY62148E MoBL® Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (CE Controlled) [26, 27] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 28 tHD DATA VALID tHZWE tLZWE Notes 26. Data I/O is high impedance if OE = VIH. 27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 28. During this period, the I/Os are in output state and input signals must not be applied. Document Number: 38-05442 Rev. *L Page 9 of 17 CY62148E MoBL® Truth Table CE H WE OE [29] I/O Mode Power X X High Z Deselect/power-down Standby (ISB) L H L Data out Read Active (ICC) L L X Data in Write Active (ICC) L H H High Z Selected, outputs disabled Active (ICC) Note 29. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05442 Rev. *L Page 10 of 17 CY62148E MoBL® Ordering Information Table 1 lists the CY62148E MoBL® key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Key features and Ordering Information Speed (ns) 45 55 Ordering Code Package Diagram Package Type Operating Range CY62148ELL-45ZSXI 51-85095 32-pin TSOP II (Pb-free) Industrial CY62148ELL-45ZSXA 51-85095 32-pin TSOP II (Pb-free) Automotive-A CY62148ELL-55SXI 51-85081 32-pin SOIC (Pb-free) Industrial CY62148ELL-55SXA 51-85081 32-pin SOIC (Pb-free) Automotive-A Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 4 8 E LL - XX XX X X Temperature Grade: X = I or A I = Industrial; A = Automotive-A Pb-free Package Type: XX = ZS or S ZS = 32-pin TSOP II S = 32-pin SOIC Speed Grade: XX = 45 ns or 55 ns LL = Low Power Process Technology: E = 90 nm Bus width: 8 = × 8 Density: 4 = 4-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05442 Rev. *L Page 11 of 17 CY62148E MoBL® Package Diagrams Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095 51-85095 *B Document Number: 38-05442 Rev. *L Page 12 of 17 CY62148E MoBL® Package Diagrams (continued) Figure 10. 32-pin SOIC (450 Mil) S32.45/SZ32.45 Package Outline, 51-85081 51-85081 *E Document Number: 38-05442 Rev. *L Page 13 of 17 CY62148E MoBL® Acronyms Acronym Document Conventions Description CE Chip Enable CMOS Complementary Metal Oxide Semiconductor I/O Input/Output OE Output Enable MoBL More Battery Life SOIC Small Outline Integrated Circuit Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere µs microsecond mA milliampere SRAM Static Random Access Memory TSOP Thin Small Outline Package ns nanosecond WE Write Enable ohm % percent pF picofarad V volt W watt Document Number: 38-05442 Rev. *L Page 14 of 17 CY62148E MoBL® Document History Page Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM Document Number: 38-05442 Revision ECN Orig. of Change Submission Date ** 201580 AJU 01/08/04 New data sheet. *A 249276 SYT See ECN Changed status from Advance Information to Preliminary. Updated Features (Added RTSOP II and removed FBGA Package). Updated Functional Description (Added RTSOP II and removed FBGA Package). UpdatedPin Configurations (Added RTSOP II and removed FBGA Package). Updated Operating Range (Updated Note 5 (Changed VCC stabilization time from 100 s to 200 s)). Updated Data Retention Characteristics (Changed maximum value of ICCDR parameter from 2.0 A to 2.5 A, changed minimum value of tR parameter from 100 s to tRC ns). Updated Switching Characteristics (Changed minimum value of tOHA parameter from 6 ns to 10 ns for both 35 ns and 45 ns speed bin, changed maximum value of tDOE parameter from 15 ns to 18 ns for 35 ns speed bin, changed maximum value of tHZOE, tHZWE parameters from 12 ns to 15 ns for 35 ns speed bin and 15 ns to 18 ns for 45 ns speed bin, changed minimum value of tSCE parameter from 25 ns to 30 ns for 35 ns speed bin and 40 ns to 35 ns for 45 ns speed bin, changed maximum value of tHZCE parameter from 12 ns to18 ns for 35 ns speed bin and 15 ns to 22 ns for 45 ns speed bin, changed minimum value of tSD parameter from 15 ns to 18 ns for 35 ns speed bin and 20 ns to 22 ns for 45 ns speed bin). Updated Ordering Information (Corrected typo in Package Name column, also updated Ordering Codes (to include Pb-free packages)). *B 414820 ZSD See ECN Changed status from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Updated Features (Removed 35 ns speed bin). Updated Pin Configurations (Removed the Note “DNU pins have to be left floating or tied to VSS to ensure proper application.” and its reference). Updated Product Portfolio (Removed 35 ns speed bin). Updated Maximum Ratings (Updated Note 3 to include current limit). Updated Electrical Characteristics (Removed “L” version of CY62148E, changed typical value of ICC parameter from 1.5 mA to 2 mA at f = 1 MHz, changed maximum value of ICC parameter from 2 mA to 2.5 mA at f = 1 MHz, changed typical value of ICC parameter from 12 mA to 15 mA at f = fmax, removed ISB1 parameter and its details, changed typical value of ISB2 parameter from 0.7 A to 1 A and maximum value of ISB2 parameter from 2.5 A to 7 A). Updated AC Test Loads and Waveforms (Changed the AC test load capacitance from 100 pF to 30 pF in Figure 2, changed test load parameters R1, R2, RTH and VTH from 1838 , 994 , 645 and 1.75 V to 1800 , 990 , 639 and 1.77 V). Updated Data Retention Characteristics (Changed maximum value of ICCDR parameter from 2.5 A to 7 A, Added typical value for ICCDR parameter). Updated Switching Characteristics (Removed 35 ns speed bin, changed minimum value of tLZOE parameter from 3 ns to 5 ns, changed minimum value of tLZCE and tLZWE parameters from 6 ns to 10 ns, changed maximum value of tHZCE parameter from 22 ns to 18 ns, changed minimum value of tPWE parameter from 30 ns to 35 ns, changed minimum value of tSD parameter from 22 ns to 25 ns). Updated Ordering Information (Updated ordering codes and replaced Package Name column with Package Diagram). Document Number: 38-05442 Rev. *L Description of Change Page 15 of 17 CY62148E MoBL® Document History Page (continued) Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM Document Number: 38-05442 Revision ECN Orig. of Change Submission Date Description of Change *C 464503 NXR See ECN Updated Product Portfolio (Included Automotive Range). Updated Operating Range (Included Automotive Range). Updated Electrical Characteristics (Included Automotive Range). Updated Data Retention Characteristics (Included Automotive Range). Updated Switching Characteristics (Included Automotive Range). Updated Ordering Information (Updated ordering codes (Included Automotive parts and their related information)). *D 485639 VKN See ECN Updated Operating Range (Updated VCC to 4.5 V to 5.5 V). *E 833080 VKN See ECN Updated Electrical Characteristics (Added VIL parameter for SOIC package, added Note 9 and referred the same note in VIL parameter for SOIC package). *F 890962 VKN See ECN Updated Pin Configurations (Added Note 1 related to SOIC package). Updated Product Portfolio (Included Automotive-A range and removed Automotive-E range). Updated Operating Range (Included Automotive-A range and removed Automotive-E range). Updated Electrical Characteristics (Included Automotive-A range and removed Automotive-E range, added Note 10 related to ISB2 and referred the same note in ISB2 parameter). Updated Data Retention Characteristics (Included Automotive-A range and removed Automotive-E range). Updated Switching Characteristics (Included Automotive-A range and removed Automotive-E range). Updated Ordering Information (Updated ordering codes (Added Automotive-A part and its related information, removed Automotive-E part and its related information). *G 2947039 VKN 06/10/2010 Updated Truth Table (Added Note 29 and referred the same note in CE column). Updated Ordering Information (Added “CY62148ELL-45ZSXA” part number). Updated Package Diagrams. Added Sales, Solutions, and Legal Information. *H 3006318 AJU 08/23/10 Updated Data Retention Characteristics (Added note 13 and referred the same note in ICCDR parameter). Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated in new template. *I 3235744 RAME 04/20/2011 Updated Functional Description (Removed the line “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines”). Updated Package Diagrams. *J 3302815 RAME 07/14/2011 Updated in new template. *K 3539544 TAVA 03/01/2012 Updated Electrical Characteristics (Updated Note 9). Updated Package Diagrams. *L 3992135 MEMJ 05/06/2013 Updated Functional Description. Updated Electrical Characteristics (Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH parameter and its corresponding values). Updated Package Diagrams: spec 51-85081 – Changed revision from *D to *E. Completing Sunset Review. Document Number: 38-05442 Rev. *L Page 16 of 17 CY62148E MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05442 Rev. *L Revised May 6, 2013 Page 17 of 17 More Battery Life is a trademark and MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.