CY62128EV30 MoBL® 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description ■ Very high speed: 45 ns The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). ■ Temperature ranges: ❐ Industrial: –40 °C to +85 °C ■ Wide voltage range: 2.2 V to 3.6 V ■ Pin compatible with CY62128DV30 ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 4 µA ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 32-pin SOIC, 32-pin thin small outline package (TSOP) Type I, and 32-pin shrunk thin small outline package (STSOP) packages To write to the device, take chip enable (CE1 LOW and CE2 HIGH) and write enable (WE) inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pin (A0 through A16). To read from the device, take chip enable (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. For a complete list of related resources, click here. Logic Block Diagram SENSE AMPS ROW DECODER 128K x 8 ARRAY I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 • POWER DOWN I/O 7 A16 A14 A12 OE A15 COLUMN DECODER WE Cypress Semiconductor Corporation Document Number: 38-05579 Rev. *M I/O 1 A13 CE1 CE2 I/O 0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 15, 2015 CY62128EV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05579 Rev. *M Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 2 of 19 CY62128EV30 MoBL® Pin Configuration Figure 1. 32-pin STSOP pinout [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Top View (not to scale) Figure 2. 32-pin TSOP I pinout [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Top View (not to scale) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Figure 3. 32-pin SOIC pinout [1] Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62128EV30LL Industrial Min Typ [2] Max 2.2 3.0 3.6 45 f = fmax Standby ISB2 (µA) Typ [2] Max Typ [2] Max Typ [2] Max 1.3 2.0 11 16 1 4 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 38-05579 Rev. *M Page 3 of 19 CY62128EV30 MoBL® DC input voltage [3, 4] ...................–0.3 V to VCC(max) + 0.3 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ................................... –55 °C to +125 °C Supply voltage to ground potential [3, 4] ...............–0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in high Z State [3, 4] ......................–0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch-up current .................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC[5] CY62128EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH voltage VOL Output LOW voltage VIH Input HIGH voltage VIL Input LOW voltage Test Conditions 45 ns (Industrial) Unit Min Typ [6] Max IOH = –0.1 mA 2.0 – – V IOH = –1.0 mA, VCC > 2.70 V 2.4 – – V IOL = 0.1 mA – – 0.4 V IOL = 2.1 mA, VCC > 2.70 V – – 0.4 V 1.8 – VCC + 0.3 V V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V V VCC = 2.2 V to 2.7 V –0.3 – 0.6 V VCC= 2.7 V to 3.6 V –0.3 – 0.8 V –1 – +1 µA IIX Input leakage current GND < VI < VCC IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 µA ICC VCC operating supply current f = fmax = 1/tRC – 11 16 mA – 1.3 2.0 mA – 1 4 µA – 1 4 µA f = 1 MHz ISB1[7] Automatic CE power-down current – CMOS inputs VCC = VCCmax IOUT = 0 mA CMOS levels CE1 > VCC0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V, VIN < 0.2 V f = fmax (address and data only), f = 0 (OE and WE), VCC = 3.60 V ISB2 [7] Automatic CE power-down current – CMOS inputs CE1 > VCC – 0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05579 Rev. *M Page 4 of 19 CY62128EV30 MoBL® Capacitance Parameter [8] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 32-pin TSOP I 32-pin SOIC 32-pin STSOP Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 °C/W 3.42 25.86 3.59 °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC R2 30 pF INCLUDING JIG AND SCOPE 90% 10% GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.50 V 3.0 V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05579 Rev. *M Page 5 of 19 CY62128EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [9] Max Unit 1.5 – – V – – 3 µA VDR VCC for data retention ICCDR[10] Data retention current tCDR[11] Chip deselect to data retention time 0 – – ns tR[12] Operation recovery time 45 – – ns VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Industrial Data Retention Waveform Figure 5. Data Retention Waveform [13] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) 100 µs. 13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 38-05579 Rev. *M Page 6 of 19 CY62128EV30 MoBL® Switching Characteristics Over the Operating Range Parameter [14, 15] Description 45 ns (Industrial) Min Max Unit Read Cycle tRC Read cycle time 45 – ns tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 45 ns tDOE OE LOW to data valid – 22 ns 5 – ns – 18 ns tLZOE tHZOE OE LOW to low Z [16] OE HIGH to high Z [16, 17] [16] tLZCE CE LOW to low Z 10 – ns tHZCE CE HIGH to high Z [16, 17] – 18 ns tPU CE LOW to power-up 0 – ns CE HIGH to power-down – 45 ns tPD Write Cycle [18, 19] tWC Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to high Z [16, 17] – 18 ns 10 – ns tLZWE WE HIGH to low Z [16] Notes 14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 4 on page 5. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 19. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 38-05579 Rev. *M Page 7 of 19 CY62128EV30 MoBL® Switching Waveforms Figure 6. Read Cycle 1 (Address Transition Controlled) [21, 22] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23, 24] 2 ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tLZCE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 20. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 22. WE is HIGH for read cycle. 23. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 24. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document Number: 38-05579 Rev. *M Page 8 of 19 CY62128EV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled) [25, 26, 27, 28] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O NOTE 29 tHD DATA VALID tHZOE Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [25, 26, 27, 28] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes 25. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 27. Data I/O is high impedance if OE = VIH. 28. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 29. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05579 Rev. *M Page 9 of 19 CY62128EV30 MoBL® Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [30, 31, 33] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 32 tHD DATA VALID tHZWE tLZWE Notes 30. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 31. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 32. During this period, the I/Os are in output state. Do not apply input signals. 33. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 38-05579 Rev. *M Page 10 of 19 CY62128EV30 MoBL® Truth Table CE1 WE OE Inputs/Outputs Mode Power [34] X X High Z Deselect/power-down Standby (ISB) [34] L X X High Z Deselect/power-down Standby (ISB) L H H L Data out Read Active (ICC) L H L X Data in Write Active (ICC) L H H H High Z Selected, outputs disabled Active (ICC) H X CE2 X Note 34. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 38-05579 Rev. *M Page 11 of 19 CY62128EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type CY62128EV30LL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) CY62128EV30LL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free) CY62128EV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 2 8 E V30 LL - 45 XX X I Temperature Grade: I = Industrial Pb-free Package Type: XX = S or Z or ZA S = 32-pin SOIC Z = 32-pin TSOP Type I ZA = 32-pin STSOP Speed Grade: 45 = 45 ns LL = Low Power Voltage Range: V30 = 3 V typical Process Technology: E = 90 nm Technology Bus Width: 8 = × 8 Density: 2 = 1-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05579 Rev. *M Page 12 of 19 CY62128EV30 MoBL® Package Diagrams Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081 51-85081 *E Document Number: 38-05579 Rev. *M Page 13 of 19 CY62128EV30 MoBL® Package Diagrams (continued) Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056 51-85056 *G Document Number: 38-05579 Rev. *M Page 14 of 19 CY62128EV30 MoBL® Package Diagrams (continued) Figure 13. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094 51-85094 *G Document Number: 38-05579 Rev. *M Page 15 of 19 CY62128EV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SOIC Small Outline Integrated Circuit mm millimeter SRAM Static Random Access Memory ns nanosecond STSOP Shrunk Thin Small Outline Package ohm TSOP Thin Small Outline Package % percent WE Write Enable pF picofarad V volt W watt Document Number: 38-05579 Rev. *M Symbol Unit of Measure Page 16 of 19 CY62128EV30 MoBL® Document History Page Document Title: CY62128EV30 MoBL®, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05579 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 285473 See ECN PCI New data sheet. *A 461631 See ECN NXR Changed status from Preliminary to Final. Removed 35 ns speed bin related information in all instances across the document. Removed “L” version of CY62128EV30 related information in all instances across the document. Removed Reverse TSOP I package related information in all instances across the document. Updated Electrical Characteristics: Changed typical value of ICC parameter from 8 mA to 11 mA corresponding to Test Condition “f = fmax”. Changed maximum value of ICC parameter from 12 mA to 16 mA corresponding to Test Condition “f = fmax”. Changed maximum value of ICC parameter from 1.5 mA to 2.0 mA corresponding to Test Condition “f = 1 MHz”. Changed typical value of ISB2 parameter from 0.5 μA to 1 μA. Changed maximum value of ISB2 parameter from 1 μA to 4 μA. Updated AC Test Loads and Waveforms: Updated Figure 4: Changed value of AC Test load Capacitance from 50 pF to 30 pF. Updated Data Retention Characteristics: Changed maximum value of ICCDR parameter from 1 µA to 3 µA corresponding to Test Condition “LL”. Updated Switching Characteristics: Changed minimum value of tLZOE parameter from 3 ns to 5 ns for 45 ns speed bin. Changed minimum value of tLZCE parameter from 6 ns to 10 ns for 45 ns speed bin. Changed maximum value of tHZCE parameter from 22 ns to 18 ns for 45 ns speed bin. Changed minimum value of tPWE parameter from 30 ns to 35 ns for 45 ns speed bin. Changed minimum value of tSD parameter from 22 ns to 25 ns for 45 ns speed bin. Changed minimum value of tLZWE parameter from 6 ns to 10 ns for 45 ns speed bin. Updated Ordering Information. *B 464721 See ECN NXR Updated Logic Block Diagram. *C 1024520 See ECN VKN Added final Automotive-A and Automotive-E information in all instances across the document. Updated Electrical Characteristics: Added Note 7 and referred the same note in ISB2 parameter. Updated Data Retention Characteristics: Added Note 10 and referred the same note in ICCDR parameter. Updated Ordering Information. *D 2257446 See ECN NXR Updated Maximum Ratings: Changed the Maximum rating of “Ambient Temperature with Power Applied” from 55 °C to +125 °C to –55 °C to +125 °C. *E 2702841 05/06/2009 VKN / PYRS *F 2781490 10/08/2009 VKN Document Number: 38-05579 Rev. *M Updated Switching Characteristics: Updated description of tPD parameter. Updated Ordering Information (Added -45SXA part). Updated Ordering Information (Included “CY62128EV30LL-45ZAXA” part). Page 17 of 19 CY62128EV30 MoBL® Document History Page (continued) Document Title: CY62128EV30 MoBL®, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05579 Rev. ECN No. Submission Date Orig. of Change *G 2934428 06/03/10 VKN Updated Truth Table: Added Note 34 and referred the same note in ‘X’ in “CE1” and “CE2” columns. Updated Package Diagrams. Updated to new template. *H 3026548 09/12/2010 AJU Updated Pin Configuration. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. *I 3115909 01/06/2011 RAME Separated Automotive and Industrial parts from this data sheet. Removed Automotive related information in all instances across the document. *J 3292906 06/25/2011 AJU Updated Functional Description: Removed the Note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com website.” and its reference. Updated Package Diagrams. Updated to new template. *K 4499499 09/11/2014 MEMJ *L 4581542 11/27/2014 VINI Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Maximum Ratings: Referred Notes 3, 4 in “Supply voltage to ground potential”. *M 4920942 09/15/2015 VINI Updated to new template. Completing Sunset Review. Document Number: 38-05579 Rev. *M Description of Change Updated Switching Characteristics: Added Note 19 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 33 and referred the same note in Figure 10. Updated Package Diagrams: spec 51-85081 – Changed revision from *C to *E. spec 51-85056 – Changed revision from *F to *G. spec 51-85094 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. Page 18 of 19 CY62128EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05579 Rev. *M Revised September 15, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 19 of 19