Features Complete Low EMI Switch Mode Power Supply n EN55022 Class B Compliant n Wide Input Voltage Range: 5V to 36V n 3.3V to 15V Output Voltage Range n 5A DC, 7A Peak Output Current n Low Input and Output Referred Noise n Output Voltage Tracking and Margining n Power Good Tracks with Margining n PLL Frequency Synchronization n±1.5% Set Point Accuracy n Current Foldback Protection (Disabled at Start-Up) n Parallel/Current Sharing n Ultrafast Transient Response n Current Mode Control n Programmable Soft-Start n Output Overvoltage Protection n –55°C to 125°C Operating Temperature Range (LTM4612MPV) n Small Surface Mount Footprint, Low Profile (15mm × 15mm × 2.8mm) LGA Package n Applications Telecom and Networking Equipment Industrial and Avionic Equipment n RF Systems n n LTM4612 EN55022B Compliant 36VIN, 15VOUT, 5A, DC/DC µModule Regulator Description The LTM®4612 is a EN55022 Class B certified high voltage input and output, 5A switching mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V, the LTM4612 supports an output voltage range of 3.3V to 15V, set by a single resistor. Only bulk input and output capacitors are needed to finish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)—see Figures 4 and 8. Furthermore, the DC/DC µModule® regulator can be synchronized with an external clock to reduce undesirable frequency harmonics and allow PolyPhase® operation for high load currents. The LTM4612 is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point-of-load regulation. The LTM4612 is Pb-free and RoHS compliant. L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and µModule are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Radiated Emission Scan at 24VIN, 5VOUT/5A 5V/5A Ultralow Noise µModule with 7V to 36V Input 70 60 CLOCK SYNC 2M 100k CIN 0.01µF 10µF 50 VIN PLLIN VOUT PGOOD RUN LTM4612 COMP INTVCC DRVCC fSET TRACK/SS VD SGND 100pF VFB FCB MARG0 MARG1 MPGM PGND 13.7k MARGIN CONTROL 392k 5% MARGIN 4612 TA01 VOUT 5V 5A COUT EN55022 CLASS B LIMIT 40 dBµV/m VIN 7V TO 36V 30 20 10 0 –10 30 226.2 422.4 618.6 814.8 1010 128.1 324.3 520.5 716.7 912.9 FREQUENCY (MHz) 4612 TA01b 4612fb 1 LTM4612 Absolute Maximum Ratings Pin Configuration (Note 1) TOP VIEW INTVCC PLLIN TRACK/SS RUN COMP MPGM INTVCC, DRVCC.............................................. –0.3V to 6V VOUT............................................................ –0.3V to 16V PLLIN, FCB, TRACK/SS, MPGM, MARG0, MARG1, PGOOD.....................–0.3V to INTVCC + 0.3V RUN.............................................................. –0.3V to 5V VFB, COMP................................................. –0.3V to 2.7V VIN , VD........................................................ –0.3V to 36V Internal Operating Temperature Range (Note 2) E and I Grades.................................... –40°C to 125°C MP Grade............................................ –55°C to 125°C Junction Temperature............................................ 125°C Storage Temperature Range................... –55°C to 125°C A VIN B BANK 1 C D E PGND BANK 2 F G H J VOUT K BANK 3 L M VD SGND fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB 1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g order information LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM4612EV#PBF LTM4612EV#PBF LTM4612V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C LTM4612IV#PBF LTM4612IV#PBF LTM4612V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C LTM4612MPV#PBF LTM4612MPV#PBF LTM4612MPV 133-Lead (15mm × 15mm × 2.8mm) LGA –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ Electrical Characteristics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted (Note 2). Per Typical Application (front page) configuration. SYMBOL PARAMETER VIN(DC) Input DC Voltage VOUT(DC) Output Voltage CONDITIONS CIN = 10µF × 3, COUT = 300µF; FCB = 0 VIN = 24V, VOUT = 12V, IOUT = 0A VIN = 36V, VOUT=12V, IOUT = 0A MIN l 5 l l 11.83 11.83 TYP MAX UNITS 36 V 12.07 12.07 12.31 12.31 V V 4.8 V Input Specifications VIN(UVLO) Undervoltage Lockout Threshold IOUT = 0A 3.2 IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A; CIN = 10µF × 2, COUT = 200µF; VOUT = 12V VIN = 24V VIN = 36V 0.6 0.7 A A 4612fb 2 LTM4612 Electrical Characteristics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted (Note 2). Per Typical Application (front page) configuration. SYMBOL PARAMETER CONDITIONS IQ(VIN) Input Supply Bias Current VIN = 36V, VOUT = 12V, Switching Continuous VIN = 24V, VOUT = 12V, Switching Continuous Shutdown, RUN = 0, VIN = 36V MIN IS(VIN) Input Supply Current VIN = 36V, VOUT = 12V, IOUT = 5A VIN = 24V, VOUT = 12V, IOUT = 5A VINTVCC Internal VCC Voltage VIN = 36V, RUN > 2V, IOUT = 0A 4.7 0 TYP MAX 57 48 50 mA mA µA 1.85 2.72 5 UNITS A A 5.3 V 5 A Output Specifications IOUT(DC) Output Continuous Current Range VIN = 24V, VOUT = 12V (Note 4) DVOUT(LINE) VOUT Line Regulation Accuracy VOUT = 12V, FCB = 0V, VIN = 22V to 36V, IOUT = 0A l 0.05 0.3 % DVOUT(LOAD) VOUT Load Regulation Accuracy VOUT = 12V, FCB = 0V, IOUT = 0A to 5A (Note 4) VIN = 36V VIN = 24V l l 0.3 0.3 0.6 0.6 % % VIN(AC) Input Ripple Voltage VOUT(AC) Output Ripple Voltage IOUT = 0A, CIN = 2 × 10µF X5R Ceramic and 1 × 100µF Electrolytic, 1 × 10µF X5R Ceramic on VD Pins VIN = 24V, VOUT = 5V VIN = 24V, VOUT = 12V 7.2 3.4 mVP-P mVP-P IOUT = 0A, COUT = 2 × 22µF, 2 × 47µF X5R Ceramic VIN = 24V, VOUT = 5V VIN = 24V, VOUT = 12V 17.5 12.5 mVP-P mVP-P fS Output Ripple Voltage Frequency IOUT = 1A, VIN = 24V, VOUT = 12V 940 kHz DVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF COUT = 200µF, VOUT = 12V, IOUT = 0A VIN = 36V VIN = 24V 20 20 mV mV tSTART Turn-On Time, TRACK/SS = Open COUT = 300µF, VOUT = 12V, IOUT = 1A Resistive Load VIN = 36V VIN = 24V 0.5 0.5 ms ms 153 mV 37 µs 9 9 A A DVOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 2 × 22µF Ceramic, 150µF Bulk VIN = 24V, VOUT = 12V tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 24V IOUT(PK) Output Current Limit COUT = 200µF VIN = 36V, VOUT = 12V VIN = 24V, VOUT = 12V VFB Voltage at VFB Pin IOUT = 0A, VOUT = 12V Control Section VRUN RUN Pin On/Off Threshold ISS / TRACK Soft-Start Charging Current VFCB Forced Continuous Threshold IFCB Forced Continuous Pin Current tON(MIN) l 0.591 0.6 0.609 V 1 1.5 1.9 V –1 –1.5 –2 µA 0.57 0.6 0.63 V VFCB = 0V –1 –2 µA Minimum On-Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off-Time (Note 3) 250 400 RPLLIN PLLIN Input Resistor VSS/TRACK = 0V 50 ns kW 4612fb 3 LTM4612 Electrical Characteristics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted (Note 2). Per Typical Application (front page) configuration. SYMBOL PARAMETER CONDITIONS IDRVCC Current into DRVCC Pin VOUT = 12V, IOUT = 1A MIN RFBHI Resistor Between VOUT and VFB Pins VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V 99.5 TYP MAX 22 30 UNITS mA 100 100.5 kW PGOOD DVFBH PGOOD Upper Threshold VFB Rising 7 10 13 % DVFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 % DVFB(HYS) PGOOD Hysteresis VFB Returning 1.5 VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4612E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4612I is guaranteed to meet specifications over the % 0.4 V –40°C to 125°C internal operating temperature range. The LTM4612MP is guaranteed and tested over the full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See the Output Current Derating curves for different VIN, VOUT and TA. 4612fb 4 LTM4612 Typical Performance Characteristics (Refer to Figure 18) 95 Efficiency vs Load Current with 5VOUT (FCB = 0) 100 95 90 95 90 85 90 80 75 70 65 5VIN 3.3VOUT 12VIN 3.3VOUT 24VIN 3.3VOUT 36VIN 3.3VOUT 60 55 50 0 1 2 3 LOAD CURRENT (A) 75 70 65 60 50 4612 G01 0 1 2 3 LOAD CURRENT (A) 85 80 75 70 65 50 4612 G02 Transient Response from 12VIN to 3.3VOUT Efficiency vs Load Current with 15VOUT (FCB = 0, Refer to Figure 20) 20VIN 12VOUT 24VIN 12VOUT 28VIN 12VOUT 36VIN 12VOUT 55 5 4 Efficiency vs Load Current with 12VOUT (FCB = 0) 60 12VIN 5VOUT 24VIN 5VOUT 36VIN 5VOUT 55 5 4 80 EFFICIENCY (%) 85 EFFICIENCY (%) EFFICIENCY (%) 100 Efficiency vs Load Current with 3.3VOUT (FCB = 0) 0 1 2 3 LOAD CURRENT (A) 5 4 4612 G03 Transient Response from 12VIN to 5VOUT 100 95 EFFICIENCY (%) 90 85 80 2A/DIV 2A/DIV 100mV/DIV 100mV/DIV 75 70 28VIN 15VOUT 32VIN 15VOUT 36VIN 15VOUT 65 60 0 1 2 3 LOAD CURRENT (A) 50µs/DIV 5 4 4612 G04 Transient Response from 24VIN to 12VOUT 50µs/DIV 4612 G05 4612 G06 LOAD STEP: 0A to 3A COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS LOAD STEP: 0A to 3A COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS Start-Up with 24VIN to 12VOUT at IOUT = 0A Start-Up with 24VIN to 12VOUT at IOUT = 5A IIN 0.2A/DIV 2A/DIV IIN 1A/DIV 200mV/ DIV VOUT 5V/DIV 50µs/DIV 4612 G07 LOAD STEP: 0A to 3A COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS VOUT 5V/DIV 500µs/DIV 4612 G08 SOFT-START CAPACITOR: 3.9nF CIN = 3 × 10µF CERAMIC CAPACITORS AND 1 × 47µF OSCON CAPACITOR 500µs/DIV 4612 G09 SOFT-START CAPACITOR: 3.9nF CIN = 3 × 10µF CERAMIC CAPACITORS AND 1 × 47µF OSCON CAPACITOR 4612fb 5 LTM4612 Typical Performance Characteristics Start-Up with 24VIN to 12VOUT at IOUT = 5A, TA = –55°C Short-Circuit with 24VIN to 12VOUT at IOUT = 0A Short-Circuit with 24VIN to 12VOUT at IOUT = 5A IIN 2A/DIV IIN 0.2A/DIV VOUT 5V/DIV VOUT 5V/DIV VOUT 5V/DIV IIN 1A/DIV 500µs/DIV 36 30 20µs/DIV 4612 G11 4612 G12 COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS VIN to VOUT Step-Down Ratio Input Ripple Output Ripple SEE FREQUENCY ADJUSTMENT SECTION FOR OPERATIONS OUTSIDE THIS REGION 24 VIN (V) 50µs/DIV 4612 G10 SOFT-START CAPACITOR: 3.9nF CIN = 3 × 10µF CERAMIC CAPACITORS AND 1 × 47µF OSCON CAPACITOR OPERATING REGION WITH DEFAULT FREQUENCY 18 50mV/DIV 10mV/DIV 12 6 0 3.3 4 6 8 10 VOUT (V) 12 14 15 4612 G13 1µs/DIV 4612 G14 VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD CIN = 3 × 10µF 50V CERAMIC 1 × 100µF BULK 1µs/DIV 4612 G15 VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD COUT = 2 × 22µF 16V CERAMIC AND 2 × 47µF 16V CERAMIC 4612fb 6 LTM4612 Pin Functions (See Package Description for Pin Assignments) VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. TRACK/SS (Pin A9): Output Voltage Tracking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins (see the LTM4612 Pin Configuration below). VD (Pins B7, C7): Top FET Drain Pins. Add more capacitors between VD and ground to handle the input RMS current and reduce the input ripple further. DRVCC (Pins C10, E11, E12): These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves efficiency at higher input voltages by reducing power dissipation in the module. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. May be left open if margining is not desired. See the Applications Information section. To parallel LTM4612s, each requires an individual MPGM resistor. Do not tie MPGM pins together. INTVCC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTVCC. See the Applications Information section. fSET (Pin B12): Frequency Set Internally to ~850kHz to 900kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. INTVCC PLLIN TRACK/SS RUN COMP MPGM TOP VIEW A VIN B BANK 1 C D E PGND BANK 2 F G H J VOUT K BANK 3 L M VD SGND fSET MARG0 MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB 1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) LTM4612 Pin Configuration 4612fb 7 LTM4612 Pin Functions VFB (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT with a 100k 0.5% precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. COMP (Pins A11, D11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. PGOOD (Pin G12): Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires. MARG1 (Pins C11, D12): MSB Logic Input for the Margining Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. RUN (Pins A10, B9): Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be accomplished with a resistor from VIN to this pin that is has a 5.1V zener to ground. Maximum pin voltage is 5V. NC (Pins J12, K12, L12): No Connect Pins. Leave floating. 4612fb 8 LTM4612 Block Diagram > 1.9V = ON < 1V = OFF MAX = 5V VOUT RUN PGOOD 5.1V ZENER COMP 1µF INPUT FILTER + VIN 20V TO 36V CIN 100k VD INTERNAL COMP CD POWER CONTROL SGND M1 2.7µH VOUT 12V AT 4A MARG1 MARG0 VFB RFB 5.23k 50k 50k fSET M2 NOISE CANCELLATION 10µF 93.1k + COUT PGND FCB 10k MPGM TRACK/SS CSS PLLIN 4.7µF 50k INTVCC 4612 F01 DRVCC Figure 1. Simplified Block Diagram decoupling requirements Specifications are at TA = 25°C. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS MIN CIN External Input Capacitor Requirement (VIN = 20V to 36V, VOUT = 12V) IOUT = 4A 20 COUT External Output Capacitor Requirement (VIN = 20V to 36V, VOUT = 12V) IOUT = 4A 100 TYP MAX UNITS µF 150 µF 4612fb 9 LTM4612 Operation Power Module Description The LTM4612 is a standalone nonisolated switching mode DC/DC power supply. It can deliver 5A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 3.3VDC to 15VDC over a 5V to 36V wide input voltage. The typical application schematic is shown in Figure 18. The LTM4612 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load at 12V output. With current mode control and internal feedback loop compensation, the LTM4612 module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Moreover, foldback current limiting is provided in an overcurrent condition while VFB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input filter and noise cancellation circuitry reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) meets the limits of EN55022 Class B. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At light load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous mode (CCM) by setting FCB pin higher than 0.6V. When the DRVCC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at higher input voltages. The MPGM, MARG0, and MARG1 pins are used to support output voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. Applications Information The typical LTM4612 application circuit is shown in Figure 18. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. VIN to VOUT Stepdown Ratios There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristic curve labeled “VIN to VOUT Step-Down Ratio.” Note that additional thermal derating may be applied. See the Thermal Considerations and Output Current Derating section in this data sheet. 4612fb 10 LTM4612 Applications Information Output Voltage Programming and Margining RPGM resistor on the MPGM pin programs the current. Calculate VOUT(MARGIN): The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 100k internal feedback resistor connects the VOUT and VFB pins together. Adding a resistor, RFB, from the VFB pin to the SGND pin programs the output voltage. VOUT = 0.6V • 100k + RFB RFB 100k VOUT −1 0.6V RFB (kW) 3.3 22.1 5 13.7 RPGM = VOUT 1.18V • • 10k 0.6V VOUT(MARGIN) Where RPGM is the resistor value to place on the MPGM pin to ground. The output margining will be ± margining of the value. This is controlled by the MARG0 and MARG1 pins. See the truth table below: Table 1. RFB Standard 1% Resistor Values vs VOUT VOUT (V) %VOUT • VOUT 100 Where %VOUT is the percentage of VOUT to be margined, and VOUT(MARGIN) is the margin quantity in volts: or equivalently, RFB = VOUT(MARGIN) = 6 11 8 10 8.06 6.34 12 5.23 15 MARG1 MARG0 MODE 4.12 LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN 14 4.42 The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference ± offset for margining. A 1.18V reference divided by the Table 2. Output Voltage Response vs Component Matrix (Refer to Figure 20) TYPICAL MEASURED VALUES VENDORS PART NUMBER VENDORS PART NUMBER Murata GRM32ER61C476KEI5L (47µF, 16V) Murata GRM32ER71H106K (10µF, 50V) Murata GRM32ER61C226KE20L (22µF, 16V) TDK C3225X5RIC226M (22µF, 16V) VOUT (V) CIN (CERAMIC) CIN (BULK) COUT1 (CERAMIC) COUT2 (BULK) VIN (V) DROOP (mV) PEAK-TOPEAK (mV) RECOVERY TIME (µs) LOAD STEP (A/µs) RFB (kΩ) 5 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 12 86 156 26 3 13.7 5 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 12 86 178 14.8 3 13.7 5 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 24 83 166 27 3 13.7 5 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 24 86 169 14.8 3 13.7 13.7 5 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 36 86 178 25 3 5 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 36 86 172 15.2 3 13.7 10 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 24 111 209 30 3 6.34 10 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 24 171 325 35 3 6.34 10 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 36 108 197 35 3 6.34 10 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 36 153 288 39 3 6.34 12 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 24 153 281 37 3 5.23 12 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 36 184 375 34.4 3 5.23 15 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 25V 28 178 338 70 3 4.12 15 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 36 134 250 70 3 4.12 4612fb 11 LTM4612 Applications Information Operating Frequency The operating frequency of the LTM4612 is optimized to achieve the compact package size and the minimum output ripple voltage while still providing high efficiency. As shown in Figure 2, the frequency is linearly increased with larger output voltages to keep the low output current ripple. Figure 3 shows the inductor current ripple DI with different output voltages. In most applications, no additional frequency adjusting is required. If lower output ripple is required, the operating frequency f can be increased by adding a resistor RfSET between fSET pin and SGND, as shown in Figure 19. f= VOUT 1.5 • 10−10 (RfSET || 93.1k ) For output voltages more than 12V, the frequency can be higher than 1MHz, thus reducing the efficiency significantly. Additionally, the 500ns minimum off time (400ns + 100ns for margin) normally limits the operation when the input voltage is close to the output voltage. Therefore, it is recommended to lower the frequency in these conditions by connecting a resistor (RfSET) from the fSET pin to VIN, as shown in Figure 20. VOUT f= ⎛3•R ⎞ fSET • 93.1k 5 • 10−11 ⎜ ⎟ RfSET − 2 • 93.1k ⎠ ⎝ The load current can affect the frequency due to its constant on-time control. If constant frequency is a necessity, the PLLIN pin can be used to synchronize the frequency of the LTM4612 to an external clock, as shown in Figures 21 to 23. 1200 INDUCTOR CURRENT RIPPLE ∆I (A) 3.5 FREQUENCY (kHz) 1000 800 600 400 200 2 4 6 10 8 VOUT (V) 12 14 16 4612 F02 Figure 2. Operating Frequency vs Output Voltage 3.0 VIN = 36V 2.5 2.0 VIN = 28V VIN = 20V 1.5 1.0 0.5 2 4 6 8 10 VOUT (V) 12 14 16 4612 F03 Figure 3. Inductor Current Ripple vs Output Voltage 4612fb 12 LTM4612 Applications Information Input Capacitors LTM4612 is designed to achieve the low input radiated EMI noise due to the fast switching of turn-on and turn-off. In the LTM4612, a high-frequency inductor is integrated into the input line for noise attenuation. VD and VIN pins are available for external input capacitors to form a high frequency π filter. As shown in Figure 18, the ceramic capacitor C1 on the VD pins is used to handle most of the RMS current into the converter, so careful attention is needed for capacitor C1 selection. For a buck converter, the switching duty cycle can be estimated as: To attenuate the high frequency noise, extra input capacitors should be connected to the VIN pads and placed before the high frequency inductor to form the π filter. One of these low ESR ceramic input capacitors is recommended to be close to the connection into the system board. A large bulk 100µF capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. Figure 4 shows the radiated EMI test results to meet the EN55022 Class B limit. For different applications, input capacitance may be varied to meet different radiated EMI limits. 70 60 V D = OUT VIN In this equation, h is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. EN55022 CLASS B LIMIT 40 dBµV/m Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: IOUT(MAX) ICIN(RMS) = • D • (1– D) h 50 30 20 10 0 –10 30 226.2 422.4 618.6 814.8 1010 128.1 324.3 520.5 716.7 912.9 FREQUENCY (MHz) 4612 F04 Figure 4. Radiated Emission Scan with 24VIN to 5VOUT at 5A (2 × 10µF Ceramic Capacitors on VIN Pads and 1 × 10µF Ceramic Capacitor on VD Pads) In a typical 5A output application, one very low ESR, X5R or X7R, 10µF ceramic capacitor is recommended for C1. This decoupling capacitor should be placed directly adjacent to the module VD pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10µF ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. 4612fb 13 LTM4612 Applications Information 1.00 0.95 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.90 0.85 RATIO = PEAK-TO-PEAK OUTPUT RIPPLE CURRENT DIr 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VO/VIN) 4612 F05 Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI Output Capacitors The LTM4612 is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical capacitance is 150µF if all ceramic output capacitors are used. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 2A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. Multiphase operation with multiple LTM4612 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 5 for the normalized output ripple current versus the duty cycle. Figure 5 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each phase’s inductor ripple current DIr at zero duty cycle is ~4.3A for a 36V to 12V design. The duty cycle is about 0.33. The 2-phase curve has a ratio of ~0.33 for a duty cycle of 0.33. This 0.33 ratio of output ripple current to the inductor ripple current DIr at 4.3A equals 1.4A of the output ripple current (DIL). The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. The equation is: ⎛ ⎞ DIL DVOUT(P-P) ≈ ⎜ ⎟ + ESR • DIL ⎝ 8 • f • N • COUT ⎠ where f is the frequency and N is the number of paralleled phases. 4612fb 14 LTM4612 Applications Information Fault Conditions: Current Limit and Overcurrent Foldback Output Voltage Tracking LTM4612 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady state operation, but also in transient. To further limit current in the event of an overload condition, the LTM4612 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. Soft-Start and Tracking The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5µA current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference plus or minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: tSOFTSTART ≅ 0.8 • (0.6 ± 0.6 • VOUT Margin %) • CSS 1.5µA If the RUN pin falls below 2.5V, then the soft-start pin is reset to allow for the proper soft-start again. Current foldback and force continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp rising time, so that another regulator can be easily tracked. Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. Figure 6 shows an example of coincident tracking where the master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 7 shows the coincident output tracking. Tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK pin. The TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: MR • 100k = R2 SR where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R2 is equal the 100k. R1 is derived from equation: R1= 0.6V VFB VFB VTRACK + − 100k RFB R2 VIN 10µF 100k VD PGOOD CIN MASTER OUTPUT TRACK CONTROL R1 5.23k PLLIN VOUT RUN VFB COMP FCB INTVCC R2 100k VIN LTM4612 DRVCC MASTER OUTPUT COUT MARG0 SLAVE OUTPUT OUTPUT VOLTAGE MARG1 fSET TRACK/SS SGND SLAVE OUTPUT MPGM PGND RFB 5.23k 4612 F06 TIME Figure 6. Coincident Tracking 4612 F07 Figure 7. Coincident Output Tracking 4612fb 15 LTM4612 Applications Information where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since R2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R1 is equal to RFB with VFB = VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R2 can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then R2 = 125k. Solve for R1 to equal to 5.18k. Each of the TRACK pins will have the 1.5µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 100k is used then a 10k can be used to reduce the TRACK pin offset to a negligible value. RUN Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with 5V logic levels. The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin. The equation for UVLO threshold: VUVLO = R A + RB • 1.5V RB where RA is the top resistor, and RB is the bottom resistor. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point, and tracks with margining. COMP Pin The pin is the external compensation pin. The module has already been internally compensated for most output voltages. LTpowerCAD™ from Linear Technology is available for more control loop optimization. FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. PLLIN Pin The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is ±30% around the set operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns. The clock high level must be greater than 1.7V and clock low level below 0.3V. During the start-up of the regulator, the phase-locked loop function is disabled. INTVCC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4612 can be directly powered by VIN . The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA • (VIN – 5V) The LTM4612 also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect the DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. 4612fb 16 LTM4612 Applications Information Parallel Operation Thermal Considerations and Output Current Derating The LTM4612 device is an inherently current mode controlled device. This allows the paralleled modules to have very good current sharing and balanced thermal on the design. Figure 21 shows a schematic of the parallel design. The voltage feedback equation changes with the variable N as modules are paralleled. The equation: In different applications, LTM4612 operates in a variety of thermal environments. The maximum output current is limited by the environment thermal condition. Sufficient cooling should be provided to help ensure reliable operation. When the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. 100k N R FB = VOUT −1 0.6V N is the number of paralleled modules. Radiated EMI Noise High radiated EMI noise is a disadvantage for switching regulators by nature. Fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. LTM4612 integrates the feature to minimize the radiated EMI noise to meet the most applications with low noise requirements. An optimized gate driver for the MOSFET and a noise cancellation network are installed inside the LTM4612 to achieve the low radiated EMI noise. Figure 8 shows a typical example for the LTM4612 to meet the Class B of EN55022 radiated emission limit. 70 60 The power loss curves in Figures 9 and 10 can be used in coordination with the load current derating curves in Figures 11 to 16 for calculating an approximate θJA for the module. Graph designation delineates between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 125°C maximum. This will maintain the maximum operating temperature below 125°C. Each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate θJA of the condition. Each figure has three curves that are taken at three different air flow conditions. Each of the derating curves in Figures 11 to 16 can be used with the appropriate power loss curve in either Figure 9 or Figure 10 to derive an approximate θJA. Table 3 provides the approximate θJA for Figures 11 to 16. A complete explanation of the thermal characteristics is provided in the thermal application note, AN110. 50 EN55022 CLASS B LIMIT dBµV/m 40 30 20 10 0 –10 30 226.2 422.4 618.6 814.8 1010 128.1 324.3 520.5 716.7 912.9 FREQUENCY (MHz) 4612 F08 Figure 8. Radiated Emission Scan with 24VIN to 5VOUT at 5A Measured in 10 Meter Chamber 4612fb 17 LTM4612 Applications Information 6 5 POWER LOSS (W) 4 3 24VIN TO 12VOUT 2 4.0 LOAD CURRENT (A) 36VIN TO 15VOUT POWER LOSS (W) 200 LFM 4.5 5 4 36VIN TO 5VOUT 3 2 1 0 5.0 6 2 1 3 4 0 5 LOAD CURRENT (A) 400LFM 3.0 2.5 2.0 1.5 1.0 1 0 0LFM 3.5 0.5 0 2 1 3 4 LOAD CURRENT (A) 4612 F09 0 5 25 35 4612 F10 45 55 65 75 85 95 AMBIENT TEMPERATURE (°C) 105 4612 F11 Figure 9. Power Loss at 12VOUT and 15VOUT 4.0 0LFM 3.5 4.0 400LFM 3.0 2.5 2.0 1.5 5.0 200 LFM 4.5 LOAD CURRENT (A) LOAD CURRENT (A) 5.0 200 LFM 4.5 Figure 11. No Heat Sink with 36VIN to 5VOUT 0LFM 3.5 4.0 400LFM 3.0 2.5 2.0 1.5 2.5 2.0 1.5 1.0 0.5 0.5 0.5 35 45 55 65 75 85 95 AMBIENT TEMPERATURE (°C) 105 0 35 25 45 55 65 75 85 95 AMBIENT TEMPERATURE (°C) 4612 F12 5.0 4.5 4.5 4.0 400LFM LOAD CURRENT (A) LOAD CURRENT (A) 3.5 200LFM 3.0 2.5 2.0 1.5 95 200LFM 400LFM 2.5 1.5 0.5 45 55 65 75 85 AMBIENT TEMPERATURE (°C) 0 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (°C) 4612 F15 Figure 15. No Heat Sink with 36VIN to 15VOUT 105 2.0 1.0 35 45 55 65 75 85 95 AMBIENT TEMPERATURE (°C) 3.0 0.5 25 35 Figure 14. BGA Heat Sink with 24VIN to 12VOUT 0LFM 3.5 1.0 0 25 4612 F14 Figure 13. No Heat Sink with 24VIN to 12VOUT 5.0 0LFM 0 4612 F13 Figure 12. BGA Heat Sink with 36VIN to 5VOUT 4.0 105 400LFM 3.0 1.0 25 0LFM 3.5 1.0 0 200 LFM 4.5 LOAD CURRENT (A) 5.0 Figure 10. Power Loss at 5VOUT 95 4612 F16 Figure 16. BGA Heat Sink with 36VIN to 15VOUT 4612fb 18 LTM4612 Applications Information Table 3. 12V and 15V Outputs DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W) Figures 11, 13, 15 24, 36 Figure 9 0 None 13 Figures 11, 13, 15 24, 36 Figure 9 200 None 9.3 Figures 11, 13, 15 24, 36 Figure 9 400 None 8.3 Figures 12, 14, 16 24, 36 Figure 9 0 BGA Heat Sink 12.2 Figures 12, 14, 16 24, 36 Figure 9 200 BGA Heat Sink 8.6 Figures 12, 14, 16 24, 36 Figure 9 400 BGA Heat Sink 7.7 VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W) Table 4. 5V Output DERATING CURVE Figure 11 36 Figure 10 0 None 14.9 Figure 11 36 Figure 10 200 None 11.1 Figure 11 36 Figure 10 400 None 10 Figure 12 36 Figure 10 0 BGA Heat Sink 14 Figure 12 36 Figure 10 200 BGA Heat Sink 10.4 Figure 12 36 Figure 10 400 BGA Heat Sink 9.3 Heat Sink Manufacturer Wakefield Engineering Part No: LTN20069 Phone: 603-635-2800 4612fb 19 LTM4612 Applications Information Safety Considerations The LTM4612 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. Layout Checklist/Example The high integration of LTM4612 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. • Place high frequency ceramic input and output capacitors next to the VD, PGND and VOUT pins to minimize high frequency noise. VIN CIN • Place a dedicated power ground layer underneath the unit. • Use round corners for the PCB copper layer to minimize the radiated noise. • To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. • Do not put vias directly on pads. • If vias are placed onto the pads, the the vias must be capped. • Interstitial via placement can also be used if necessary. • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. • Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout. CIN GND SIGNAL GND COUT COUT VOUT 4612 F17 Figure 17. Recommended PCB Layout 4612fb 20 LTM4612 Applications Information PULL-UP SUPPLY ≤ 5V CLOCK SYNC VIN 22V TO 36V R4 100k R5 2M C1 10µF 50V R3 100k CIN 10µF 50V CERAMIC VD VIN PLLIN VOUT PGOOD RUN LTM4612 ON/OFF VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM C4 SGND PGND 0.01µF C3 22pF RFB 5.23k MARGIN CONTROL COUT1 22µF 16V VOUT 12V COUT2 5A 220µF 16V + REFER TO TABLE 2 R1 392k 5% MARGIN 4612 F18 Figure 18. Typical 22V to 36VIN, 12V at 5A Design PULL-UP SUPPLY ≤ 5V CLOCK SYNC VIN 5V TO 36V R4 100k R3 100k ON/OFF CIN 10µF 50V CERAMIC EXTERNAL 5V SUPPLY IMPROVES EFFICIENCY— ESPECIALLY FOR HIGH INPUT VOLTAGES C1 10µF 50V VD VIN PLLIN VOUT PGOOD RUN VFB COMP LTM4612 INTVCC FCB C3 22pF RFB 22.1k DRVCC RfSET 191k 1% fSET TRACK/SS C4 0.01µF SGND MARG0 MARG1 MPGM PGND MARGIN CONTROL COUT1 22µF 6.3V + COUT2 220µF 6.3V VOUT 3.3V 5A REFER TO TABLE 2 R1 392k 5% MARGIN 4612 F19 Figure 19. Typical 5V to 36VIN, 3.3V at 5A Design with 400kHz Frequency 4612fb 21 LTM4612 Applications Information PULL-UP SUPPLY ≤ 5V CLOCK SYNC VIN 26V TO 36V R4 100k RfSET 806k, 1% CIN 10µF 50V CERAMIC R3 100k C1 10µF 50V VD VIN PLLIN VOUT PGOOD RUN LTM4612 ON/OFF VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND C4 0.01µF C3 22pF COUT1 22µF 16V RFB 4.12k + COUT2 220µF 16V VOUT 15V 4A MARGIN CONTROL R1 392k 5% MARGIN 4612 F20 Figure 20. 26V to 36VIN, 15V at 4A Design with Reduced Frequency PULL-UP SUPPLY ≤ 5V VIN 20V TO 36V R4 100k C2 10µF 50V + 2-PHASE OSCILLATOR R5 124k C11 0.1µF C5 100µF 50V R2 100k C1 10µF 50V CLOCK SYNC 0° PHASE VD VIN PLLIN PGOOD VOUT RUN LTM4612 VFB COMP FCB INTVCC DRVCC MARG0 fSET TRACK/SS MARG1 MPGM C7 SGND PGND 0.33µF VOUT 12V, 10A C6 47pF C3 22µF 16V + C4 220µF 16V C9 22µF 16V + C10 220µF 16V MARGIN CONTROL R1 392k RFB 2.61k 5% MARGIN V+ OUT1 GND OUT2 SET MOD RFB = C11 10µF 50V LTC6908-1 C8 10µF 50V CLOCK SYNC 180° PHASE VD VIN PLLIN VOUT PGOOD RUN LTM4612 VFB COMP FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND 100k/N VOUT –1 0.6V R6 392k 4612 F21 Figure 21. 2-Phase, Parallel 12V at 10A Design 4612fb 22 LTM4612 Applications Information PULL-UP SUPPLY ≤ 5V VIN 22V TO 36V R4 100k + C5 100µF 50V R2 100k C2 10µF 50V C7 0.15µF C1 10µF 50V VD CLOCK SYNC 0° PHASE VIN 2-PHASE OSCILLATOR V+ R5 118k C11 0.1µF OUT1 GND OUT2 SET MOD PLLIN PGOOD VOUT RUN LTM4612 VFB COMP FCB INTVCC DRVCC MARG0 fSET TRACK/SS MARG1 MPGM SGND PGND 12V AT 5A C6 22pF C3 22µF 16V + C4 220µF 16V MARGIN CONTROL RFB1 5.23k R1 392k 5% MARGIN PULL-UP SUPPLY ≤ 5V LTC6908-1 R3 100k R7 100k 12V TRACK C8 10µF 50V R8 100k R9 6.34k C11 10µF 50V CLOCK SYNC 180° PHASE VD VIN PLLIN VOUT PGOOD RUN LTM4612 VFB COMP FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND 10V AT 5A C1 22pF C9 22µF 16V + C10 220µF 16V MARGIN CONTROL R6 392k RFB2 6.34k 4612 F22 Figure 22. 2-Phase, 12V and 10V at 5A Design 4612fb 23 LTM4612 Applications Information 5V VIN 7V TO 36V R2 100k R4 100k C2 10µF 50V + C5 100µF 50V RfSET1 150k C7 0.15µF C1 10µF 50V PLLIN VD VIN VOUT PGOOD RUN LTM4612 VFB COMP INTVCC FCB DRVCC MARG0 fSET MARG1 TRACK/SS MPGM SGND PGND 2-PHASE OSCILLATOR R5 200k C11 0.1µF CLOCK SYNC 0° PHASE 5V AT 5A C6 22pF C3 22µF 6.3V + C4 220µF 6.3V MARGIN CONTROL R1 392k RFB1 13.7k 5% MARGIN V+ OUT1 GND OUT2 SET MOD 3.3V LTC6908-1 R3 100k R7 100k 5V TRACK C8 10µF 50V R8 100k R9 22.1k RfSET2 100k C11 CLOCK SYNC 10µF 180° PHASE 50V VIN VD PLLIN VOUT PGOOD RUN VFB COMP LTM4612 FCB INTVCC DRVCC fSET TRACK/SS SGND MARG0 MARG1 MPGM PGND 3.3V AT 5A C1 22pF C9 22µF 6.3V + C10 220µF 6.3V MARGIN CONTROL R6 392k RFB2 22.1k 4612 F23 Figure 23. 2-Phase, 5V and 3.3V at 5A Design with 500kHz Frequency 4612fb 24 LTM4612 Package Description Pin Assignment Tables (Arranged by Pin Function) PIN NAME PIN NAME A1 A2 A3 A4 A5 A6 VIN VIN VIN VIN VIN VIN D1 D2 D3 D4 D5 D6 PGND PGND PGND PGND PGND PGND B1 B2 B3 B4 B5 B6 VIN VIN VIN VIN VIN VIN C1 C2 C3 C4 C5 C6 VIN VIN VIN VIN VIN VIN E1 E2 E3 E4 E5 E6 E7 E8 PGND PGND PGND PGND PGND PGND PGND PGND F1 F2 F3 F4 F5 F6 F7 F8 F9 PGND PGND PGND PGND PGND PGND PGND PGND PGND G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A7 A8 A9 A10 A11 A12 INTVCC PLLIN TRACK/SS RUN COMP MPGM B7 B8 B9 B10 B11 B12 VD RUN MPGM fSET C7 C8 C9 C10 C11 C12 VD DRVCC MARG1 MARG0 D7 D8 D9 D10 D11 D12 SGND COMP MARG1 E9 E10 E11 E12 DRVCC DRVCC F10 F11 F12 VFB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB 4612fb 25 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 4 PAD 1 CORNER 15 BSC PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 X 15 BSC Y DETAIL B 2.72 – 2.92 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE LAND DESIGNATION PER JESD MO-222, SPP-010 SYMBOL TOLERANCE aaa 0.10 bbb 0.10 eee 0.05 6. THE TOTAL NUMBER OF PADS: 133 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 M L TRAY PIN 1 BEVEL COMPONENT PIN “A1” PADS SEE NOTES 1.27 BSC 13.97 BSC 0.12 – 0.28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 DETAIL A 0.27 – 0.37 SUBSTRATE eee S X Y DETAIL B MOLD CAP 0.630 ±0.025 SQ. 133x aaa Z 2.45 – 2.55 bbb Z aaa Z 0.6350 0.0000 0.6350 (Reference LTM DWG # 05-08-1766 Rev Ø) Z 26 1.9050 LGA Package 133-Lead (15mm × 15mm × 2.82mm) K G F E LTMXXXXXX µModule PACKAGE BOTTOM VIEW H D C B LGA 133 1107 REV Ø A DETAIL A PACKAGE IN TRAY LOADING ORIENTATION J 13.97 BSC 1 2 3 4 5 6 7 8 9 10 11 12 C(0.30) PAD 1 LTM4612 Package Description 4612fb 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 LTM4612 Revision History REV DATE DESCRIPTION A 03/10 Changes to Title and Description PAGE NUMBER Changes to Absolute Maximum Ratings Changes to Electrical Characteristics Text Changes to Operation Section Text Changes to Applications Information Section Changes to Figures 18, 19, 20, 21, 22 Changes to Related Parts B 05/11 Changes to the Title, Description, Features and Typical Application sections. Changes to “The l denotes...” statement and Note 2. Changes to the Pin Functions. 1 1 2, 3 10 12, 14 19, 20, 21, 22 26 1 2, 3, 4 7, 8 Changes to the Block Diagram. 9 Text changes to the Operation section. 10 Text changes to the Applications Information section. Changes to Figures 17, 19, 21, 22. Changes to the Related Parts. 10–20 20, 21, 22, 23 28 4612fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTM4612 Package Photograph 15mm 2.8mm 15mm 4612 F24 Related Parts PART NUMBER DESCRIPTION COMMENTS LTM4606 EN55022B Compliant 6A, DC/DC µModule Regulator EN55022B Compliant with PLL, Output Tracking and Margining, LTM4612 Pin Compatible LTM4613 EN55022B Compliant 36V, 8A, Step-Down µModule 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 4.3mm LGA Package Regulator with PLL, Output Tracking LTM4601/LTM4601A 12A DC/DC µModule Regulator with PLL, Output Tracking/Margining and Remote Sensing Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has No Remote Sensing, LGA Package LTM4604A Low VIN 4A DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.3mm LGA Package LTM4608A Low VIN 8A DC/DC µModule Regulator 2.7V ≤ VIN ≤ 5.5V, 0.6V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.8mm LGA Package LTM8022/LTM8023 36VIN, 1A and 2A DC/DC µModule Regulator Pin Compatible, 4.5V ≤ VIN ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package LTM4627 20VIN, 15A DC/DC Step-Down µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, 15mm × 15mm × 4.3mm LGA Package LTM4618 26VIN, 6A DC/DC Step-Down µModule Regulator with PLL, Output Tracking 4.5V ≤ VIN ≤ 26.5V, 0.8V ≤ VOUT ≤ 5V, Synchronizable, 9mm × 15mm × 4.3mm LGA Package LTM8033 EN55022B Compliant 36VIN, 3A DC/DC Step-Down µModule Regulator 3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 24V, Synchronizable, 11.25mm × 15mm × 4.3mm LGA Package 4612fb 28 Linear Technology Corporation LT 0511 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2008