CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description ■ 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) ■ 550 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW ■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1] ❐ Supports both 1.5 V and 1.8 V I/O supply ■ HSTL inputs and variable drive HSTL output buffers ■ Available in 165-Ball FBGA package (13 × 15 × 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ JTAG 1149.1 compatible test access port ■ Phase-locked loop (PLL) for accurate data placement The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C11661KV18), 9-bit words (CY7C11771KV18), 18-bit words (CY7C11681KV18), or 36-bit words (CY7C11701KV18) that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Table 1. Selection Guide Description Maximum operating frequency Maximum operating current Configurations 550 500 450 400 MHz MHz MHz MHz Unit 550 500 450 400 MHz mA x8 740 690 630 580 x9 740 690 630 580 x18 760 700 650 590 x36 970 890 820 750 With Read cycle latency of 2.5 cycles: CY7C11661KV18 – 2 M × 8 CY7C11771KV18 – 2 M × 9 CY7C11681KV18 – 1 M × 18 CY7C11701KV18 – 512 K × 36 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD. Cypress Semiconductor Corporation Document Number: 001-53199 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 31, 2011 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Logic Block Diagram (CY7C11661KV18) Write Reg CLK Gen. K DOFF Read Add. Decode K 1 M × 8 Array LD Write Reg 1 M × 8 Array Address Register Write Add. Decode 20 A(19:0) 8 Output Logic Control R/W Read Data Reg. 16 VREF R/W NWS[1:0] Control Logic 8 Reg. 8 CQ Reg. 8 CQ 8 Reg. DQ[7:0] 8 QVLD Logic Block Diagram (CY7C11771KV18) Write Reg CLK Gen. DOFF VREF R/W BWS[0] Read Add. Decode K 1 M × 9 Array K Address Register Write Reg 1 M × 9 Array LD Write Add. Decode 20 A(19:0) 9 Output Logic Control R/W Read Data Reg. 18 Control Logic 9 9 Reg. Reg. 9 Reg. 9 CQ CQ 9 DQ[8:0] QVLD Document Number: 001-53199 Rev. *I Page 2 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 CLK Gen. K Write Add. Decode K DOFF Write Reg 512 K × 18 Array Address Register LD Write Reg 512 K × 18 Array 19 A(18:0) Read Add. Decode Logic Block Diagram (CY7C11681KV18) 18 Output Logic Control R/W Read Data Reg. 36 VREF R/W BWS[1:0] Control Logic 18 18 Reg. Reg. 18 Reg. 18 CQ CQ 18 DQ[17:0] QVLD K CLK Gen. DOFF VREF R/W BWS[3:0] Write Add. Decode K Address Register Write Reg 256 K × 36 Array LD Write Reg 256 K × 36 Array 18 A(17:0) Read Add. Decode Logic Block Diagram (CY7C11701KV18) 36 Output Logic Control R/W Read Data Reg. 72 Control Logic 36 36 Reg. Reg. 36 Reg. 36 CQ CQ 36 DQ[35:0] QVLD Document Number: 001-53199 Rev. *I Page 3 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Contents Functional Overview ........................................................ 5 Read Operations ......................................................... 5 Write Operations ......................................................... 5 Byte Write Operations ................................................. 5 DDR Operation ............................................................ 5 Depth Expansion ......................................................... 5 Programmable Impedance .......................................... 5 Echo Clocks ................................................................ 5 Valid Data Indicator (QVLD) ........................................ 6 PLL .............................................................................. 6 Application Example ........................................................ 6 Truth Table ........................................................................ 7 Write Cycle Description – CY7C11661KV18 and CY7C11681KV18 ............................................................... 7 Write Cycle Descriptions – CY7C11771KV18 ................. 8 Write Cycle Descriptions – CY7C11701KV18 ................. 8 IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9 Disabling the JTAG Feature ........................................ 9 Test Access Port—Test Clock ..................................... 9 Test Mode Select (TMS) ............................................. 9 Test Data-In (TDI) ....................................................... 9 Test Data-Out (TDO) ................................................... 9 Performing a TAP Reset ............................................. 9 TAP Registers ............................................................. 9 TAP Instruction Set ..................................................... 9 TAP Electrical Characteristics ...................................... 12 TAP AC Switching Characteristics ............................... 13 Document Number: 001-53199 Rev. *I TAP Timing and Test Conditions .................................. 13 Power-up Sequence in DDR II+ SRAM ......................... 16 Power-up Sequence .................................................. 16 PLL Constraints ......................................................... 16 Maximum Ratings ........................................................... 17 Operating Range ............................................................. 17 Neutron Soft Error Immunity ......................................... 17 Electrical Characteristics ............................................... 17 DC Electrical Characteristics ..................................... 17 AC Electrical Characteristics ........................................ 19 Capacitance .................................................................... 19 Thermal Resistance ........................................................ 19 Switching Characteristics .............................................. 20 Switching Waveforms .................................................... 21 Read/Write/Deselect Sequence ................................ 21 Ordering Information ...................................................... 22 Ordering Code Definitions ......................................... 22 Package Diagram ............................................................ 23 Acronyms ........................................................................ 24 Document Conventions ................................................. 24 Units of Measure ....................................................... 24 Document History Page ................................................. 25 Sales, Solutions, and Legal Information ...................... 26 Worldwide Sales and Design Support ....................... 26 Products .................................................................... 26 PSoC Solutions ......................................................... 26 Page 4 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Functional Overview The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of two and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS, the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input and output timing are referenced from the rising edge of the input clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the input clocks (K and K). All synchronous control (R/W, LD, NWS[X:0], BWS[X:0]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C11681KV18 is described in the following sections. The same basic descriptions apply to CY7C11661KV18, CY7C11771KV18, and CY7C11701KV18. Read Operations The CY7C11681KV18 is organized internally as two arrays of 512 K × 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K and K). To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). When read access is deselected, the CY7C11681KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output following the next rising edge of the negative input clock (K). This enables a transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). Document Number: 001-53199 Rev. *I When the write access is deselected, the device ignores all inputs after the pending write operations have been completed. Byte Write Operations Byte write operations are supported by the CY7C11681KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. DDR Operation The CY7C11681KV18 enables high performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C11681KV18 requires two No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a Posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 20. Page 5 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Valid Data Indicator (QVLD) QVLD is provided on the DDR II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+. Application Example Figure 1 shows two DDR II+ used in an application. Figure 1. Application Example DQ A SRAM#1 LD R/W BWS ZQ CQ/CQ K K R = 250ohms DQ A SRAM#2 LD R/W BWS ZQ CQ/CQ K K R = 250ohms DQ Addresses BUS LD MASTER R/W (CPU or ASIC) BWS Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Document Number: 001-53199 Rev. *I Page 6 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Truth Table The truth table for the CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 follows.[2, 3, 4, 5, 6, 7] Operation K LD R/W Write cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L D(A) at K(t + 1) D(A+1) at K(t + 1) Read cycle: (2.5 cycle latency) Load address; wait two and half cycles; read data on consecutive K and K rising edges. L-H L H Q(A) at K(t + 2) Q(A+1) at K(t + 3) NOP: No operation L-H H X High Z High Z Stopped X X Previous state Previous state Standby: clock stopped DQ DQ Write Cycle Description – CY7C11661KV18 and CY7C11681KV18 The write cycle description table for CY7C11661KV18 and CY7C11681KV18 follows.[2, 8] BWS0/ BWS1/ K K L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – NWS0 NWS1 L Comments During the data portion of a write sequence CY7C11661KV18 both nibbles (D[7:0]) are written into the device. CY7C11681KV18 both bytes (D[17:0]) are written into the device. L-H During the data portion of a write sequence CY7C11661KV18 both nibbles (D[7:0]) are written into the device. CY7C11681KV18 both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence CY7C11661KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C11681KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H During the data portion of a write sequence CY7C11661KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C11681KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence CY7C11661KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C11681KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H During the data portion of a write sequence CY7C11661KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C11681KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. Notes 2. X = “Do not Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 7. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with the Write Cycle Description – CY7C11661KV18 and CY7C11681KV18 table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-53199 Rev. *I Page 7 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Write Cycle Descriptions – CY7C11771KV18 The write cycle description table for CY7C11771KV18 follows. [2, 8] BWS0 K K Comments L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions – CY7C11701KV18 The write cycle description table for CY7C11701KV18 follows.[2, 8] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-53199 Rev. *I L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Page 8 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull-up resistor. TDO must be left unconnected. Upon power-up, the device comes up in a reset state, which does not interfere with the operation of the device. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 12. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Test Mode Select (TMS) Boundary Scan Register The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. Test Data-In (TDI) The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. Test Access Port—Test Clock The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 11. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 14). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-53199 Rev. *I The Boundary Scan Order on page 15 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 14. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 14. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. Page 9 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power-up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a high Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high z condition. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the Test-Logic-Reset state. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Reserved Document Number: 001-53199 Rev. *I These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 10 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 The state diagram for the TAP controller follows.[9] Figure 2. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-53199 Rev. *I Page 11 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Figure 3. TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH voltage IOH =2.0 mA 1.4 V VOH2 Output HIGH voltage IOH =100 µA 1.6 V VOL1 Output LOW voltage IOL = 2.0 mA 0.4 V VOL2 Output LOW voltage IOL = 100 µA 0.2 V VIH Input HIGH voltage VIL Input LOW voltage IX Input and output load current 0.65 VDD VDD + 0.3 GND VI VDD V –0.3 0.35 VDD V –5 5 A Notes 10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the DC Electrical Characteristics Table. 11. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 12. All voltage referenced to ground. Document Number: 001-53199 Rev. *I Page 12 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 TAP AC Switching Characteristics Over the operating range[13, 14] Parameter Description Min Max Unit 50 – ns TCK clock frequency – 20 MHz TCK clock HIGH 20 – ns TCK clock LOW 20 – ns tTCYC TCK clock cycle time tTF tTH tTL Setup Times tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns Hold Times tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns Output Times tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns TAP Timing and Test Conditions Figure 4 shows the TAP timing and test conditions.[14] Figure 4. TAP Timing and Test Conditions 0.9 V ALL INPUT PULSES 1.8 V 0.9 V 50 TDO 0V Z0 = 50 (a) CL = 20 pF tTH GND tTL Test Clock TCK tTCYC tTMSH tTMSS Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Notes 13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 14. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-53199 Rev. *I Page 13 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Table 2. Identification Register Definitions Instruction Field Value CY7C11661KV18 CY7C11771KV18 CY7C11681KV18 CY7C11701KV18 000 000 000 000 Revision Number (31:29) Description Version number. Cypress Device ID 11010111000000100 11010111000001100 11010111000010100 11010111000100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 00000110100 1 1 1 1 ID Register Presence (0) Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Table 3. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Table 4. Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-53199 Rev. *I Page 14 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Table 5. Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 108 Internal 24 9K 52 8A 80 1F 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-53199 Rev. *I Page 15 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Power-up Sequence in DDR II+ SRAM DDR II+ SRAMs must be powered-up and initialized in a predefined manner to prevent undefined operations. PLL Constraints ■ PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 20 s of stable clock to relock to the desired clock frequency. Power-up Sequence ■ ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL. ~ ~ Figure 5. Power-up Waveforms K K ~ ~ Unstable Clock > 20Ps Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF Document Number: 001-53199 Rev. *I V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to VDDQ) Page 16 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied . –55 °C to +125 °C Supply voltage on VDD relative to GND ........–0.5 V to +2.9 V Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD DC applied to outputs in high z..........–0.5 V to VDDQ + 0.3 V DC input voltage [11] Static discharge voltage (MIL-STD-883, M 3015)... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Commercial Industrial Test Parameter Description Conditions Typ Max* Ambient Temperature (TA) VDD[15] VDDQ[15] 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to VDD –40 °C to +85 °C Unit LSBU Logical single-bit upsets 25 °C 197 216 FIT/ Mb LMBU Logical multi-bit upsets 25 °C 0 0.01 FIT/ Mb SEL Single event latch-up 85 °C 0 0.1 FIT/ Dev ............................. –0.5 V to VDD + 0.3 V Current into outputs (LOW) ......................................... 20 mA Range Neutron Soft Error Immunity * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Electrical Characteristics DC Electrical Characteristics Over the Operating Range[12] Min Typ Max Unit VDD Parameter Power supply voltage Description Test Conditions 1.7 1.8 1.9 V VDDQ I/O supply voltage 1.4 1.5 VDD V VOH Output HIGH voltage Note 16 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOL Output LOW voltage Note 17 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOH(LOW) Output HIGH voltage IOH =0.1 mA, nominal impedance VDDQ – 0.2 – VDDQ V VOL(LOW) Output LOW voltage IOL = 0.1 mA, nominal impedance VSS – 0.2 V VIH Input HIGH voltage VREF + 0.1 – VDDQ + 0.15 V VIL Input LOW voltage –0.15 – VREF – 0.1 V IX Input leakage current GND VI VDDQ 2 – 2 µA IOZ Output leakage current GND VI VDDQ, output disabled VREF Input reference voltage[18] Typical value = 0.75 V 2 – 2 µA 0.68 0.75 0.95 V Notes 15. Power-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 . 17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 . 18. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller. Document Number: 001-53199 Rev. *I Page 17 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 DC Electrical Characteristics (continued) Over the Operating Range[12] Parameter IDD[19] Description VDD operating supply Test Conditions VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 550 MHz 500 MHz 450 MHz 400 MHz ISB1 Automatic power-down current Max VDD, both ports deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC, inputs static 550 MHz 500 MHz 450 MHz 400 MHz Min Typ Max Unit (x8) – – 740 mA (x9) – – 740 (x18) – – 760 (x36) – – 970 (x8) – – 690 (x9) – – 690 (x18) – – 700 (x36) – – 890 (x8) – – 630 (x9) – – 630 (x18) – – 650 (x36) – – 820 (x8) – – 580 (x9) – – 580 (x18) – – 590 (x36) – – 750 (x8) – – 380 (x9) – – 380 (x18) – – 380 (x36) – – 380 (x8) – – 360 (x9) – – 360 (x18) – – 360 (x36) – – 360 (x8) – – 340 (x9) – – 340 (x18) – – 340 (x36) – – 340 (x8) – – 320 (x9) – – 320 (x18) – – 320 (x36) – – 320 mA mA mA mA mA mA mA Note 19. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-53199 Rev. *I Page 18 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 AC Electrical Characteristics Over the operating range[11] Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH voltage VREF + 0.2 – VDDQ + 0.24 V VIL Input LOW voltage –0.24 – VREF – 0.2 V Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description CIN Input capacitance CO Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V Max Unit 4 pF 4 pF 165-FBGA Package Unit 13.7 °C/W 3.73 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 6. AC Test Loads and Waveforms VREF = 0.75 V VREF 0.75 V VREF OUTPUT Z0 = 50 Device Under Test ZQ RL = 50 R = 50 ALL INPUT PULSES 1.25 V 0.75 V OUTPUT Device Under VREF = 0.75 V Test ZQ RQ = 250 (a) 0.75 V INCLUDING JIG AND SCOPE 5 pF [20] 0.25 V Slew rate = 2 V/ns RQ = 250 (b) Note 20. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms. Document Number: 001-53199 Rev. *I Page 19 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Switching Characteristics Over the operating range[20, 21] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHKH tKHKL tKLKH tKHKH Setup Times tAVKH tSA tSC tIVKH tSCDDR tIVKH tSD tDVKH Hold Times tHA tKHAX tHC tKHIX tHCDDR tKHIX tHD tKHDX Output Times tCO tCHQV tDOH tCHQX tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHZ tCHQZ tCLZ tCHQX1 tQVLD tCQHQVLD PLL Timing tKC Var tKC Var tKC lock tKC lock tKC Reset tKC Reset Description 550 MHz 500 MHz 450 MHz 400 MHz Min Max Min Max Min Max Min Max Unit VDD(typical) to the first access[22] K clock cycle time Input clock (K/K) HIGH Input clock (K/K) LOW K clock rise to K clock rise (rising edge to rising edge) 1 1.81 0.4 0.4 0.77 – 8.4 – – – 1 2.0 0.4 0.4 0.85 – 8.4 – – – 1 2.2 0.4 0.4 0.94 – 8.4 – – – 1 2.5 0.4 0.4 1.06 – 8.4 – – – ms ns ns ns ns Address setup to K clock rise Control setup to K clock rise (LD, R/W) 0.23 0.23 – – 0.25 0.25 – – 0.275 0.275 – – 0.4 0.4 – – ns ns Double data rate control setup to clock (K/K) Rise 0.18 (BWS0, BWS1, BWS2, BWS3) D[X:0] setup to clock (K/K) rise 0.18 – 0.20 – 0.22 – 0.28 – ns – 0.20 – 0.22 – 0.28 – ns 0.23 0.23 – – 0.25 0.25 – – 0.275 0.275 – – 0.4 0.4 – – ns ns 0.18 – 0.20 – 0.22 – 0.28 – ns 0.18 – 0.20 – 0.22 – 0.28 – ns Address hold after K clock rise Control hold after K clock rise (LD, R/W) Double data rate control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) D[X:0] hold after clock (K/K) rise K/K clock rise to data valid Data output hold after output K/K clock rise (active to active) K/K clock rise to echo clock valid Echo clock hold after K/K Clock rise Echo clock high to data valid Echo clock high to data invalid Output clock (CQ/CQ) HIGH[23] CQ clock rise to CQ clock rise (rising edge to rising edge)[23] Clock (K/K) rise to high Z (active to high Z) [24, 25] – 0.45 – 0.45 – 0.45 – 0.45 –0.45 – –0.45 – –0.45 – –0.45 – ns ns – 0.45 – 0.45 – 0.45 – 0.45 –0.45 – –0.45 – –0.45 – –0.45 – – 0.15 – 0.15 – 0.15 – 0.20 –0.15 – –0.15 – –0.15 – –0.20 – 0.655 – 0.75 – 0.85 – 1.00 – 0.655 – 0.75 – 0.85 – 1.00 – ns ns ns ns ns ns 0.45 ns Clock (K/K) rise to low Z[24, 25] Echo clock high to QVLD valid[26] –0.45 – –0.45 – –0.45 – –0.45 – –0.15 0.15 –0.15 0.15 –0.15 0.15 –0.20 0.20 ns ns Clock phase jitter PLL lock time (K) K static to PLL reset[27] – – 20 30 0.45 0.15 – – – – 20 30 0.45 0.15 – – – – 20 30 0.45 0.15 – – – – 20 30 0.20 – – ns µs ns Notes 21. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 22. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated. 23. These parameters are extrapolated from the input timing parameters (tCYC/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 24. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage. 25. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 26. tQVLD specification is applicable for both rising and falling edges of QVLD signal. 27. Hold to >VIH or <VIL. Document Number: 001-53199 Rev. *I Page 20 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Switching Waveforms Read/Write/Deselect Sequence[28, 29, 30] Figure 7. Waveform for 2.5 Cycle Read Latency READ 2 NOP 1 READ 3 NOP 5 NOP 4 WRITE 7 NOP 6 WRITE 8 READ 9 NOP 10 NOP 11 12 K t KH t KHKH tCYC t KL K LD tSC t HC R/W A A0 t SA t HA A1 A2 t QVLD t QVLD A3 A4 t QVLD QVLD tHD t HD tSD Q00 DQ tCLZ (Read Latency = 2.5 Cycles) Q01 Q10 Q11 t DOH tCO t CCQO tSD D20 D21 D30 D31 Q40 tCHZ t CQD t CQDOH t CQOH CQ t CQOH t CCQO tCQH tCQHCQH CQ DON’T CARE UNDEFINED Notes 28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 29. Outputs are disabled (high z) one clock cycle after a NOP. 30. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-53199 Rev. *I Page 21 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Table 6. Ordering Information Speed (MHz) 450 400 Ordering Code CY7C11681KV18-450BZC CY7C11681KV18-450BZXC CY7C11681KV18-400BZC CY7C11701KV18-400BZXC Package Diagram 51-85180 51-85180 Package Type 165-ball FPBGA (13 × 15 × 1.4 mm) 165-ball FPBGA (13 × 15 × 1.4 mm) Pb-free 165-ball FPBGA (13 × 15 × 1.4 mm) 165-ball FPBGA (13 × 15 × 1.4 mm) Pb-free Operating Range Commercial Commercial Ordering Code Definitions CY 7C 11XXX K V18 - XXX XXX C Temperature Range: C = Commercial Package Type: XXX = BZ or BZX BZ = 165-ball FPBGA BZX = 165-ball FPBGA (Pb-free) Frequency Range: XXX = 450 MHz or 400 MHz Voltage: 1.8 V 65 nm Die Revision Part Identifier: 11XXX = 11681 or 11701 = 18-Mbit DDR II+ two-word burst architecture Marketing Code : 7C = SRAM Company ID: CY = Cypress Document Number: 001-53199 Rev. *I Page 22 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Package Diagram Figure 8. 165-Ball FBGA (13 × 15 × 1.4 mm), 51-85180 TOP VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 Ø0.08 M C Ø0.25 M C A B A Ø0.50 B 11 10 9 8 7 6 5 4 -0.06 +0.14 3 (165X) 2 1 C A D B E C 1.00 F D 15.00±0.10 G E H F K L G 14.00 15.00±0.10 J H J M K N L 7.00 P M R N P A R A 1.00 5.00 B 13.00±0.10 1.40 MAX. SEATING PLANE C 0.15 C 0.53±0.05 0.36 0.25 C 10.00 B 13.00±0.10 0.15(4X) NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / ISSUE E PACKAGE CODE : BB0AC 51-85180 *C Document Number: 001-53199 Rev. *I Page 23 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Acronyms Acronym Description DDR double data rate FBGA fine-pitch ball grid array HSTL high speed transceiver logic JEDEC joint electron device engineering council JTAG joint test action group LMBU logical multiple-bit upset LSBU logical single-bit upset PLL phase-locked loop QDR quad data rate SEL single event latch-up TAP test access port TCK test clock TDI test data in TDO test data out TMS test mode select Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA micro amperes mA milliamperes ns nano seconds ohms pF pico Farad V volts W watts Document Number: 001-53199 Rev. *I Page 24 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Document History Page Document Title: CY7C11661KV18/CY7C11771KV18/CY7C11681KV18/CY7C11701KV18, 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-53199 Revision ECN Orig of Change Submission Description of Change Date ** 2702744 VKN/PYRS 05/06/09 *A 2747707 VKN/AESA 08/03/2009 Converted from preliminary to final For 550 MHz, 500 MHz, and 450 MHz bins, changed tCO, tCCQO, tCHZ to 450 ps and tDOH, tCQOH, tCLZ to –450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information *B 2761928 AJU 09/10/2009 Post to external web *C 2767155 VKN 09/23/2009 Changed Input Capacitance (CIN) from 2 pF to 4 pF Changed Output Capacitance (CO) from 3 pF to 4 pF Modified Ordering code disclaimer *D 2785104 VKN 10/16/2009 Updated Ordering information table *E 2855911 VKN 01/18/2010 Included “CY7C11701KV18-400BZXC” part in the Ordering information table Updated package outline diagram Added Contents. *F 2896003 NJY 03/19/2010 Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information. *G 2950522 CS/NJY 08/16/10 *H 3056557 NJY 10/12/2010 Added new CY7C11681KV18-400BZXC part number to the Ordering Information table. *I 3158084 AJU 01/31/2011 Updated Ordering Information. Document Number: 001-53199 Rev. *I New datasheet Added partnumber CY7C11701KV18-450BZXC and CY7C11701KV18-400BZXC to the ordering information table. Template update. Added ordering code definitions, acronyms, and units of measure. Page 25 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53199 Rev. *I Revised January 31, 2011 Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback