X9271
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
June 23, 2011
Single, Digitally Controlled (XDCP™)
Potentiometer
FEATURES
• 256 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of Potentiometer
• Wiper Resistance, 100Ω typical @ VCC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position
on Power-up
• Standby Current < 3µA Max
• VCC = 2.7V to 5.5V Operation
• 50kΩ, 100kΩ Versions of End-to-End Resistance
• 100-yr Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 14-Lead TSSOP
• Low-power CMOS
• Pb-free Plus Anneal Available (RoHS Compliant)
FN8174.3
DESCRIPTION
The X9271 integrates a single, digitally controlled
potentiometer (XDCP™) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented by
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four
nonvolatile data registers that can be directly written to
and read by the user. The contents of the WCR control
the position of the wiper on the resistor array though the
switches. Power-up recalls the contents of the default
data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications. including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
SPI
Bus
Interface
Address
Data
Status
RH
Write
Read
Transfer
Inc/Dec
Bus
Interface
and Control
Control
VSS
1
50kΩ and 100kΩ
256 Taps
Power-on Recall
Wiper Counter
Register (WCR)
POT
Data Registers
16 Bytes
RW
RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2011. All Rights Reserved
XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation
or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
X9271
Ordering Information
PART NUMBER
(Notes 1, 3)
PART
MARKING
VCC LIMITS
(V)
X9271UV14IZ (Note 2)
X9271 UVZI
5 ±10%
50
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271UV14Z (Note 2)
X9271 UVZ
5 ±10%
50
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271TV14 (Note 4)
X9271 TV
5 ±10%
100
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
2.7 to 5.5
100
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
X9271TV14I-2.7T1 (Note 4) X9271 TVG
POTENTIOMETER TEMP. RANGE
ORGANIZATION (kΩ)
(°C)
PACKAGE
PKG.
DWG. #
X9271TV14IZ (Note 2)
X9271 TVZI
5 ±10%
100
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271TV14Z (Note 2)
X9271 TVZ
5 ±10%
100
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271UV14I-2.7 (Note 4)
X9271 UVG
2.7 to 5.5
50
-40 to +85
14 Ld TSSOP (4.4mm)
X9271UV14IZ-2.7 (Note 2)
X9271 UVZG
2.7 to 5.5
50
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271UV14Z-2.7 (Note 2)
X9271 UVZF
2.7 to 5.5
50
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271TV14IZ-2.7 (Note 2)
X9271 TVZG
2.7 to 5.5
50
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9271TV14Z-2.7 (Note 2)
X9271 TVZF
2.7 to 5.5
100
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
M14.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363.
4. Not recommended for new designs.
2
FN8174.3
June 23, 2011
X9271
DETAILED FUNCTIONAL DIAGRAM
VCC
Bank 0 Power-on Recall
R0 R1
HOLD
CS
SCK
R2 R3
Interface
and
Control
Circuitry
SO
SI
A0
A1
50kΩ and 100kΩ
256 Taps
Wiper
Counter
Register
(WCR)
RH
RL
RW
DATA
WP
Control
Bank 1
Bank 2
Bank 3
R0 R1
R0 R1
R0 R1
R2 R3
R2 R3
R2 R3
12 Additional Nonvolatile Registers
3 Banks of 4 Registers x 8 Bits
VSS
CIRCUIT-LEVEL APPLICATIONS
SYSTEM-LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier.
• Adjust the contrast in LCD displays.
• Provide programmable DC reference voltages for
comparators and detectors.
• Control the power level of LED transmitters in
communication systems.
• Control the volume in audio circuits.
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems.
• Trim out the offset voltage error in a voltage amplifier
circuit.
• Set the output voltage of a voltage regulator.
• Trim the resistance in Wheatstone bridge circuits.
• Control the gain, characteristic frequency, and
Q-factor in filter circuits.
• Set the scale factor and zero point in sensor signal
conditioning circuits.
• Vary the frequency and duty cycle of timer ICs.
• Vary the DC biasing of a pin diode attenuator in RF
circuits.
• Control the gain in audio and home entertainment
systems.
• Provide the variable DC bias for tuners in RF
wireless systems.
• Set the operating points in temperature control
systems.
• Control the operating point for sensors in industrial
systems.
• Trim offset and gain errors in artificial intelligence
systems.
• Provide a control variable (I, V, or R) in feedback
circuits.
3
FN8174.3
June 23, 2011
X9271
PIN CONFIGURATION
TSSOP
S0
1
X9271
14
VCC
13
RL
A0
2
NC
3
12
RH
CS
4
11
RW
SCK
5
10
HOLD
SI
6
9
A1
VSS
7
8
WP
PIN ASSIGNMENTS
TSSOP
Symbol
Function
1
SO
Serial Data Output
2
A0
Device Address
3
NC
No Connect
4
CS
Chip Select
5
SCK
Serial Clock
6
SI
Serial Data Input
7
VSS
System Ground
8
WP
Hardware Write Protect
9
A1
Device Address
10
HOLD
11
RW
Wiper Terminal of Potentiometer
12
RH
High Terminal of Potentiometer
13
RL
Low Terminal of Potentiometer
14
VCC
4
Device Select. Pause the serial bus.
System Supply Voltage
FN8174.3
June 23, 2011
X9271
PIN DESCRIPTIONS
Potentiometer Pins
Bus Interface Pins
RH, RL
SERIAL OUTPUT (SO)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
The Serial Output (SO) is the serial data output pin.
During a read cycle, data is shifted out on this pin.
Data is clocked out by the falling edge of the serial
clock.
SERIAL INPUT (SI)
RW
The wiper pin (RW) is equivalent to the wiper terminal
of a mechanical potentiometer.
Supply Pins
The Serial Input (SI) is the serial data input pin. All
operational codes, byte addresses, and data to be
written to the potentiometers and potentiometer
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The System Supply Voltage (VCC) pin is the system
supply voltage. The Supply Ground (VSS) pin is the
system ground.
SERIAL CLOCK (SCK)
Other Pins
The Serial Clock (SCK) input is used to clock data into
and out of the X9271.
HARDWARE WRITE PROTECT INPUT (WP)
HOLD (HOLD)
The Hardware Write Protect Input (WP) pin, when
LOW, prevents nonvolatile writes to the data registers.
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is under way, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
NO CONNECT
No Connect pins should be left floating. These pins
are used for Intersil manufacturing and testing
purposes.
DEVICE ADDRESS (A1 - A0)
The Device Address (A1 - A0) inputs are used to set
the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9271.
CHIP SELECT (CS)
When Chip Select (CS) is HIGH, the X9271 is
deselected, the SO pin is at high impedance, and
(unless an internal write cycle is under way) the device
is in standby state. CS LOW enables the X9271,
placing it in the active power mode. It should be noted
that after a power-up, a HIGH to LOW transition on CS
is required prior to the start of any operation.
5
FN8174.3
June 23, 2011
X9271
PRINCIPLES OF OPERATION
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
Device Description
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array, only one
switch may be turned on at a time.
SERIAL INTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
These switches are controlled by a Wiper Counter
Register (WCR). The eight bits of the WCR
(WCR[7:0]) are decoded to select, and enable, one of
256 switches (Table 1).
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
POWER-UP AND POWER-DOWN RECOMMENDATIONS
There are no restrictions on the power-up or
power-down conditions of VCC and the voltages
applied to the potentiometer pins, provided that VCC is
always more positive than or equal to VH, VL, and VW;
i.e., VCC ≥ VH, VL, VW. The VCC ramp rate
specification is always in effect.
ARRAY DESCRIPTION
The X9271 is composed of a resistor array (Figure 1).
The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
SERIAL DATA PATH
RH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
8
8
BANK_0 Only
REGISTER 2
(DR2)
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
REGISTER 3
(DR3)
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
RW
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
6
FN8174.3
June 23, 2011
X9271
DEVICE DESCRIPTION
.
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit),
WCR[7:0]: Used to store current wiper position
(Volatile, V)
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register (WCR)
for the DCP potentiometer. The WCR can be
envisioned as an 8-bit parallel and serial load counter,
with its outputs decoded to select one of 256 switches
along its resistor array (Table 1). The contents of the
WCR can be altered in four ways:
1. It can be written directly by the host via the Write Wiper
Counter Register instruction (serial load).
2. It can be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register instruction (parallel load).
3. It can be modified one step at a time by the Increment/
Decrement instruction.
4. It is loaded with the contents of its Data Register zero
(DR0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9271 is powered down. Although the
register is automatically loaded with the value in DR0
upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loading of the R0
value into the WCR. The DR0 value of Bank 0 is the
default value.
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
V
V
V
V
V
V
V
V
(MSB)
(LSB)
.
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to
store wiper positions or data (Nonvolatile, NV)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
TABLE 3. STATUS REGISTER, SR (WIP is 1-bit)
WIP
(LSB)
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host (Table 2). Data can also be transferred between
any of the four Data Registers and the associated
WCR. All operations changing data in one of the Data
Registers are nonvolatile operations and take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).
Status Register (SR)
The 1-bit Status Register is used to store the system
status (Table 3).
WIP: Write In Progress status bit; read only.
– WIP = 1 indicates that a high-voltage write cycle is in
progress.
– WIP = 0 indicates that no high-voltage write cycle is
in progress
7
FN8174.3
June 23, 2011
X9271
DEVICE DESCRIPTION
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations to the
Wiper Counter Register (Tables 5 and 6).
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bit is the device ID for the X9271; this is fixed as
0101[B] (Table 4).
The A1 - A0 bits in the ID byte are the internal slave
address. The physical device address is defined by
the state of the A1 - A0 input pins. The slave address
is externally specified by the user. The X9271
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9271 to successfully continue the
command sequence. Only the device for which slave
address matches the incoming device address sent by
the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS.
TABLE 4. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER
ID2
ID1
ID0
0
1
0
1
0
0
INTERNAL
SLAVE
ADDRESS
A1
A0
(MSB)
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE
RB
RA
REGISTER
SELECTION
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write; Wiper
Counter Register Operations
1
0
2
Data Register Read and Write; Wiper
Counter Register Operations
1
1
3
Data Register Read and Write; Wiper
Counter Register Operations
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used to provide the instruction
operation code (I[3:0]). The RB and RA bits point to
one of the four Data Registers. P0 is the POT
selection; since the X9271 is single POT, P0 = 0. The
format is shown in Table 7.
ID3
SET TO 0 FOR
PROPER
OPERATION
OPERATIONS
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
P1
P0
BANK
SELECTION
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write Only
1
0
2
Data Register Read and Write Only
1
1
3
Data Register Read and Write Only
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks.
Bank 0 is the default bank of registers. Only Bank 0
registers can be used for the data register to Wiper
Counter Register operations.
OPERATIONS
TABLE 7. INSTRUCTION BYTE FORMAT
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
REGISTER
SELECTION
INSTRUCTION OPCODE
I3
I2
I1
P0
(MSB)
RB
RA
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 5)
P1
P0
(LSB)
NOTE:
5. Set to P0 = 0 for potentiometer operations.
8
FN8174.3
June 23, 2011
X9271
DEVICE DESCRIPTION
Instructions
Five of the eight instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register: Read the current
wiper position of the potentiometer.
– Write Wiper Counter Register: Change current
wiper position of the potentiometer.
– Read Data Register: Read the contents of the
selected Data Register.
– Write Data Register: Write a new value to the
selected Data Register.
– Read Status: This command returns the contents of
the WIP bit, which indicates if the internal write cycle
is in progress.
See Table 8 for details of the instruction set.
The basic sequence of the 3-byte instruction is shown
in Figure 2. These 3-byte instructions exchange data
between the WCR and one of the Data Registers. A
transfer from a Data Register to a WCR is essentially a
write to a static RAM, with the static RAM controlling
the wiper position. The response of the wiper to this
action is delayed by tWRL. A transfer from the WCR
(current wiper position) to a Data Register is a write to
nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers, or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register. The Read Status Register instruction is the
only unique format (Figure 3).
9
Two instructions require a 2-byte sequence to
complete (Figure 4). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers, or directly between
the host and the Wiper Counter Register. These
instructions are:
– XFR Data Register to Wiper Counter Register:
Transfers the contents of one specified Data Register to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register:
Transfers the contents of the specified Wiper Counter Register to the associated Data Register.
The final command is Increment/Decrement (Figures 5
and 6). It is different from the other commands,
because its length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment step,
thereby providing a fine-tuning capability to the host.
For each SCK clock pulse (tHIGH) while SI is HIGH,
the selected wiper moves one resistor segment
towards the RH terminal. Similarly, for each SCK clock
pulse while SI is LOW, the selected wiper moves one
resistor segment towards the RL terminal.
Write-in-Process (WIP) Bit
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by the Write-in-Process bit
(WIP). The WIP bit is read with a Read Status
command.
FN8174.3
June 23, 2011
X9271
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
A1 A0
I3
Internal
Address
Device ID
I1
I2
D7 D6 D5 D4 D3 D2 D1 D0
RB RA P1 P0
I0
Register
Address
Instruction
Opcode
Pot/BankWCR[7:0] valid only when P1 = P0 = 0;
Address
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
X
A1 A0
I3
Internal
Address
Device ID
I2
I1 I0
Instruction
Opcode
X
X
RB RA P1 P0
Register
Address
X
X
X
X
X
Don’t Care
Pot/Bank
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE (READ)
CS
SCK
SI
1
0
0
ID3 ID2 ID1 ID0
0
0
0
1
0
Device ID
0
A1
A0
Internal
Address
I3
I2
I1 I0
Instruction
Opcode
0
RB RA P1 P0
Register
Address
Pot/Bank
Address
These commands only valid when P1 = P0 = 0
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
10
FN8174.3
June 23, 2011
X9271
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
0
A1 A0
I3
Internal
Address
Device ID
I1
I2
I0
Instruction
Opcode
0
RA RB P1 P0
Register
Address
Pot/Bank
Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
tWRID
SCK
SI
VOLTAGE OUT
VW
INC/DEC CMD ISSUED
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 8. INSTRUCTION SET
INSTRUCTION SET
(1/0 = DATA IS ONE OR ZERO)
INSTRUCTION
Read Wiper Counter Register
I3
I2
I1
I0
RB
RA
P1
P0
1
0
0
1
0
0
0
1/0
OPERATION
Read contents of Wiper Counter Register.
Write Wiper Counter Register
1
0
1
0
0
0
0
1/0
Write new value to Wiper Counter Register.
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read contents of Data Register pointed to by P1 - P0
and RB - RA.
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to Data Register pointed to by P1 - P0
and RB - RA.
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
0
0
Transfer contents of Data Register pointed to by
RB - RA (Bank 0 only) to Wiper Counter Register.
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
0
0
Transfer contents of Wiper Counter Register to Register
pointed to by RB-RA (Bank 0 only).
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
0
0
Enable increment/decrement of the Wiper Counter
Register.
Read Status (WIP Bit)
0
1
0
1
0
0
0
1
Read status of internal write cycle by checking WIP bit.
11
FN8174.3
June 23, 2011
X9271
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
CS
Falling
Edge 0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1
0
0
1
DR/Bank
Addresses
0
0
0
Wiper Position
(Sent by X9271 on SO)
W
C
R
6
W
C
0
R
7
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Write Wiper Counter Register (WCR)
Device Type
Identifier
CS
Falling
Edge 0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1
0
1
0
DR/Bank
Addresses
0
0
0
Data Byte
(Sent by Host on SI)
W
C
0
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Read Data Register (DR)
Device Type
Device
Instruction
DR/Bank
Data Byte
CS
CS
Identifier
Addresses
Opcode
Addresses
(Sent
by
X9271 on SO)
Falling
Rising
Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge
Device Type
Identifier
CS
Falling
Edge 0
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1 1 1 0
12
DR/Bank
Addresses
RB
RA
0
0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
FN8174.3
June 23, 2011
X9271
Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 6, 7)
Device Type
Device
CS
Identifier
Addresses
Falling
Edge 0 1 0 1 0 0 A1 A0
Instruction
Opcode
DR/Bank
Addresses
1 1 0 1 RB RA
0
0
CS
Rising
Edge
Increment/Decrement Wiper Counter Register (WCR) (Notes 6, 7, 8, 9, 10)
Device Type
CS
Identifier
Falling
Edge 0 1 0 1
Device
Addresses
0 0
A1
A0
Instruction
Opcode
DR/Bank
Addresses
Increment/Decrement
(Sent by Master on SDA)
0 0 1 0 X X 0 0 I/D I/D
.
.
.
.
CS
Rising
I/D I/D Edge
Read Status Register (SR) (Note 6)
Device Type
CS
Identifier
Falling
Edge 0 1 0 1
Device
Addresses
0 0
A1
A0
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
0 1 0 1 0 0 0 1 0 0 0 0 0 0 0
WIP
CS
Rising
Edge
NOTES:
6. “A1 ~ A0”: stands for the device addresses sent by the master.
7. WCRx refers to wiper position data in the Wiper Counter Register.
8. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high).
9. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high).
10. “X:”: Don’t Care.
13
FN8174.3
June 23, 2011
X9271
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on SCK, any address input,
with respect to VSS ................................. -1V to +7V
ΔV = |(VH - VL)|..................................................... 5.5V
Lead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds).................................................. ±6mA
Pb-Free Reflow Profile .......................... see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Commercial
0°C
+70°C
Industrial
-40°C
+85°C
Supply Voltage (VCC) Limits
(Note 14)
Device
X9271
5V ± 10%
X9271-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
(Note 18)
Typ.
Max.
(Note 18)
Units
Test Conditions
RTOTAL
End to End Resistance
100
kΩ
T version
RTOTAL
End to End Resistance
50
kΩ
U version
End to End Resistance
Tolerance
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
300
W
RW
Wiper Resistance
150
W
IW = ± 3mA @ VCC = 5V
VTERM
Voltage on any RH or RL Pin
VCC
V
VSS = 0V
Noise
Resolution
VSS
-120
dBV/√Hz
0.4
%
IW = ± 3mA @ VCC = 3V
Ref: 1V
Absolute Linearity (Note 11)
±1
MI
(Note 13)
Rw(n)(actual) - Rw(n)(expected)
(Note 15)
Relative Linearity (Note 12)
±0.2
MI
(Note 13)
Rw(n + 1) - [Rw(n) + MI] (Note 15)
Temperature Coefficient of
RTOTAL
±300
Ratiometric Temp.
Coefficient
CH/CL/CW
+25°C, each pot
Potentiometer
Capacitance
ppm/°C
20
10/10/25
ppm/°C
pF
See macro model
NOTES:
11. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
12. Relative linearity is used to determine actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
13. MI = RTOT / 255 or (RH - RL) / 255, single pot.
14. During power-up, VCC > VH, VL, and VW.
15. n = 0, 1, 2, …,255; m =0, 1, 2, …., 254.
14
FN8174.3
June 23, 2011
X9271
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Min.
Max.
(Note 18) Typ. (Note 18) Units
Parameter
Test Conditions
400
μA
fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
5
mA
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
VCC Current (Standby)
3
μA
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
ILI
Input Leakage Current
10
μA
VIN = VSS to VCC
ILO
Output Leakage Current
10
μA
VOUT = VSS to VCC
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW Voltage
-1
VCC x 0.3
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA
VOH
Output HIGH Voltage
VCC - 0.8
V
IOH = -1mA, VCC ≥ +3V
VOH
Output HIGH Voltage
VCC - 0.4
V
IOH = -0.4mA, VCC ≤ +3V
ICC1
VCC Supply Current
(Active)
ICC2
VCC Supply Current
(Nonvolatile Write)
ISB
1
ENDURANCE AND DATA RETENTION
Parameter
Min.
(Note 18)
Units
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
Years
CAPACITANCE
Symbol
Test
Max.
(Note 18)
Units
Test Conditions
CIN/OUT (Note 16)
Input / Output Capacitance (SI)
8
pF
VOUT = 0V
COUT (Note 16)
Output Capacitance (SO)
8
pF
VOUT = 0V
CIN (Note 16)
Input Capacitance (A0, CS, WP, HOLD, and
SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
Parameter
Min.
(Note 18)
Max.
(Note 18)
Units
0.2
tr VCC (Note 16)
VCC Power-up Rate
50
V/ms
tPUR (Note 17)
Power-up to Initiation of Read Operation
1
ms
tPUW (Note 17)
Power-up to Initiation of Write Operation
50
ms
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
NOTES:
16. This parameter is not 100% tested.
17. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and are not 100% tested.
18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
15
FN8174.3
June 23, 2011
X9271
EQUIVALENT A.C. LOAD CIRCUIT
5V
SPICE Macromodel
3V
1462Ω
1382Ω
RTOTAL
RH
SO pin
RL
SO pin
2714Ω
100pF
CW
CL
1217Ω
100pF
CL
10pF
25pF
10pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2.5
MHz
fSCK
SSI/SPI Clock Frequency
tCYC
SSI/SPI Clock Cycle Time
500
ns
tWH
SSI/SPI Clock High Time
200
ns
tWL
SSI/SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
2
μs
tFI
SI, SCK, HOLD and CS Input Fall Time
2
μs
tDIS
SO Output Disable Time
tV
SO Output Valid Time
tHO
SO Output Hold Time
tRO
SO Output Rise Time
100
ns
tFO
SO Output Fall Time
100
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
ns
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs
10
ns
tCS
CS Deselect Time
2
μs
tWPASU
WP, A0 Setup Time
0
ns
tWPAH
WP, A0 Hold Time
0
ns
16
0
250
ns
200
ns
0
ns
FN8174.3
June 23, 2011
X9271
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage Write Cycle Time (Store Instructions)
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Min.
Max.
Units
tWRPO
Symbol
Wiper Response Time After Third (Last) Power Supply is Stable
Parameter
5
10
μs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
5
10
μs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
17
FN8174.3
June 23, 2011
X9271
TIMING DIAGRAMS
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
...
tWH
tWL
...
MSB
SI
tLAG
tRI
tFI
LSB
High Impedance
SO
Output Timing
CS
SCK
tV
...
MSB
SO
SI
...
tHO
tDIS
LSB
ADDR
Hold Timing
CS
tHSU
SCK
tHH
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
18
FN8174.3
June 23, 2011
X9271
XDCP Timing (for All Load Instructions)
CS
SCK
SI
...
tWRL
...
MSB
LSB
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
WP
tWPAH
A0
A1
19
FN8174.3
June 23, 2011
X9271
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
3-terminal Potentiometer;
Variable Voltage Divider
2-terminal Variable Resistor;
Variable Current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
}
10kΩ
}
TL072
10kΩ
VO
R1
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
20
FN8174.3
June 23, 2011
X9271
Application Circuits (continued)
Attenuator
Filter
C
VS
R2
R1
VO
–
–
VS
+
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R2
}
VS
R1
}
Inverting Amplifier
Equivalent L-R Circuit
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
Frequency ∝ R1, R2, C
Amplitude ∝ RA, RB
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8174.3
June 23, 2011
X9271
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
22
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN8174.3
June 23, 2011