X9251
®
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
April 13, 2007
FN8166.5
Quad Digitally-Controlled (XDCP™)
Potentiometer
Features
The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.
• 256 resistor taps–0.4% resolution
• Four potentiometers in one package
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
The digitally controlled potentiometers are imple-mented
with a combination of resistor elements and CMOS switches.
The position of the wipers are controlled by the user through
the SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.
• Wiper resistance: 100Ω typical @ VCC = 5V
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current <5µA max
• VCC: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ versions of total resistance
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 100 year data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free plus anneal available (RoHS compliant)
Functional Diagram
HOLD
A1
SPI
Interface
A0
SO
SI
RH1
RH0
VCC
WCR0
DR00
DR01
DR02
DR03
POWER UP,
INTERFACE
CONTROL
AND
STATUS
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
RH3
RH2
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
SCK
CS
VSS
WP
1
RW0
RL0
RW1
RL1
RW2
RL2
RW3
RL3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9251
Ordering Information
PART NUMBER
PART
MARKING
X9251US24
X9251US
X9251US24Z (Note)
VCC LIMITS
(V)
5 ±10%
POTENTIOMENTER
ORGANIZATION
TEMP RANGE
(kΩ)
(°C)
50
PACKAGE
PKG.
DWG. #
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9251US Z
0 to +70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9251UV24
X9251UV
0 to +70
24 Ld TSSOP (4.4mm)
MDP0044
X9251UV24Z (Note)
X9251UV Z
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TS24
X9251TS
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9251TS24Z (Note)
X9251TS Z
0 to +70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9251TS24I
X9251TS I
-40 to +85
24 Ld SOIC (300 mil)
M24.3
X9251TS24IZ (Note)
X9251TS ZI
-40 to +85
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9251TV24I
X9251TV I
-40 to +85
24 Ld TSSOP (4.4mm)
MDP0044
X9251TV24IZ (Note)
X9251TV ZI
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251US24I-2.7
X9251US G
-40 to +85
24 Ld SOIC (300 mil)
M24.3
-40 to +85
24 Ld SOIC (300 mil) (Pb-free)
M24.3
MDP0044
100
2.7 to 5.5
50
X9251US24IZ-2.7 (Note) X9251US ZG
X9251UV24-2.7
X9251UV F
0 to +70
24 Ld TSSOP (4.4mm)
X9251UV24Z-2.7 (Note)
X9251UV ZF
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251UV24I-2.7
X9251UV G
-40 to +85
24 Ld TSSOP (4.4mm)
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251UV24IZ-2.7 (Note) X9251UV ZG
X9251TS24-2.7
X9251TS F
X9251TS24Z-2.7 (Note)
100
MDP0044
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9251TS ZF
0 to +70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9251TV24-2.7
X9251TV F
0 to +70
24 Ld TSSOP (4.4mm)
MDP0044
X9251TV24Z-2.7 (Note)
X9251TV ZF
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TV24I-2.7
X9251TV G
-40 to +85
24 Ld TSSOP (4.4mm)
X9251TV24IZ-2.7 (Note)
X9251TV ZG
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8166.5
April 13, 2007
X9251
Circuit Level Applications
Pinout
• Vary the gain of a voltage amplifier
X9251
(24 LD SOIC/TSSOP)
TOP VIEW
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
SO
1
24
HOLD
A0
2
23
SCK
RW3
3
22
RL2
RH3
4
21
RH2
RL3
5
20
RW2
NC
6
19
NC
18
VSS
X9251
• Control the gain, characteristic frequency and
Q-factor in filter circuits
VCC
7
RL0
8
17
RW1
• Set the scale factor and zero point in sensor signal
conditioning circuits
RH0
9
16
RH1
RW0
10
15
RL1
CS
11
14
A1
WP
12
13
SI
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
System Level Applications
Pin Assignments
PIN
(SOIC)
SYMBOL
• Control the power level of LED transmitters in
communication systems
1
SO
Serial Data Output for SPI bus
2
A0
Device Address for SPI bus. (See Note 1)
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
3
RW3
Wiper Terminal of DCP3
4
RH3
High Terminal of DCP3
• Control the gain in audio and home entertainment systems
5
RL3
Low Terminal of DCP3
• Provide the variable DC bias for tuners in RF wireless
systems
7
VCC
System Supply Voltage
8
RL0
Low Terminal of DCP0
• Set the operating points in temperature control
systems
9
RH0
High Terminal of DCP0
10
RW0
Wiper Terminal of DCP0
• Control the operating point for sensors in industrial
systems
11
CS
SPI bus. Chip Select active low input
12
WP
Hardware Write Protect - active low
• Adjust the contrast in LCD displays
• Trim offset and gain errors in artificial intelligent
systems
FUNCTION
13
SI
Serial Data Input for SPI bus
14
A1
Device Address for SPI bus. (See Note 1)
15
RL1
Low Terminal of DCP1
16
RH1
High Terminal of DCP1
17
RW1
Wiper Terminal of DCP1
18
VSS
System Ground
20
RW2
Wiper Terminal of DCP2
21
RH2
High Terminal of DCP2
22
RL2
Low Terminal of DCP2
23
SCK
Serial Clock for SPI bus
24
HOLD
6, 19
NC
Device select. Pauses the SPI serial bus.
No Connect
NOTE:
1. A0 and A1 device address pins must be tied to a logic level.
3
FN8166.5
April 13, 2007
X9251
Pin Descriptions
Supply Pins
Bus Interface Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
SERIAL OUTPUT (SO)
The VCC pin is the system supply voltage. The VSS pin is
the system ground.
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.
Other Pins
SERIAL INPUT (SI)
NO CONNECT
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the device registers are input on
this pin. Data is latched by the rising edge of the serial clock.
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
SERIAL CLOCK (SCK)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
The SCK input is used to clock data into and out of the
X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is brought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
DEVICE ADDRESS (A1 AND A0)
The address inputs are used to set the two least significant
bits of the slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9251. Device pins A1 and
A0 must be tied to a logic level which specifies the internal
address of the device, see Figures 2, 3, 4, 5 and 6.
HARDWARE WRITE PROTECT INPUT (WP)
Principles of Operation
The X9251 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and a serial
interface providing direct communication between a host
and the potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin is an
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the SO pin
is at high impedance, and (unless an internal write cycle is
underway) the device is in the standby state. CS LOW
enables the X9251, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of RH and RL such that
RH0 and RL0 are the terminals of DCP0 and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of RW such that RW0 is the terminals of
DCP0 and so on.
4
FN8166.5
April 13, 2007
X9251
One of Four Potentiometers
RH
#: 0, 1, 2, or 3
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
DR#1
8
DR#2
IF WCR = 00[H] then RW is closet to RL
IF WCR = FF[H] then RW is closet to RH
8
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR#)
DR#3
COUNTER
--DECODE
DCP
CORE
RW
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power Up and Down Recommendations
Data Registers (DR)
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW (i.e., VCC ≥ VH, VL,
VW). The VCC ramp rate specification is always in effect.
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.
5
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP = 0, indicates that no high-voltage write cycle is
in progress.
FN8166.5
April 13, 2007
X9251
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
(MSB)
(LSB)
TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
Serial Interface
The X9251 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in,
on the rising SCK. CS must be LOW and the HOLD and WP
pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
Identification Byte
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the Identification Byte are a
Device Type Identifier, ID[3:0]. For the X9251, this is fixed as
0101 (refer to Table 3).
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0,
A1 is the logic value at the input pin A1, and A0 is the logic
value at the input pin A0. Only the device which Slave
Address matches the incoming bits sent by the master
executes the instruction. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
Instruction Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below in
Table 4.
TABLE 3. IDENTIFICATION BYTE FORMAT
Device Type
Identifier
Slave Address
ID3
ID2
ID1
ID0
A3
A2
A1
A0
0
1
0
1
0
0
Pin A1
Logic Value
Pin A0
Logic Value
(MSB)
(LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
Register
Selection
Instruction
Opcode
I3
I2
I1
I0
(MSB)
RB
DCP Selection
(WCR Selection)
RA
P1
P0
(LSB)
Data Register Selection
REGISTER
RB
RA
DR#0
0
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
#: 0, 1, 2, or 3
6
FN8166.5
April 13, 2007
X9251
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3
I2
I1
I0
RB
RA
P1
P0
OPERATION
Read Wiper Counter Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter Register
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed to
by P1 - P0 and RB - RA
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
1/0
1/0
Transfer the contents of the Data Register pointed to
by P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
1/0
1/0
Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed
to by RB - RA
Global XFR Data Registers to
Wiper Counter Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers pointed
to by RB - RA of all four pots to their respective
Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
1/0
1/0
Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,
• Write Wiper Counter Register – change current wiper
position of the selected potentiometer,
• Read Data Register – read the contents of the selected
Data Register,
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register. The
Read Status Register instruction is the only unique format
(See Figure 5).
Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9251; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are:
• Write Data Register – write a new value to the selected
Data Register,
• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• Read Status – this command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
7
• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
FN8166.5
April 13, 2007
X9251
Increment/Decrement Command
For each SCK clock pulse (tHIGH) while SI is HIGH, the
selected wiper moves one wiper position towards the RH
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position towards
the RL terminal. A detailed illustration of the sequence and
timing for this operation are shown. See Instruction format
for more details.
The final command is Increment/Decrement (See Figures 6
and 7). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9251 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
CS
SCK
SI
0
1
0
1
0
0
ID3
ID2
ID1
ID0
0
0
A1
A0
INTERNAL
ADDRESS
DEVICE ID
I3
I2
I1
RB
I0
INSTRUCTION
OPCODE
RA
P1
REGISTER
ADDRESS
P0
DCP/WCR
ADDRESS
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
A1
A0
I3
I1
I0
INSTRUCTION
OPCODE
INTERNAL
ADDRESS
DEVICE ID
I2
RB RA P1 P0
D7
D6 D5 D4
D3
D2
D1 D0
DATA FOR WCR[7:0] OR DR[7:0]
REGISTER DCP/WCR
ADDRESS ADDRESS
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
X
A1
A0
INTERNAL
ADDRESS
DEVICE ID
I3
I2
I1
I0
INSTRUCTION
OPCODE
RB RA P1 P0
X
X
X
X
X
X
X
DON’T CARE
REGISTER DCP/WCR
ADDRESS ADDRESS
S0
D7
D6 D5 D4
D3
D2
D1 D0
WCR[7:0]
OR
DATA REGISTER BIT [7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
8
FN8166.5
April 13, 2007
X9251
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
1
A1
A0
INTERNAL
ADDRESS
DEVICE ID
I3
0
1
1
I2
I1
I0
INSTRUCTION
OPCODE
0
RB RA
0
0
0
0
0
P1 P0
0
WIP
REGISTER POT/WCR
ADDRESS ADDRESS
STATUS
BIT
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)
CS
SCK
SI
0
ID3
1
0
ID2
ID1
1
0
0
ID0
0
0
DEVICE ID
A1
A0
INTERNAL
ADDRESS
I2
I3
I1
I0
INSTRUCTION
OPCODE
RB RA P1 P0
REGISTER POT/WCR
ADDRESS ADDRESS
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
tWRID
SCK
SI
VOLTAGE OUT
RW
INC/DEC CMD ISSUED
FIGURE 7. INCREMENT/DECREMENT TIMING SPEC
9
FN8166.5
April 13, 2007
X9251
Instruction Format
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
0
WCR
Addresses
0
1
0
0
Wiper Position
(Sent by X9251 on SO)
0
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
0
CS
Rising
Edge
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
0
1
WCR
Addresses
0
0
0
0
Data Byte
(Sent by Host on SI)
W W W W W W W W
C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
0
CS
Rising
Edge
Read Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
1
0
1
DR and WCR
Addresses
1
RB
RA
P1
Data Byte
(Sent by X9271 on SO)
P0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Rising
Edge
Write Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
1
0
0
DR and WCR
Addresses
RB
RA
P1
Data Byte
(Sent by Host on SI)
D D D D D D D D
7 6 5 4 3 2 1 0
P0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
0
0
0
DR
Addresses
1
RB
RA
0
0
CS
Rising
Edge
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Counter Register
3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
10
FN8166.5
April 13, 2007
X9251
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
0
0
DR
Addresses
0
RB
RA
0
CS
Rising
Edge
0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
Device
Addresses
1
0
0
A1
Instruction
Opcode
A0
1
1
1
DR and WCR
Addresses
0
RB
RA
0
CS
Rising
Edge
0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
1
1
0
DR and WCR
Addresses
1
RB
RA
0
0
CS
Rising
Edge
Increment/Decrement Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
0
0
1
WCR
Addresses
0
X
X
0
Increment/Decrement
(Sent by Master on SI)
0
I/D
I/D
.
.
.
.
I/D
I/D
CS
Rising
Edge
Read Status Register (SR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
0
0
A1
Instruction
Opcode
A0
0
1
0
WCR
Addresses
1
0
0
0
Data Byte
(Sent by X9251 on SO)
1
0
0
0
0
0
0
0
WIP
CS
Rising
Edge
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Counter Register
3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
11
FN8166.5
April 13, 2007
X9251
Absolute Maximum Ratings
Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SCK, CS, SI, SO, WP, HOLD, VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) Limits (Note 4)
X9251. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9251-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
RTOTAL
End to End Resistance
T version
100
RTOTAL
End to End Resistance
U version
50
End to End Resistance Tolerance
RW
Wiper Resistance
IW =
IW =
VTERM
V(VCC)
RTOTAL
V(VCC)
RTOTAL
Voltage on any RH or RL Pin
VSS = 0V
Noise (Note 6)
Ref: 1V
UNITS
kΩ
kΩ
±20
%
300
Ω
220
Ω
@ VCC = 3V
@ VCC = 5V
VSS
Resolution
CH/CL/CW
MAX
Absolute Linearity (Note 1)
Rw(n)(actual) - Rw(n)(expected) (Note 5)
Relative Linearity (Note 2)
Rw(n + 1) - [Rw(n) + MI] (Note 5)
VCC
V
-120
dBV/√Hz
0.4
%
-1
+1
MI (Note 3)
-0.6
+0.6
MI (Note 3)
Temperature Coefficient of RTOTAL
(Note 6)
±300
ppm/°C
Ratiometric Temp. Coefficient
(Note 6)
±20
ppm/°C
Potentiometer Capacitances
See Macro model, (Note 6)
10/10/25
pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/255 or (RH - RL)/255, single pot
4. During power up VCC > VH, VL, and VW.
5. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
12
FN8166.5
April 13, 2007
X9251
DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP
MAX
UNITS
400
μA
5
mA
ICC1
VCC supply current
(active)
fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC2
VCC supply current
(non-volatile write)
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ISB
VCC current (standby)
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
3
μA
1
ILI
Input leakage current
VIN = VSS to VCC
10
μA
ILO
Output leakage current
VOUT = VSS to VCC
10
μA
VIH
Input HIGH voltage
VCC x 0.7
V
VIL
Input LOW voltage
VOL
Output LOW voltage
IOL = 3mA
VOH
Output HIGH voltage
IOH = -1mA, VCC ≥ +3V
VCC - 0.8
V
VOH
Output HIGH voltage
IOH = -0.4mA, VCC ≤ +3V
VCC - 0.4
V
VCC x 0.3
V
0.4
V
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
UNITS
100,000
Data changes per bit per register
100
years
Capacitance
SYMBOL
TEST
TYP
UNITS
VOUT = 0V
8
pF
Output capacitance (SO)
VOUT = 0V
8
pF
Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
VIN = 0V
6
pF
CIN/OUT (Note 6) Input/Output capacitance (SI)
COUT (Note 6)
CIN (Note 6)
TEST CONDITIONS
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
tr VCC (Note 6)
VCC Power-up rate
tPUR (Note 7)
Power-up to initiation of read operation
1
ms
tPUW (Note 7)
Power-up to initiation of write operation
50
ms
0.2
V/ms
A.C. Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
NOTES:
6. This parameter is not 100% tested
7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
13
FN8166.5
April 13, 2007
X9251
Equivalent A.C. Load Circuit
VCC
SPICE Macromodel
2kΩ
RTOTAL
RL
RH
SO pin
CW
CL
2kΩ
10pF
CL
10pF
25pF
10pF
RW
AC TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
2
MHz
fSCK
SPI clock frequency
tCYC
SPI clock cycle rime
500
ns
tWH
SPI clock high rime
200
ns
tWL
SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
μs
tFI
SI, SCK, HOLD and CS input fall time
2
μs
250
ns
200
ns
tDIS
SO output disable time
tV
SO output valid time
0
tHO
SO output hold time
tRO (Note 6)
SO output rise time
100
ns
tFO (Note 6)
SO output fall time
100
ns
tHOLD
0
HOLD time
ns
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
10
ns
tCS
CS deselect time
2
μs
tWPASU
WP, A0 setup time
0
ns
tWPAH
WP, A0 hold time
0
ns
High-Voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
High-voltage write cycle time (store instructions)
TYP
MAX
UNITS
5
10
ms
XDCP Timing
SYMBOL
tWRPO (Note 6)
tWRL (Note 6)
MIN
MAX
UNITS
Wiper response time after the third (last) power supply is stable
PARAMETER
5
10
μs
Wiper response time after instruction issued (all load instructions)
5
10
μs
14
FN8166.5
April 13, 2007
X9251
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Input Timing
tCS
CS
SCK
tSU
tH
tLAG
tCYC
tLEAD
...
tWH
tWL
...
SI
MSB
SO
HIGH IMPEDANCE
tRI
tFI
LSB
Output Timing
CS
SCK
...
tV
MSB
SO
SI
tHO
tDIS
...
LSB
ADDR
15
FN8166.5
April 13, 2007
X9251
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
...
MSB
LSB
VWx
SO
HIGH IMPEDANCE
Write Protect and Device Address Pins Timing
(ANY INSTRUCTION)
CS
tWPASU
tWPAH
WP
A0
A1
16
FN8166.5
April 13, 2007
X9251
Applications information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal
Potentiometer;
Variable voltage divider
Two terminal Variable
Resistor;
Variable current
Application Circuits
NON INVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
}
10kΩ
}
TL072
10kΩ
VO
R1
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
17
FN8166.5
April 13, 2007
X9251
Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
R2
R1
VO
–
–
VS
+
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
VS
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
18
FN8166.5
April 13, 2007
X9251
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
19
FN8166.5
April 13, 2007
X9251
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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20
FN8166.5
April 13, 2007