TC74VHC273F/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC273F,TC74VHC273FT,TC74VHC273FK Octal D-Type Flip-Flop with Clear The TC74VHC273 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLR input is held “L”, the Q outputs are at a low logic level independent of the other inputs. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. TC74VHC273F TC74VHC273FT Features • High speed: fmax = 165 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Power down protection is provided on all inputs. Balanced propagation delays: tpLH ∼ − tpHL • • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Low noise: VOLP = 0.8 V (max) • Pin and function compatible with 74ALS273 TC74VHC273FK Weight SOP20-P-300-1.27A TSSOP20-P-0044-0.65A VSSOP20-P-0030-0.50 1 : 0.22 g (typ.) : 0.08 g (typ.) : 0.03 g (typ.) 2012-08-04 TC74VHC273F/FT/FK Pin Assignment IEC Logic Symbol CLR CK CLR 1 20 VCC Q1 2 19 Q8 D1 3 18 D8 D1 D2 4 17 D7 D3 Q2 D4 Q3 6 15 Q6 D3 7 14 D6 D4 8 13 D5 Q4 9 12 Q5 GND 10 11 CK D5 D6 D7 D8 R C1 (3) (2) 1D (4) D2 Q7 16 5 (1) (11) Q1 (5) (7) (6) (8) (9) (13) (12) (14) (15) (17) (18) (16) (19) Q2 Q3 Q4 Q5 Q6 Q7 Q8 (top view) Truth Table Inputs Output Function CLR D CK Q L X X L Clear H L L ― H H H ― H X Qn No Change X: Don’t care System Diagram CLR 1 D1 3 D2 4 D R CK CK D3 7 D R Q CK D R Q D5 13 D4 8 CK D R Q CK D6 14 D R Q CK D7 17 D R Q CK D8 18 D R Q CK D R Q CK Q 11 2 Q1 5 Q2 6 9 Q3 Q4 2 12 Q5 15 16 Q6 19 Q7 Q8 2012-08-04 TC74VHC273F/FT/FK Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to 7.0 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK −20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±75 mA Power dissipation PD 180 mW Storage temperature Tstg −65 to 150 °C DC output voltage Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to 5.5 V VOUT 0 to VCC V Operating temperature Topr −40 to 85 °C Input rise and fall time dt/dv Output voltage Note: 0 to 100 (VCC = 3.3 ± 0.3 V) 0 to 20 (VCC = 5 ± 0.5 V) ns/V The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 3 2012-08-04 TC74VHC273F/FT/FK Electrical Characteristics DC Characteristics Characteristics VCC (V) Min Typ. Max Min Max 2.0 1.50 ⎯ ⎯ 1.50 ⎯ 3.0 to 5.5 VCC × 0.7 ⎯ ⎯ 2.0 ⎯ ⎯ 0.50 3.0 to 5.5 ⎯ ⎯ VCC × 0.3 ⎯ VCC × 0.3 2.0 1.9 2.0 ⎯ 1.9 ⎯ 3.0 2.9 3.0 ⎯ 2.9 ⎯ 4.5 4.4 4.5 ⎯ 4.4 ⎯ IOH = −4 mA 3.0 2.58 ⎯ ⎯ 2.48 ⎯ IOH = −8 mA 4.5 3.94 ⎯ ⎯ 3.80 ⎯ 2.0 ⎯ 0.0 0.1 ⎯ 0.1 3.0 ⎯ 0.0 0.1 ⎯ 0.1 4.5 ⎯ 0.0 0.1 ⎯ 0.1 IOL = 4 mA 3.0 ⎯ ⎯ 0.36 ⎯ 0.44 IOL = 8 mA 4.5 ⎯ ⎯ 0.36 ⎯ 0.44 High-level input voltage VIH ⎯ Low-level input voltage VIL ⎯ IOH = −50 μA High-level output voltage VOH VIN = VIH or VIL IOL = 50 μA Low-level output voltage VOL Ta = −40 to 85°C Ta = 25°C Test Condition Symbol VIN = VIH or VIL VCC × 0.7 ⎯ ⎯ Unit V 0.50 V V V Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ⎯ ⎯ 4.0 ⎯ 40.0 μA Ta = −40 to 85°C Unit Timing Requirements (input: tr = tf = 3 ns) Characteristics Minimum pulse width (CK) Symbol tw (L) ⎯ tw (H) tw (L) ⎯ Minimum set-up time ts ⎯ Minimum hold time th ⎯ trem ⎯ Minimum pulse width ( CLR ) Minimum removal time ( CLR ) Ta = 25°C Test Condition 4 VCC (V) Typ. Limit Limit 3.3 ± 0.3 ⎯ 5.5 6.5 5.0 ± 0.5 ⎯ 5.0 5.0 3.3 ± 0.3 ⎯ 5.0 6.0 5.0 ± 0.5 ⎯ 5.0 5.0 3.3 ± 0.3 ⎯ 5.5 6.5 5.0 ± 0.5 ⎯ 4.5 4.5 3.3 ± 0.3 ⎯ 1.0 1.0 5.0 ± 0.5 ⎯ 1.0 1.0 3.3 ± 0.3 ⎯ 2.5 2.5 5.0 ± 0.5 ⎯ 2.0 2.0 ns ns ns ns ns 2012-08-04 TC74VHC273F/FT/FK AC Characteristics (input: tr = tf = 3 ns) Characteristics VCC (V) Propagation delay time tpLH (CK-Q) tpHL Propagation delay time Min Typ. Max Min Max 15 ⎯ 8.7 13.6 1.0 16.0 50 ⎯ 11.2 17.1 1.0 19.5 15 ⎯ 5.8 9.0 1.0 10.5 50 ⎯ 7.3 11.0 1.0 12.5 15 ⎯ 8.9 13.6 1.0 16.0 50 ⎯ 11.4 17.1 1.0 19.5 15 ⎯ 5.2 8.5 1.0 10.0 50 ⎯ 6.7 10.5 1.0 12.0 15 75 120 ⎯ 65 ⎯ 50 50 75 ⎯ 45 ⎯ 15 120 165 ⎯ 100 ⎯ 50 80 110 ⎯ 70 ⎯ 3.3 ± 0.3 50 ⎯ ⎯ 1.5 ⎯ 1.5 5.0 ± 0.5 50 ⎯ ⎯ 1.0 ⎯ 1.0 ⎯ 4 10 ⎯ 10 pF ⎯ 31 ⎯ ⎯ ⎯ pF 3.3 ± 0.3 ⎯ 5.0 ± 0.5 ⎯ ( CLR -Q) 5.0 ± 0.5 3.3 ± 0.3 Maximum clock frequency fmax ⎯ 5.0 ± 0.5 Output to output skew tosLH tosHL Input capacitance CIN Power dissipation capacitance CPD (Note 1) Unit CL (pF) 3.3 ± 0.3 tpHL Ta = −40 to 85°C Ta = 25°C Test Condition Symbol ⎯ (Note 2) ns ns MHz ns Note 1: Parameter guaranteed by design. tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn| Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC/8 (per bit) And the total CPD when n pcs.of flip flop operate can be gained by the following equation: CPD (total) = 22 + 9·n Noise Characteristics (input: tr = tf = 3 ns) Characteristics Ta = 25°C Test Condition Symbol VCC (V) Typ. Max Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 0.5 0.8 V Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 −0.5 −0.8 V Minimum high level dynamic input voltage VIHD CL = 50 pF 5.0 ⎯ 3.5 V Maximum low level dynamic input voltage VILD CL = 50 pF 5.0 ⎯ 1.5 V 5 2012-08-04 TC74VHC273F/FT/FK Input Equivalent Circuit INPUT 6 2012-08-04 TC74VHC273F/FT/FK Package Dimensions Weight: 0.22 g (typ.) 7 2012-08-04 TC74VHC273F/FT/FK Package Dimensions Weight: 0.08 g (typ.) 8 2012-08-04 TC74VHC273F/FT/FK Package Dimensions Weight: 0.03 g (typ.) 9 2012-08-04 TC74VHC273F/FT/FK RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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