FSSD07 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Features Description On Resistance: 5Ω Typical, VDDC=2.7V ftoggle: >75MHz Low On Capacitance: 6pF Typical Low Power Consumption: 2µA Maximum Supports Secure Digital (SD), Secure Digital I/O The FSSD07 is a 2:1 multiplexer that allows dual Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) host controllers to share a common peripheral. The host controllers can be equal to, greater than, or less than peripheral card supply with minimal power consumption. This configuration enables dual host CMD, CLK, and D[3:0] signals to be multiplexed to a common peripheral. Supports 1-Bit / 4-Bit Host Controllers (VDDH1/H2=1.65V The architecture includes the necessary bi-directional data and command transfer capability for single highvoltage cards or dual-voltage supply cards. The clock path is a uni-directional buffer. (SDIO), and Multimedia Card (MMC) Specifications to 3.6V) Communicating with High-Voltage (2.7-3.6V) and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V) Typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, set-top boxes, and notebooks. VDDC=1.65 to 3.6V, VDDH1/H2=1.65 to 3.6V 24-Lead MLP and UMLP Packages Applications Cell Phone, PDA, Digital Camera, Portable GPS, and Notebook Computer LCD Monitor, TV, and Set-Top Box Related Resources FSSD07 Evaluation Board Evaluation Board Users Guide For samples, questions, or board requests; please contact [email protected] Figure 1. Analog Symbol Diagram Ordering Information Part Number Top Mark Operating Temperature Range FSSD07BQX FSSD07 -40°C to +85°C 24-Lead Molded Leadless Package (MLP), JEDEC MO-220, 3.5 x 4.5mm Tape & Reel FSSD07UMX JK -40°C to +85°C 24-Lead Ultra-thin Molded Leadless Package (UMLP), 0.4mm pitch Tape & Reel © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 Package Description Packing Method www.fairchildsemi.com FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer March 2012 CMD 5 20 1DAT[0] VDDC 6 19 1DAT[1] GND 7 18 CLK 8 17 2DAT[3] 2DAT[2] 2CMD 15 VDDH2 Figure 2. OE 1DAT[2] 1DAT[3] 1CMD VDDH1 21 20 19 1 18 1CLK CMD 2 17 1DAT[0] VDDC 3 16 1DAT[1] GND 4 15 2DAT[2] CLK 5 14 2DAT[3] DAT[0] 6 13 2CMD 2CLK 2DAT[0] 16 10 S 9 DAT[1] 2DAT[1] DAT[0] 13 14 22 MLP Pin Assignments 7 8 Figure 3. 9 10 11 12 2CLK 21 1CLK 12 23 DAT[3] VDDH2 4 11 24 VDDH1 2DAT[0] 22 3 S 1DAT[3] 1CMD 23 DAT[2] OE 1DAT[2] 24 2DAT[1] DAT[3] 1 DAT[1] DAT[2] 2 UMLP Pin Assignments Pin Definitions Pin# MLP Pin# UMLP Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1DAT[2] OE DAT[2] DAT[3] CMD VDDC GND CLK DAT[0] DAT[1] S 2DAT[1] 2DAT[0] 2CLK VDDH2 2CMD 2DAT[3] 2DAT[2] 1DAT[1] 1DAT[0] 1CLK VDDH1 1CMD 1DAT[3] Description SDIO Common Port Output Enable (Active HIGH) SDIO Common Port Power Supply (SDIO Peripheral Card Port) Ground Clock Path Port FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Pin Configuration SDIO Common Port Select Pin Host Common Port Clock Path Port Power Supply (Host Port) Host Common Port Clock Path Port Power Supply (SDIO Host Port) Host Common Port Truth Table OE S Function HIGH LOW 1CMD, 1CLK, 1DAT[3:0] connected to CMD, CLK, DAT[3:0] HIGH HIGH 2CMD, 2CLK,2DAT[3:0] connected to CMD, CLK, DAT[3:0] LOW X CMD, DAT[3:0] ports high impedance; CLK is function of selected nCLK © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 2 VDDC 1.65V to 3.6V RCMD , RDAT[3:0] VDDH1 FSSD07 1.65V to 3.6V CMD, DAT[3:0] WiFi, Bluetooth, MMC or SD Peripheral 1CMD, 1DAT[3:0] 5 Processor #1 5 1CLK CLK Secure Data/ Multi Media Card Dual Host Selector VDDH2 1.65V to 3.6V SD Card R1CMD, 2CMD = 10k to 100k ohm R1DAT[3:0] , 2DAT[3:0] = 10k to 100k ohm 2CMD, 2DAT[3:0] MMC Card R1CMD, 2CMD = 4.7k to 100k ohm R1DAT[3:0], 2DAT[3:0] = 50k to 100k ohm 5 2CLK OE S GND Figure 4. Typical Application Diagram © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 Processor #2 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Typical Application www.fairchildsemi.com 3 The FSSD07 enables the multiplexing of dual ASIC / baseband processor hosts to a common peripheral card or module, providing bi-directional support of the dualvoltage SD/SDIO or MMC cards available in the marketplace. Each host SDIO port has its own supply rail, such that hosts with different supplies can be interfaced to a common peripheral module or card. The peripheral card supply must be equal to or greater than the host(s) to minimize power consumption. The independent VDDC, VDDH1, and VDDH2 are defined by the supplies connected from the application Power Management ICs (PMICs) to the FSSD07. The clock path is a uni-directional buffered path rather than a bidirectional switch port. The supplies (VDDC, VDDH1, and VDDH2) have an internal termination resistor (typically 3M) to ensure the supply rails internally do not float if the application turns off one or all of these sources. IDLE State & Power-Up CMD/DAT Bus “Parking” The SD and MMC card specifications were written for a direct point-to-point communication between host controller and card. The introduction of the FSSD07 in that path, as an expander, requires that the functional operation and system latency not be impacted by the switch characteristics. Since there are various card formats, protocols, and configurable controllers, an OE pin is available to facilitate a fast IDLE transition for the CMD/DAT[3:0] outputs. Some controllers, rather than placing CMD/DAT into high-impedance mode, pull the outputs HIGH for a clock cycle prior to going into highimpedance mode (referred to as “parking” the output). Some legacy controllers pull their outputs HIGH versus high impedance. If the OE pin is pulled HIGH and the controller places its command and data outputs into high-impedance (driving nCMD/nDAT[3:0]), the FSSD07 CMD/DAT[3:0] output rise time is a function of the RC time constant through the switch path. Pulling OE LOW puts the switches into high impedance, disabling communication from the host to card, and the CMD/DAT[3:0] outputs are pulled HIGH by the system pull-up resistors chosen for the application. This mechanism facilitates power-up sequencing by holding OE LOW until supplies are stable and communication between the host(s) and card is enabled. CMD, DAT Bus Pull-ups The CMD and DAT[3:0] ports do not have, internally, the system pull-up resistors as defined in the MMC or SD card system bus specifications. The system bus pull-up must be added external to the FSSD07. The value, within the specific specification limits, is a function of the individual application and type of card or peripheral connected. For SD card applications, the RCMD and RDAT pull-ups should be between 10kΩ and 100kΩ. For MMC applications, the RCMD pull-ups should be between 4.7kΩ and 100kΩ, and the RDAT pull-ups between 50kΩ and 100kΩ. The card-side CMD and DAT[3:0] outputs have a circuit that facilitates incident wave switching, so the external pull-up resistors ensure retention of the output high level. Power Optimization FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Functional Description Since the FSSD07 has multiple supplies (VDDC, VDDH1, and VDDH2), the control signals have been referenced to the card peripheral side (VDDC). To minimize power consumption, current paths between supplies are isolated when one or more supplies are not present. This includes the configuration of the removal of VDDC with host controller supplies remaining present. The OE pin can be used to place the CMD and DAT[3:0] into high-impedance mode during power-up sequencing or when the system enters IDLE state (see IDLE State CMD/DAT Bus “Parking”). CLK Bus The 1CLK and 2CLK inputs are bi-state buffer architectures, rather than a switch I/O, to ensure 52MHz incident wave switching. Since most host controllers also have a clock enable register bit to enable or disable the system clock when in IDLE mode, the CLK output is not disabled by the OE pin. Instead, the CLK output is a function of whichever host controller clock is selected by the S pin. Consequently, there is always a clock path connected between the selected host and the card. The state of the CLK pin is a function of the selected host controller nCLK output pin, which facilitates retaining clock duty cycle in the system or performing read / wait operations. © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDDC Parameter Conditions Card Supply Voltage VDDH1,VDDH2 Host Controller Supply Voltage VSW VCNTRL VCLKI 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD Pins Switch I/O Voltage(1) Control Input Voltage(1) CLK Input Voltage (1) (1) Min. Max. Unit -0.5 4.6 V -0.5 4.6 V -0.5 (2) VDDx + 0.3V (4.6V maximum) V (2) VDDx + DAT[3:0], CMD Pins -0.5 0.3V (4.6V maximum) V S, OE -0.5 4.6 V 1CLK, 2CLK -0.5 4.6 V -0.5 (2) VDDx + 0.3V (4.6V maximum) V -50 mA VCLKO CLK Output Voltage IINDC Input Clamp Diode Current ISW Switch I/O Current SDIO Continuous 50 mA Peak Switch Current SDIO Pulsed at 1ms Duration, <10% Duty Cycle 100 mA +150 C +150 C +260 C ISWPEAK TSTG CLK Storage Temperature Range -65 TJ Maximum Junction Temperature TL Lead Temperature ESD Soldering, 10 Seconds Human Body Model, JEDEC: JESD22-A114 I/O to GND 8 Supply to GND 10 All Other Pins 5 Charged Device Model, JEDEC-JESD-C101 kV FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Absolute Maximum Ratings 2 Notes: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. 2. VDDx references the specific SDIO port VDD rail (i.e. VDDH1, VDDH2, VDDC). Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDDC VDDH1, VDDH2 VCNTRL VCLKI VSW Parameter Min. Max. Unit Supply Voltage - Card Side 1.65 3.60 V Supply Voltage - Dual Host Controller 1.65 3.60 V Control Input Voltage - VS, VOE 0 VDDC V Clock Input Voltage - VCLKI 0 VDDH1/H2 V CMD, DAT[3:0] 0 VDDC V 1CMD, 1DAT[3:0] 0 VDDH1 V 2CMD, 2DAT[3:0] 0 VDDH2 V -40 +85 °C +50 °C/W Switch I/O Voltage TA Operating Temperature JA Thermal Resistance, Free Air © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 MLP Package www.fairchildsemi.com 5 All typical values are for VDDC=1.8V at 25°C unless otherwise specified. Symbol Parameter VDDC (V) VDDH1 / VDDH2 (V) Conditions TA=-40 to +85°C Min. Typ. Max. Unit Common Pins VIK Clamp Diode Voltage 1.80 1.80 IIK=-18mA -1.2 VIH Control Input Voltage High 1.80 1.80 VIL Control Input Voltage Low 1.80 1.80 IIN S, OE Input High Current 1.95 1.95 VCNTRL=0V to VDDC IOZ Off Leakage, Current of all ports 1.95 1.95 VSW =0V to VDDC -1.0 VOHC CLK Output Voltage High(3) 1.95 1.95 IOH=-2mA 1.6 VOLC CLK Output Voltage (3) Low 1.65 1.65 IOL=-2mA 90 mV RON Switch On Resistance(4) 1.65 1.65 VCMD, DAT[3:0]=0V, ION=-2mA Figure 5 10 Ω ∆RON Delta On Resistance(3, 5) 1.65 1.65 VCMD, DAT[3:0]=0V, ION=- 2mA 1.3 V V -1 0.5 0.5 V 1 µA 1.0 µA V 0.85 Ω Power Supply ICC(VDDC) Quiescent Supply Current (Card) 1.95 0 VSW =0 or VDDC, IOUT=0 2 µA ICC(VDDH1/H2) Quiescent Supply Current (Hosts) 1.95 1.95 VSW =0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA Delta ICC(VDDH1, VDDH2) for One Host Powered Off 1.95 1.95 / 0 0 / 1.95 VSW =0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA ∆IHOST FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer DC Electrical Characteristics at 1.8V VDDC Notes: 3. Guaranteed by characterization, not production tested. 4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 5. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage. © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 6 All typical values are for VDDC=2.7V at 25°C unless otherwise specified. Symbol Parameter VDDC (V) VDDH1 / VDDH2 (V) Conditions TA=-40 to +85°C Min. Typ. Max. Unit Common Pins VIK Clamp Diode Voltage 2.7 2.7 IIK=-18mA -1.2 VIH Control Input Voltage High 2.7 2.7 VIL Control Input Voltage Low 2.7 2.7 IIN S, OE Input High Current 3.6 3.6 VCNTRL=0V to VDDC IOZ Off Leakage Current of all Ports 3.6 3.6 VSW =0V to VDDC -1.0 VOHC CLK Output Voltage (6) High 2.7 2.7 IOH=-2mA 2.4 VOLC CLK Output Voltage Low(6) 3.6 3.6 IOL=-2mA RON Switch On Resistance(7) 2.7 2.7 VCMD, DAT[3:0]=0V, ION=-2mA Figure 5 5.0 ∆RON Delta On Resistance(6, 8) 2.7 2.7 VCMD, DAT[3:0]=0V, ION=- 2mA 0.8 Quiescent Supply Current (Card) 3.6 0 Quiescent Supply Current (Hosts) 3.6 Delta ICC(VDDH1, VDDH2) for One Card Powered Off 3.6 1.8 V 0.8 -1 0.5 1 µA 1.0 µA V 90 mV 8.0 Ω Ω Power Supply ICC(VDDC) ICC (VDDH1/C2) ∆IHOST VSW =0 or VDDC, IOUT=0 2 µA 3.6 VSW =0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA 3.6 / 0 0 / 3.6 VSW =0 or VDDx, IOUT=0, VCLKI=VDDHX, VCLKO=Open, OE=VDDC 2 µA FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer DC Electrical Characteristics at 2.7V VDDC Notes: 6. Guaranteed by characterization, not production tested. 7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 8. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage. © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 7 All typical values are for VDDC=1.8V at 25°C unless otherwise specified. Symbol Parameter VDDH1 / VDDH2 (V) VDDC (V) Conditions TA=-40 to +85°C Min. Typ. Max. Unit tON Turn-On Time, S, OE to CMD, DAT[3:0] VSW =0V, RL=1kΩ, 1.65 to 1.95 1.65 to 3.6 CL=20pF Figure 7, Figure 8 8 18 ns tOFF Turn-Off Time, S, OE to CMD, DAT[3:0] VSW =0V, RL=1kΩ, 1.65 to 1.95 1.65 to 3.6 CL=20pF Figure 7, Figure 8 6 13 ns CMD/DAT Output Edge Rates RL=1kΩ, CL=20pF 1.65 to 1.95 1.65 to 3.6 (10-90%) Figure 7, Figure 8 3 tPD Switch Propagation Delay(9) 1.65 to 1.95 1.65 to 3.6 tpLH LH Propagation Delay 1CLK, 2CLK to CLK tpHL tRISE1/ FALL1 tRISE2/ FALL2 (9) RL=1kΩ, CL=20pF Figure 7, Figure 89 ns 4.5 9 ns CL=20pF 1.65 to 1.95 1.65 to 3.6 Figure 10, Figure 11 4 6 ns HL Propagation Delay 1CLK, 2CLK to CLK CL=20pF 1.65 to 1.95 1.65 to 3.6 Figure 10, Figure 11 4 6 ns CLK Output Edge Rates(9) 1.65 to 1.95 1.65 to 3.6 CL=20pF (10-90%) Figure 7, Figure 8 3 ns OIRR Off Isolation(9) 1.8 f=10MHz, RT=50Ω, 1.65 to 3.6 CL=20pF, Figure 12 -60 dB Xtalk Non-Adjacent Channel Crosstalk(9) 1.8 f=10MHz, RT=50Ω, 1.65 to 3.6 CL=20pF, Figure 13 -60 dB ftoggle Clock Frequency(9) 1.8 1.65 to 3.6 CL=20pF 75 MHz FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer AC Electrical Characteristics at 1.8V VDDC Note: 9. Guaranteed by characterization, not production tested. © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 8 All typical values are for VDDC=3.3V at 25°C unless otherwise specified. Symbol Parameter VDDC (V) VDDH1 / VDDH2 (V) Conditions TA=-40 to +85°C Min. Typ. Max. Unit tON Turn-On Time, S, OE to CMD, DAT[3:0] 2.7 to 3.6 1.65 to 3.6 VSW =0V, RL=1kΩ, CL=20pF Figure 7, Figure 8 8 18 ns tOFF Turn-Off Time, S, OE to CMD, DAT[3:0] 2.7 to 3.6 1.65 to 3.6 VSW =0V, RL=1kΩ, CL=20pF Figure 7, Figure 8 6 13 ns CMD/DAT Output Edge Rates(10) 2.7 to 3.6 1.65 to 3.6 RL=1kΩ, CL=20pF (1090%) Figure 7, Figure 8 3 tPD Switch Propagation Delay(10) 2.7 to 3.6 1.65 to 3.6 RL=1kΩ, CL=20pF Figure 7, Figure 8 tpLH LH Propagation Delay 1CLK, 2CLK to CLK 2.7 to 3.6 1.65 to 3.6 tpHL HL Propagation Delay 1CLK, 2CLK to CLK 2.7 to 3.6 FALL2 CLK Output Edge Rates(10) OIRR tRISE1/ FALL1 ns 2.5 6 ns CL=20pF Figure 10, Figure 11 4 6 ns 1.65 to 3.6 CL=20pF Figure 10, Figure 11 4 6 ns 2.7 to 3.6 1.65 to 3.6 CL=20pF (10-90%) Figure 7, Figure 8 3 ns Off Isolation(10) 2.7 1.65 to 3.6 f=10MHz, RT=50Ω, CL=20pF Figure 12 -60 dB Xtalk Non-Adjacent Channel Crosstalk(10) 2.7 1.65 to 3.6 f=10MHz, RT=50Ω, CL=20pF, Figure 13 -60 dB ftoggle Clock Frequency(10) 2.7 1.65 to 3.6 CL=20pF 75 MHz tRISE2/ FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer AC Electrical Characteristics at 3.3V VDDC Note: 10. Guaranteed by characterization, not production tested. Capacitance Symbol Parameter CIN(S, OE, Control and nCLK Pin Input Capacitance(11) CLK) TA=-40 to +85°C VDDC (V) VDDH1/H2 (V) 0 2.7 VDDC=0V 2.5 pF 7.5 pF 4 pF Conditions CON Common Port On Capacitance(11) (CDAT[3:0], CMD) 2.7 2.7 VOE=VDDC, Vbias=0.5V, f=1MHz Figure 14 COFF Input Source Off Capacitance(11) 2.7 2.7 VOE=0V, Vbias=0.5V, f=1MHz Figure 15 Min. Typ. Max. Unit Note: 11. Guaranteed by characterization, not production tested. © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 9 V ON I OZ NC nDAT[3:0],nCMD A DAT[3:0],CMD V IN V IN GND RON = Select VS = VON / ION Select I ON VS = GND 0 orVDDH 0 or VDDH Each switch port tested separately. Figure 5. On Resistance Figure 6. Off Leakage tRISE = 2.5ns Input - VCNTRL DAT[3:0], CMD VSW 90% 90% Vddx /2 Vddx /2 10% VOH V OUT CL RS 10% GND RL GND tFALL = 2.5ns Vddx V DDx nDAT[3:0],nCMD GND Output - VOUT VOL+ 0.15V VOL GND 50% tON tOFF VS FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Test Diagrams VOH GND RL , RS , and CL are functions of the application environment (see AC tables for specific values). CL includes test fixture and stray capacitance. Output - VOUT Figure 8. Turn On/Off Time Waveforms tFALL = 2.5ns 1CLK, 2CLK Vddx Input - VSW 10% GND VOL+ 0.15V tOFF tON Figure 7. AC Test Circuit Load tRISE = 2.5ns 50% VOL 90% Vddx /2 90% V ddx/2 CLK V CLKI GND R S 10% V OUT CL GND VOH Output-- VOUT VOL VS 50% 50% tpLH GND tpHL Figure 9. Switch Propagation Delay (tPD) Waveform © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 R L , R S and C L are function of application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance Figure 10. AC Test Circuit Load (CLK) www.fairchildsemi.com 10 t FALL = 2.5ns tRISE = 2.5ns Network Analyzer Vddx RS 90% Input - VCLKI 10% GND 90% V ddx /2 V ddx /2 GND RT 10% VS Output - VOUT GND V OUT GND RT RS and R T are functions of the application environment (see AC tables for specific values). 50% 50% VS GND GND VOHC V IN GND Off Isolation = 20 Log (VOUT / VIN ) VOL tpLH tpHL Figure 11. CLK Propagation Delay Waveforms Figure 12. Channel Off Isolation Network Analyzer NC RS GND V IN VS VS GND GND FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Test Diagrams (Continued) RT GND GND RT VOUT RS and RT are functions of the application environment GND (see AC tables for specific values). Crosstalk = 20 Log (VOUT / VIN ) Figure 13. Channel-to-Channel Crosstalk nDAT[3:0], nCMD, nCLK Capacitance Meter f = 1MHz Capacitance Meter S VS = 0 or Vddh S VS = 0 orVddh f = 1MHz nDAT[3:0], nCMD, nCLK nDAT[3:0], nCMD, nCLK Figure 14. Channel On Capacitance © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 Figure 15. Channel Off Capacitance www.fairchildsemi.com 11 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Physical Dimensions Figure 16. 24-Lead, Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Always visit Fairchild Semiconductor’s online packaging area for the most recent container drawings: http://www.fairchildsemi.com/packaging/MLP24B_TNR.pdf. © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 12 2.80 2.23 0.66 0.10 C A 2.50 2X 24 B 0.56 19 1 0.40 2.23 PIN #1 IDENT 3.70 3.40 13 7 0.10 C 0.23 2X TOP VIEW RECOMMENDED LAND PATTERN 0.55 MAX. 0.10 C 0.15 SEATING PLANE 0.08 C C 0.05 0.00 SIDE VIEW 7 23X 0.35 0.45 13 0.40 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer Physical Dimensions 1 0.45 0.55 24 19 BOTTOM VIEW 0.15 24X 0.25 0.10 C A B 0.05 C Figure 17. 24-Lead, Ultra-thin Molded Leadless Package (UMLP), 0.4mm pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/MicroMLP24_TNR.pdf © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 13 FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer © 2007 Fairchild Semiconductor Corporation FSSD07 Rev. 1.0.2 www.fairchildsemi.com 14