NSBMC096 NSBMC096 Burst Memory Controller Literature Number: SNOS687A NSBMC096-16/-25/-33 Burst Memory Controller General Description e The NSBMC096 has been designed to allow maximum flexibility in its application. The full range of processor speeds is supported for a wide range of DRAM speeds, sizes and organizations. No glue logic is required because the bus interface is customized to the i960 CA/CF. System integration is further enhanced by providing a 24-bit heartbeat timer and a bus watch timer on-chip. The NSBMC096 is packaged as a 132-pin PQFP with a footprint of only 1.3 square inches. It reduces design complexity, space requirements and is fully derated for loading, temperature and voltage. Features Y Y Interfaces directly to the i960 CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer/Drivers Supports DRAMs trom 256 kB to 64 MB Bit counter/timer Non-interleaved or two way interleaved operation 5-Bit Bus Watch Timer Software-configured operational parameters High-Speed/Low Power CMOS technology et The NSBMC096 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an i960É CA/CF SuperScalar Embedded Processor. The NSBMC096 is functionally equivalent to the V96BMC TM . The extremely high instruction rate achieved by these processors place extraordinary demands on memory system design if maximum throughput is to be sustained and costs minimized. Static RAM offers a simple solution for high speed memory systems. However, high cost and low density make this an expensive and space consumptive choice. Dynamic RAMs are an attractive alternative with higher density and low cost. Their drawbacks are, slower access time and more complex control circuitry required to operate them. The access time problem is solved if DRAMs are used in page mode. In this mode, access times rival that of static RAM. The control circuit problem is resolved by the NSBMC096. The function that the NSBMC096 performs is to optimally translate the burst access protocol of the i960 CA/CF to the page mode access protocol supported by dynamic RAMs. The device manages one or two-way interleaved arrangements of DRAMs such that during burst access, data can be read, or written, at the rate of one word per system clock cycle. Y Y Y Y Y Y bs ol Y Y O Block Diagram TL/V/11805 – 1 This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications of this product without notice. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. NSBMC096TM and WATCHDOGTM are trademarks of National Semiconductor Corporation. i960É is a registered trademark of Intel Corporation. V96BMCTM is a trademark of V3 Corporation. C1995 National Semiconductor Corporation TL/V/11805 RRD-B30M115/Printed in U. S. A. NSBMC096-16/-25/-33 Burst Memory Controller August 1993 e Logic and Connection Diagrams O bs ol et TL/V/11805 – 2 TL/V/11805 – 3 Order Number NSBMC096VF See Package Number VF132A 2 Pin Descriptions TABLE I Signal Name Pin Ý Signal Name Pin Ý Signal Name 1 2 3 4 5 6 A14 A15 A16 VCC A17 A19 44 45 46 47 48 53 LEB TXA TXB VCC VSS AA0 91 92 93 94 95 96 VCC VSS AB4 AB5 AB6 AB7 7 8 9 10 11 12 A20 A18 A21 A24 A22 A23 54 55 56 57 58 59 AA1 AA2 AA3 VCC VSS AA4 97 98 99 100 101 102 VCC VSS AB8 AB9 AB10 AB11 13 14 15 19 20 21 A26 A25 A27 A31 A28 A29 60 61 62 63 64 65 AA5 AA6 AA7 VCC VSS AA8 103 104 105 106 107 108 VCC VSS CASB0 CASB1 CASB2 CASB3 22 23 24 25 26 27 A30 D/C SUP PCLK INT BERR 66 67 68 69 70 71 28 29 30 31 32 33 W/R BE0 DEN BLAST BE1 VSS 72 73 74 75 76 77 34 35 36 37 38 39 ADS BE2 BE3 BTERM READY ID0 40 41 42 43 ID1 ID2 REFRESH LEA et e Pin Ý 109 110 111 112 113 114 VCC VSS RASB0 RASB1 RASB2 RASB3 CASA1 CASA2 CASA3 VCC VSS RASA0 115 118 119 120 121 122 VCC MWEB VSS RESET A2 A3 78 79 80 81 82 86 RASA1 RASA2 RASA3 VCC MWEA VSS 123 124 125 126 127 128 A4 A5 A6 A7 A8 A9 87 88 89 90 AB0 AB1 AB2 AB3 129 130 131 132 A10 A11 A12 A13 O bs ol AA9 AA10 AA11 VCC VSS CASA0 Note: In order for the switching characteristics of this device to be guaranteed, it is necessary to connect all of the power pins (VCC, VSS) to the appropriate power levels. The use of low impedance wiring to the power pins is required. In systems using the i960 CA with its attendant high switching rates, multi-layer printed circuit boards with buried power and ground planes are required. 3 Pin Descriptions (Continued) be wired together. All 3-State outputs are to be weakly pulled up to VCC. In typical situations, a 10 kX resistor is sufficient. i960 CA/CF INTERFACE The following pins are functionally equivalent to those on the i960 CA/CF from which their names are taken. Like named pins on the i960 CA/CF and the NSBMC960 are to Pin Description Address Bus (Input): This system bus is a word address which determines the location at which an access is required. ADS Address Strobe (Input; Active Low): Indicates that a new access cycle is being started. D/*C Data/*Code (Input): Signals whether an access is for data or instructions. BLAST Burst Last (Input; Active Low): Indicates that the last cycle of a burst is in progress. DEN Data Enable (Input; Active Low): This input is monitored by the Bus Watch Timer to detect a bus access not returning READY. BTERM Burst Terminate (Output; 3-State; Active Low): This output is used to request termination of a burst in progress. Used to disable burst writes. READY Data Ready (Output; 3-State; Active Low): The READY output is used to signal that data on the processor bus is valid for Read, or that data has been accepted for Write. RESET Reset (Input; Active Low): Assertion of this input sets the NSBMC960 to its initial state. Following initialization, the NSBMC960 must be configured before any memory access is possible. BE0 – 3 Byte Enable (Input; Active Low): These inputs are used to determine which byte(s) within the addressed word are to be accessed. W/*R WRITE/*READ (Input): This input indicates the direction which data is to be transferred to/from on the data bus. SUP Supervisor (Input; Active Low): Indicates that the processor is operating in supervisor mode. Required for access to configuration registers. PCLK System Clock (Input): Processor output clock required to operate and synchronize NSBMC960 internal functions. BERR Bus Error (Output; Active Low): When enabled, this signal is generated by the Bus Watch Circuit to prevent processor lock-up on access to a region that is not responding. INT Interrupt (Output; 12 mA; Active Low): This signal is assented when the 24-bit counter reaches terminal count and interrupt out is enabled. May be programmed for pulse or handshake operation. ID0 – 2 Chip ID (Input): These inputs select the address offset of the NSBMC960 configuration registers. Each NSBMC960 in a system must have a unique address for proper operation. O bs ol et e A2 – 31 4 Pin Descriptions (Continued) drivers in order to minimize propagation delay due to input impedance and trace capacitance. External array drivers are not required. The address and control signals, however, should be externally terminated. MEMORY INTERFACE The NSBMC960 is designed to drive a memory array organized as 2 leaves each of 32 bits. The address and control signals for the memory array are output through high current Pin Description Multiplexed Address Bus (Output; 24 mA): These two buses transfer the multiplexed row and column addresses to the memory array leaves A and B. When non-interleaved operation is selected, only address bus A should be used. RAS(A,B)0–3 Row Address Strobes (Output; 12 mA Active Low): These strobes indicate the presence of a valid row address on busses A(A,B)0–11. These signals are to be connected one to each leaf of memory. Four banks of interleaved memory may be attached to a NSBMC960. CAS(A,B)0–3 Column Address Strobe (Output; 12 mA, Active Low): These strobes latch a column address from A(A,B)0 – 11. They are assigned one to each byte in a leaf. MWE(A,B) Memory Write Enable (Output; 24 mA, Active Low): These are the DRAM write strobes. One is supplied for each leaf to minimize signal loading. REFRESH Refresh in progress (Output; 12 mA, Active Low): This output gives notice that a refresh cycle is to be executed. The timing leads refresh RAS by one cycle. e A(A,B)0 – 11 Multiple operating modes facilitate choice of buffer type, and simple bus buffers (‘‘245’’s), bus latches (‘‘543’’s) and bus registers (‘‘646’’s) are all supported. et BUFFER CONTROLS Buffer control signals are provided to simplify the control of the interface between the DRAM and i960 data busses. Pin Data Bus Latch Enable A and B (Output; Active Low): These outputs are mode independent, however, the timing of the signals change for different operational modes. They control transparent latches that hold data transmiffed during a write transaction. In modes 0 and 1, the latch controls follow the timing of CAS for each leaf, while in modes 2 and 3 the timing of LEA and LEB is shortened to (/2 clock. O LE(A,B) Data Bus Transmit A and B (Output; Active Low): These outputs are multi-function signals. The signal names, as they appear on the logic symbol, are the default signal names (Mode e 0). The purpose of these outputs is to control buffer output enables during data read transactions and, in effect, control the multiplexing of data from each memory leaf onto the i960 CA/CF data bus. bs ol TX(A,B) Description 5 Functional Description allowed. If interleaved mode is selected, burst access is zero-wait-state; if memory is non-interleaved, 1-wait-state burst access results. The NSBMC960 allows for flexibility in the control of data buffers to the memory array. Propagation delay is minimized by providing these controls directly, and design flexibility maximized by allowing the control strategy to be programmable. Buffers as diverse as 74FCT245, 74FCT543, 74FCT646, 74FCT853 and 74FCT861 may be used without additional glue logic. PRODUCT OVERVIEW bs ol et e The NSBMC960 couples the i960 CA/CF interface to DRAM access protocols, generates bus buffer and data multiplexor controls and incorporates system and bus monitor timing resources. These functional elements are shown in Figure 1 . A maximum of 8 controllers may be included in a system, each managing up to 4 banks of memory. The NSBMC960 directly drives an array of fast page mode DRAMs. This array may be organized as 1 or 2 leaves of 32 bits each. Standard memory sizes from 256 kbit to 64 Mbit are supported and 8-, 16-, and 32-bit access are TL/V/11805 – 4 FIGURE 1. Functional Block Diagram ed by the contents of the byte data field. Bits [1,0] are reserved and must be ‘‘0’’. The base address is fixed at 0xff0f0000 while the BMC select field must match the value programmed at the ID[2..0] pins. In order to protect against accidental programming, the configuration registers can only be modified when the processor is in supervisor mode. O CONFIGURATION AND CONTROL The NSBMC960 contains 64 bits of configuration data that controls it’s operational mode. The configuration is programmed by sending data on the address bus. Figure 2 shows the format of a configuration access. The byte select field determines which byte of the 64-bit field will be updat- TL/V/11805 – 5 FIGURE 2. Address Bus Fields Used to Access Configuration Data 6 Functional Description (Continued) control bits. The block address, however, is constrained to start on a boundary that is an integer multiple of the block size. For example, if 1 Mbit c 1 DRAMs are used, the memory block size is 8 Mbytes and must start on an 8 Mbyte boundary. BLOCK ADDRESS FIELD et e Once configured, a NSBMC096 responds to access requests within the programmed block address range. The programmed value sets the starting address of the block, while the size of the block is determined by the DRAM size TL/V/11805 – 6 bs ol FIGURE 3. Configuration Register Control Fields violations during burst writes. If burst writes are disabled, latching buffers are no longer required. ROW ADDRESS HOLD Bit 18 of the configuration register controls the time at which the memory address switches from row to column address. This allows the designer to control the address hold time relative to RAS so that the slowest memory can be used for a range of clock speeds. Setting Bit 18 yields the maximum row address hold time, clearing it shortens the row address hold in favor of additional column address setup. INTERLEAVE DISABLE In cost sensitive applications, it is sometimes desirable for a system to operate with a single bank of memory so as to reduce the minimum memory required. In this case the interleave mode bit is programmed to ‘‘1’’. If a second bank of memory is added, this bit can be programmed to ‘‘0’’ to enable interleave operation and peak performance. In noninterleave mode a burst access is either 2-1-1-1 with Cycle Extend disabled, or 3-2-2-2 with Extended Cycle. Non-interleave operation uses only leaf A signals. O CYCLE EXTEND In order to maximize the choice of memory device speeds that may be used for various system clock rates, the Row Address Strobe (RAS) period for a basic access may be programmed for either 3 or 4 clock cycles. When cleared to ‘‘0’’, configuration bit 20 indicates that 3 clock cycles (2 wait states) are to be used (2-0-0-0 burst access), when set to ‘‘1’’, 4 are required (3 wait states for a basic access 3-0-1-0 for burst). Setting bit 20 to ‘‘1’’ also has the effect of increasing the RAS pre-charge time by 1 clock cycle. Calculation of the number of cycles required per access type is detailed in the NSBMC096 Application Guide. BURST WRITE DISABLE It bit 19 of the configuration word is set to ‘‘1’’, burst write cycles are disabled. Subsequently, when the NSBMC096 detects the start of a burst write access, it asserts the BTERM signal to request that the processor terminate the burst in progress and transfer the remaining data using a series of simple cycles. This feature is included in order to facilitate the implementation of systems without latching buffers. Latching buffers are required to prevent data hold 7 Functional Description (Continued) TABLE IV. Size Code Settings, DRAM Density and Address Range Size BUFFER CONTROL MODE FIELD The transfer of Data from the memory sub-system to the i960 bus occurs through buffers controlled by the NSBMC096. Two of the signals (LEA, LEB) provide transparent latch controls for use during write cycles. LEA and LEB have variable timing but fixed interpretation. The other two signals, TXA and TXB, change in both timing and function according to programmed mode. Table II presents these signals using names that are based on the function performed. Signals containing TX are transmit controls for buffers that have output enables (transmit from the memory system). Buffers such as ’245s or ’646s, which have direction and enable pins, are controlled by CE (chip enable) in modes 1 and 3. Signals ending with A or B are specific to one or the other of the two leaves of memory controlled by the NSBMC096. Signals without suffixes apply to both leaves. The signal LeafB/*A, required in some configurations, indicates which memory leaf will be selected on the next clock cycle. TABLE II. Interpretation of the Buffer Control Signals for Various Control Modes Signal 2 TXA CEA TX CE TXB CEB LeafB/*A LeafB/*A Memory Types 000 001 010 011 2 MB 8 MB 32 MB 128 MB 1 1 1 1 256k x 1 1 MB x 1 4 MB x 1 16 MB x 1 100 101 110 111 2 MB 8 MB 32 MB 128 MB 4* 4* 4* 4* 64k x 4 256k x 4 1 MB x 4 4 MB x 4 *Note that banks are sequentially addressed within a block. REFRESH RATE FIELD The system clock frequency is used to derive the period of DRAM refresh cycles. The refresh rate is calculated as (PCLK clock frequency) / (16 x (programmed value a 1)). If, for example, the system clock is 25 MHz and the programmed value is 24 (0x18), the NSBMC096 will execute the 256 refresh cycles for a 256k DRAM in 4.096 ms. The algorithm employed by the NSBMC096 guarantees the time for complete device refresh, however, individual row refresh may be delayed so as not to pre-empt bursts in progress. Since the maximum burst is 6 clock cycles in length, this delay in no way endangers data integrity. Access to devices other than NSBMC096 controlled memory are not delayed by refresh, access to memory while refresh is in progress are completed once the refresh cycle is complete. TIMER CONTROL FIELD The 24-bit timer is a counter which scales PCLK by a programmable amount and automatically reloads when terminal count is reached. The contents of the timer cannot be read directly, however, the counter will generate an interrupt when terminal count is reached. The timer is disabled following a RESET and the Timer Reload value (Configuration Bytes 4 – 6) must be programmed before the timer is enabled. The terminal count interrupt can be generated to comply with either edge triggered or level sense interrupt controllers. Edge triggered mode generates a pulse that is low for two cycles when terminal count is reached. In Level sense mode, the output is asserted low when terminal count is reached and the output remains low until the Acknowledge Timer Interrupt op-code is written to configuration byte 0. See the section on Operation Control for further detail concerning timer interrupt control. BUS WATCH TIMER CONTROL FIELD The NSBMC096 contains circuitry that monitors all bus access requests regardless of the target address. Access made to a region configured for external ready can hang the processor if for some reason READY is not returned to terminate the access. The NSBMC096 can detect such a condition and if the bus watch feature is enabled, will return READY and BERR. bs ol Table III presents some of the possible configurations with the corresponding mode settings. For a comprehensive discussion of the selection of a buffer strategy, refer to the NSBMC096 Application Guide. TABLE III. Possible NSBMC096 Memory/Buffer Configurations Max Banks e Signal 1 0 1 2 3 Memory Block Size et Mode Memory Size Code Buffer Type DRAM Type Write Access Read Access Buffer Mode 74FCT245 74FCT245 74FCT646 74FCT543 Am29C983 None Nibble Bit Nibble Bit Bit Nibble 2-4-4-4* 2-4-4-4* 1-0-0-0 1-0-0-0 1-0-0-0 2-4-4-4* 2-0-0-0 2-0-0-0 2-0-0-0 2-0-0-0 2-0-0-0 2-0-0-0 Mode 3 Mode 1 Mode 3 Mode 0 Mode 2 Mode 2, 3 *These configurations have burst writes disabled. O DRAM SIZE FIELD This three bit field, bits 12–14, selects the DRAM device address size, and consequently, memory block size. Note that the memory in both leaves of a bank are required to be of the same size and organization for correct operation. Table IV lists the size codes and the corresponding device sizes. 8 Functional Description (Continued) must be zero for proper in-circuit operation. The second field is the operation control field which is used to control the state of the page cache, timer, interrupts and bus error signal. The third field is the Iow two bits of the refresh rate. The NSBMC096 has been designed such that if any of the bits in the operation control field is written with a ‘‘1’’, access to the other two fields is disabled and the previous value is retained. If all bits in the operation control field are ‘‘0’’, the reserved and refresh rate fields are updated from the current input. Since the control register is accessed as a byte, automatic masking of the non-control field bits simplifies programming of the control parameters. AII parameters in this field may be modified on-the-fly, and all functions are disabled by reset. The operational controls have been encoded such that any access to the register will only modify one parameter. The bus monitor operates by monitoring the state of the DEN signal. Should it be asserted for longer than the programmed Bus Time Out value in configuration register 7, Ready is asserted if configuration bit 63 is set. If configuration bit 62 is set, BERR is also asserted. The BERR signal behaves much like the timer interrupt in that it can be programmed to produce a pulse or a level state. If level state operation is selected, (configuration bit 61 e 1), BERR will only be deasserted when configuration register 7 is accessed in a read cycle. If configuration bit 61 is cleared to zero, a two cycle pulse is produced on time-out. By providing both modes of operation, the BERR signal may be connected directly to the processor, or to an external WATCHDOGTM circuit. OPERATION CONTROL FIELD Byte 0 of the configuration register contains three fields. The first field (from LSB) is reserved for test purposes and 5 4 3 2 1 0 D X D X 0 0 0 1 0 0 0 0 D X D X X X X X X X X X X X 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 0 X X X X X X X X X X X X X X 1 1 1 1 0 1 0 0 X X X X Control Function Update Bits 0, 1, 6 and 7 with data D Instruction Access Page Cache Disable (Default) Instruction Access Page Cache Enable Data Access Page Cache Disable (Default) Data Access Page Cache Enable Acknowledge Timer Interrupt Enable Timer Output for Level Sense Interrupt Disable All Timer Interrupts Enable Timer Output for Edge Sense Interrupt bs ol et 6 e Bit 7 on the behavior of the program being executed as related to the ‘‘run-length’’ of data and instruction access, the processor internal cache utilization, and the locality of data and instruction references. Since throughput is lowered by cache misses, the page cache can be dynamically enabled/ disabled for instruction and/or data access. In this manner the programmer can apply the mechanism judiciously in order to maximize throughput. For systems in which Instruction and data spaces are controlled by independent NSBMC096s, the page cache management can be used to greater effect as data and instruction ‘‘run length’’ ceases to be a factor in determining performance. In this type of configuration cache efficiency is simply a function of locality of reference and a control strategy for the page cache mechanism is much simpler to derive and implement. PCache management is independently controlled for instruction and data access. A recommended starting strategy for improving performance of mixed instruction/data systems is to rely on the burst mechanism and the internal cache for instruction fetching, and enable PCache for Data access only. This general rule of thumb can be improved on, once program behavior is benchmarked. O PAGE CACHE MANAGEMENT The Page Cache management implemented by the NSBMC096 incorporates a mechanism whereby advantage can be taken of the page access mode of DRAMs, not only for burst access, but also for non-sequential data and instruction access. The mechanism relies on the fact that as long as RAS is asserted, access to the selected row can be gained by simply asserting a column address and the CAS strobe. The resulting access is slower than a burst only by the amount of time required to ensure that the desired address is in the same row as was previously selected. The benefits of this type of access are obvious, however, there can be drawbacks. If the required address does not reside in the same page as that selected, the currently selected row must be released and the new row selected before the access can proceed. The process of de-selecting a row and selecting a new one requires that the RAS precharge time be allowed to expire before the selection of a new row can begin. This pre-charge time can require up to two additional cycles over a standard access startup. The efficiency of this type of cache (PCache) is related to a large extent on the locality of reference of the datum being accessed. For systems that have mixed Instruction and Data memory systems, PCache efficiency is very dependent 9 Application Example Cycle Extend: System Clock: 25 MHz Refresh Rate: 16 ms per row (0 c 18) Memory Size: 1 MB x 1 (Size e 1) Signal 1 e CEA, Signal 2 e CEB (Mode 1) Interleave: Enabled Row Address Hold: (/2 clock cycle (Row Address Hold e 0) Buffer Mode: Burst Write: Base Address: Disabled (3 clock RAS derived from tRSHL of NSBMC096, RAS access time of DRAM, buffer delay of 74FCT245 and setup time of the processor’s data inputs) Disabled 8 MB (0b000000000100) Required Configuration for startup 0000 0000 1000 1000 1001 0110 0000 0000 (0x00889600) Configuration Setup 0xFF0F0000 (0xFF0F0000, 0); /* Config. bits 7..0 e 0 */ 0xFF0F0658 (0xFF0F0400 a (0x96 m 2), 0); /* Config. bits 15..8 e 0 */ 0xFF0F0A20 (0xFF0F0800 a (0x88 m 2), 0); /* Config. bits 23..16 e 0 */ 0xFF0F0C00 (0xFF0F0C00, 0); /* Config. bits 31..24 e 0 */ et e ate inputs of the processor and require only a small pull up resistor to keep them de-asserted when in the high impedance state. If multiple processor peripherals are connected to READY or BTERM, 3-state drivers should be used in such a manner that the signals are actively de-asserted prior to the driver being placed in its’ high impedance state. If this rule is followed, a simple ‘‘wire or’’ can be used. Alternately, all sources of READY or BTERM can be combined using multiple input gates and the processor signals driven by the outputs. O bs ol The ease with which the NSBMC096 may be integrated into a system design is illustrated in the diagram in Figure 4 . The system shown supports an i960 CA/CF with between 2 and 128 MB of memory, depending on the devices selected, managed by a single NSBMC096. This specific example accommodates 1 MB x 1, 4 MB x 1 or 16 MB x 1 devices. Connection of the NSBMC096 to the i960 CA/CF processor is accomplished simply by wiring together pins with the same names. The only exceptions are READY and BTERM. If the NSBMC096 is the only device that generates these two signals, they can be connected directly to the appropri- FIGURE 4. Possible System Interconnection using V96BMC (Mode 1 where TXA is used as CEA and TXB as CEB) 10 TL/V/11805 – 7 Timing Parameters depending on whether Cycle Extend is enabled. If multiple access cycles are requested back to back then the BMC will pause for a minimum of 2 clocks between RAS cycles to insure that the RAS pre-charge time is met. This will result in 5 or 6 clocks between successive simple cycles. INTERFACE TIMING The NSBMC096 interface to the i960 CA/CF has been designed for direct interconnect. It is not necessary to place other Iogic devices between the processor and the NSBMC096, nor is their use encouraged. The introduction of intermediate address or control signal buffers can result in skews or delays that will require the system clock frequency to be derated for operation under worst case conditions. The timing diagrams presented in this section assume that all signals between the processor and the NSBMC096 are un-buffered. Figure 6 shows the timing relationship between the system clock, processor control signals and NSBMC096 outputs. AIl NSBMC096 outputs are derived synchronously with the exception of tARA (processor address to row address delay). Two simple access cycles are shown in the diagram. The first is a read cycle that assumes that the NSBMC096 was idle prior to the start of the cycle, the second is backed onto the first to show the effect of RAS pre-charge imposed by NSBMC096. If Cycle Extend is enabled, a wait state will be inserted after cycles T3 and T8. REFRESH TIMING Figure 5 details the timing of the RAS only refresh performed by the memory controller when there is a competing request from a bus master. A competing request is defined as any request that occurs between T0 and T5. For any request in this range, the timing is exactly as shown. As illustrated, the diagram represents the timing that results when Cycle Extend is disabled. If Cycle Extend is enabled, an additional cycle is inserted at T3 and T8. e BURST ACCESS TIMING When a burst access is requested by the processor, the NSBMC096 generates the sequence in Figure 7. If the burst is for 2 words (load double for example), the processor generates *BLAST in T5 and the sequence is shortened appropriately. The first access of the burst sequence begins in the same manner as a simple access. Consequently the timing parameters from Figure 6 may be applied in Figure 7 . O bs ol et SIMPLE ACCESS TIMING The NSBMC096 can return data to the processor in only 3 or 4 clock cycles for a basic access (2 or 3 wait states) TL/V/11805 – 8 FIGURE 5. Refresh Timing 11 et e Timing Parameters (Continued) TL/V/11805 – 9 O bs ol FIGURE 6. Basic Access Timing TL/V/11805 – 10 FIGURE 7. Burst Access Timing 12 et e Timing Parameters (Continued) TL/V/11805 – 11 bs ol FIGURE 8. Burst Access w/t PCache Hit with DRAM. Figure 9 shows the worst case scenario. This example shows two back-to-back simple access to different rows with PCache is enabled. O Figures 8 and 9 show the sequence of events that can occur when PCache is enabled. The sequence in Figure 8 shows two back-to-back bursts in the same page. This type of sequence yields the highest data transfer rate achievable TL/V/11805 – 12 FIGURE 9. Simple Access w/t PCache Miss 13 Absolute Maximum Ratings Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage (VIN) D.C. Input Current (IIN) Storage Temperature ( O STG) All Voltages References to Ground Supply Voltage (VCC) Ambient Temperature Range ( O A) Plastic Package Ceramic Package b 0.3V to a 7V b 0.3V to VCC a 0.3V g 50 mA 4.5V to 5.5V b 0§ C to a 70§ C b 55§ C to a 85§ C b 65§ C to a 150§ C DC Electrical Characteristics Description Conditions VCC e 4.75V VIH High Level Input Voltage VCC e 5.25V IIL Low Level Input Current VIN e VSS, VCC e 5.25V IIH High Level Input Current VIN e VCC e 5.25V VOL Low Level Output Voltage VIN e VIL or VIH IOL e 24 mA VOH High Level Output Voltage VIN e VIL or VIH IOL e 24 mA IOZL Low Level TRI-STATEÉ Output Current VIN e VIL or VIH VO e VSS IOZH Low Level TRI-STATE Output Current VIN e VIL or VIH VO e 5.25V ICC(Max) Maximum Supply Current Continuous Burst Access Continuous Simple Access Units 1.4 V V b 10 mA 10 mA 0.4 3.7 V V b 20 mA 20 mA 100 30 mA Input Capacitance 20 pF Output Capacitance 20 pF O COUT Max 3.7 bs ol CIN Min et Low Level Input Voltage e Symbol VIL 14 AC Timing Parameters (Unless otherwise stated VCC e 5.0V g 5%, 0§ C k TA k 70§ C.) Symbol 16 MHz Description Min Max 1. tADSU Address Strobe Setup Time 2. tADH Address Strobe Hold Time 14 3. tSU Synchronous Input Setup 4. tH Synchronous Input Hold 5. tBLSU BLAST Input Setup 6. tBLH BLAST Input Hold 3 7. tRZH READY 3-state to Valid Delay Relative to *PCLK 8. tRHL 9. tRLH 10. 25 MHz Min Max 12 3 14 33 MHz Min 9 3 12 3 Units Max ns 3 9 ns 3 ns 3 3 ns 29 24 19 ns READY Synchronous Assertion Delay 26 21 17 ns READY Synchronous De-assertion Delay 25 20 16 ns tRHZ READY Valid to 3-state Delay Relative to *PCLK 27 22 17 ns 11. tARA Address Input to Row Address Output Delay (Note 1) 23 19 15 ns 12. tRAH *PCLK or PCLK to Row Address Hold 13. tCAV *PCLK or PCLK to Column Address Valid (Note 1) 14. tCAH PCLK to Column Address Hold 15. tDRAH DRAM Row Address Hold (Note 2) 16. tRSHL PCLK to RAS Asserted Delay (Note 1) 29 24 19 ns 17. tRSLH PCLK to RAS De-asserted Delay (Note 1) 26 21 17 ns 18. tCHL PCLK to CAS Asserted Delay (Note 1) 23 19 15 ns 19. tCLH PCLK to CAS De-asserted Delay (Note 1) 20 16 13 ns 20. tBHL PCLK to Buffer Control Asserted Delay (Note 1) 17 ns 21. tBLH PCLK to Buffer Control De-asserted Delay (Note 1) 22. tBSV PCLK to Bank Select Valid Time (Note 1) 23. tBSH PCLK to Bank Select Hold Time (Note 1) 24. tWEHL *PCLK to Write Enable Asserted Delay (Note 1) 25. tWELH PCLK to Write Enable De-asserted Delay (Note 1) 26. tBCAH *PCLK to Column Address Hold Time (Burst) (Note 1) 27. tBCAV *PCLK to Column Address Valid Delay (Burst) (Note 1) 29 23 19 ns 28. tLEHL *PCLK to Latch Enable Assertion 23 19 15 ns 29. tLELH PCLK to Latch Enable De-assertion 20 16 13 ns 30. tRFA PCLK to Row Address Valid (Refresh) 38 31 25 31. tRFH PCLK to Row Address Hold (Refresh) 32. tRFHL REFRESH Synchronous Assertion Delay 20 16 13 ns 33. tRFLH REFRESH Synchronous De-assertion Delay 20 16 13 ns 12 9 40 33 26 38 31 25 4 4 et 4 tM-4 bs ol tM-4 26 4 23 4 26 4 tM-3 21 19 5 4 21 4 31 ns ns ns ns 15 ns 17 ns 20 ns 4 25 ns ns 5 5 O ns e 14 3 ns 4 5 ns 4 ns ns *Signal output delays are measured relative to PCLK (except as indicated) using a 50 pF load. Note 1: Derate the given delays by 0.006 ns per pF of load in excess of 50 pF. Note 2: tM e PCLK High duration when configuration bit 18 e 0. tM e PCLK cycle time e 1/(PCLK frequency) for configuration bit 18 e 1. Timing for Rev AB silicon. 15 Errata for NSBMC096 The document defines all known errata related to the operation of the NSBMC096 Memory Controller. ERRATUM Ý2 When the NSBMC096 is programmed for extended timing mode operation, back to back memory read cycles will fail. ERRATUM Ý1 Pulse mode interrupts from the NSBMC096 are two cycles long. The current rev. of the i960CA/CF requires a minimum interrupt pulse width of three clock cycles. RECOMMENDED FIX Program the i960CA/CF memory region for the NSBMC096 to insert one wait state following each memory access (i.e., Set NXDA e 1). RECOMMENDED FIX Program the NSBMC096 for level mode interrupts. Ordering Code Information NS BMC 096 National Semiconductor VF 33 Frequency 16 MHz 25 MHz 33 MHz Packaging VF 132-Lead PQFP O bs ol et e Mode Burst Mode Controller Processor Intel i960 16 17 e et bs ol O e et bs ol NSBMC096-16/-25/-33 Burst Memory Controller Physical Dimensions inches (millimeters) 132-Pin Plastic Quad Flatpak (PQFP) Order Number NSBMC096VF NS Package Number VF132A LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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