ETC PLX9060

PCI 9060
December, 1995
PCI Bus Master Interface Chip for
VERSION 1.2
Adapters and Embedded Systems
________________________________________________________________________________
Features
•
•
•
•
•
•
•
•
General Description _______________
PCI Bus Master Interface supporting adapters and
embedded systems
Two independent DMA channels for local bus
memory to/from PCI host bus data transfers
Four bi-directional FIFOs for zero wait-state burst
operation; one for each DMA channel, one for Direct
Master interface and one for slave interface
PCI Bus Master transfers up to 132 MBytes/sec
Supports both multiplexed and non-multiplexed local
buses, 32, 16 or 8 bit. May connect directly to Intel
i960Cx, Hx, Jx, Kx and Sx processors
Local bus can run asynchronously to the PCI clock.
Eight 32 bit mailbox and two 32 bit doorbell registers
Low power CMOS in 208 Pin Plastic QFP Package
The PCI9060 provides a compact high performance PCI
bus master interface for adapter boards and embedded
systems. The chip’s local bus follows the protocol of the
Intel i960 microprocessor family.
The PCI9060 provides two independent bi-directional
DMA channels with bi-directional FIFOs supporting zero
wait-state burst transfers between host and local
memory. Each channel also supports full data chaining
modes which allows concurrent operations. The chip
also contains a bi-directional FIFO for efficient slave
access. In addition, another bi-directional FIFO ensures
high speed Direct Bus Master transfers.
The PCI9060 also allows the local processor and other
intelligent controllers to perform direct bus master
transfers on the PCI bus. As an option, the PCI9060 can
enable the local processor to configure other PCI devices
in the system.
________________________________________________________________________________
Figure 1. Typical Adapter or Embedded System Block Diagram
________________________________________________________________________________
 PLX Technology, Inc., 1995
PLX Technology, Inc., 625 Clyde Avenue, Mountain View, CA 94043 (415) 960-0448 FAX (415) 960-0479
Products and Company names are trademarks/registered trademarks of their respective holders
TABLE OF CONTENTS
________________________________________________________________________________
TABLE OF CONTENTS
1. SECTION 1 - PCI 9060 GENERAL DESCRIPTION ..................................................................................................... 6
2. SECTION 2 - BUS OPERATION ................................................................................................................................. 7
2.1 PCI BUS CYCLES...................................................................................................................................................... 7
2.1.1 PCI Target Command Codes ............................................................................................................................... 7
2.1.2 PCI Master Command Codes............................................................................................................................... 7
2.1.2.1 DMA Master Command Codes........................................................................................................................................ 7
2.1.2.2 Direct Local to PCI Command Codes.............................................................................................................................. 7
2.2 LOCAL BUS CYCLES ................................................................................................................................................ 8
2.2.1 Local Bus Slave................................................................................................................................................... 8
2.2.2 Local Bus Master ................................................................................................................................................. 8
2.2.2.1 Ready/Wait State Control ............................................................................................................................................... 8
2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM “Burst Terminate” mode) .................................................................... 8
2.2.2.3 Recovery States ............................................................................................................................................................ 8
2.2.2.4 Local Bus Read Accesses............................................................................................................................................... 9
2.2.2.5 Local Bus Write Accesses............................................................................................................................................... 9
2.2.2.6 Direct Slave Write Access to 8 and 16 bit bus ................................................................................................................. 9
2.2.2.7 Local Bus Data Parity ..................................................................................................................................................... 9
3. SECTION 3 - FUNCTIONAL DESCRIPTION............................................................................................................. 10
3.1 PCI 9060 INITIALIZATION ............................................................................................................................................ 10
3.2 RESET..................................................................................................................................................................... 10
3.2.1 PCI Bus Input RST#........................................................................................................................................... 10
3.2.2 Local Bus Input LRESETi#................................................................................................................................. 10
3.2.3 Local Bus Output LRESETo#............................................................................................................................. 10
3.2.4 Software Reset .................................................................................................................................................. 10
3.3 EEPROM ................................................................................................................................................................. 11
3.4 INTERNAL REGISTER ACCESS....................................................................................................................................... 13
3.4.1 PCI Bus Access to Internal Registers ................................................................................................................. 13
3.4.2 Local Bus Access to Internal Registers............................................................................................................... 14
3.5 DIRECT DATA TRANSFER MODES ................................................................................................................................. 15
3.5.1 Direct Bus Master Operation (Local Master to PCI Bus Access) ......................................................................... 15
3.5.2 Direct Slave Operation (PCI Master to Local Bus Access)................................................................................. 18
3.5.2.1 PCI to Local Address Mapping...................................................................................................................................... 18
3.5.2.2 Deadlock and BREQo ................................................................................................................................................... 20
3.5.3 Direct Slave Priority ........................................................................................................................................... 21
3.6 DMA OPERATION ....................................................................................................................................................... 22
3.6.1 Non-Chaining Mode DMA .................................................................................................................................. 22
3.6.2 Chaining Mode DMA.......................................................................................................................................... 23
3.6.3 DMA Data Transfers .......................................................................................................................................... 24
3.6.3.1 Local to PCI Bus DMA Transfer .................................................................................................................................... 24
3.6.3.2 PCI to Local Bus DMA Transfer .................................................................................................................................... 25
3.6.3.3 Unaligned Transfers...................................................................................................................................................... 26
3.6.4 Demand Mode DMA .......................................................................................................................................... 26
3.6.5 DMA Priority ...................................................................................................................................................... 26
3.6.6 DMA Arbitration ................................................................................................................................................. 26
3.6.6.1 Local Latency and Pause Timers .................................................................................................................................. 26
3.7 BREQ INPUT. ............................................................................................................................................................ 26
3.8 DOORBELL REGISTERS ................................................................................................................................................ 26
3.9 MAILBOX REGISTERS .................................................................................................................................................. 27
3.10 INTERRUPTS............................................................................................................................................................. 27
3.10.1 PCI Interrupts (INTA#) ..................................................................................................................................... 27
3.10.1.1 Doorbell Interrupt ........................................................................................................................................................ 27
3.10.1.2 Local Interrupt Input.................................................................................................................................................... 27
________________________________________________________________________________
Page - 2 Version 1.2
Section B
PCI9060
TABLE OF CONTENTS
________________________________________________________________________________
3.10.1.3 Master/Target Abort Interrupt ...................................................................................................................................... 27
3.10.2 Local Interrupts (LINTo#) ................................................................................................................................. 28
3.10.2.1 Doorbell Interrupt ........................................................................................................................................................ 28
3.10.2.2 Built In Self Test Interrupt (BIST) ................................................................................................................................ 28
3.10.2.3 DMA Channel 0/Channel 1 Interrupts .......................................................................................................................... 28
3.10.3 PCI SERR# (PCI NMI) .................................................................................................................................... 28
3.10.4 Local LSERR# (Local NMI) ............................................................................................................................ 29
4. SECTION 4 - REGISTERS ....................................................................................................................................... 30
4.1 REGISTER ADDRESS MAPPING ..................................................................................................................................... 30
4.2 PCI CONFIGURATION REGISTERS................................................................................................................................. 32
4.2.1 PCI Configuration ID Register (Offset 00h) ........................................................................................................ 33
4.2.2 PCI Command Register (Offset 04h).................................................................................................................. 33
4.2.3 PCI Status Register (Offset 06h)........................................................................................................................ 34
4.2.4 PCI Revision ID Register (Offset 08h)................................................................................................................ 34
4.2.5 PCI Class Code Register (Offset 09 - 0Bh) ........................................................................................................ 35
4.2.6 PCI Cache Line Size Register (Offset 0Ch)........................................................................................................ 35
4.2.7 PCI Latency Timer Register (Offset 0Dh)........................................................................................................... 35
4.2.8 PCI Header Type Register (Offset 0Eh) ............................................................................................................. 35
4.2.9 PCI Built-In Self Test (BIST) Register (PCI Offset 0Fh)...................................................................................... 36
4.2.10 PCI Base Address Register for Memory Access to Runtime Registers (Offset 10h).......................................... 36
4.2.11 PCI Base Address Register for I/O Access to Runtime Registers(Offset 14h)................................................... 37
4.2.12 PCI Base Address Register for Memory Access to Local Address Space 0 (Offset 18h)................................... 37
4.2.13 PCI Base Address Register (Offset 1Ch).......................................................................................................... 37
4.2.14 PCI Base Address Register (Offset 20h) .......................................................................................................... 38
4.2.15 PCI Base Address Register (Offset 24h) .......................................................................................................... 38
4.2.16 PCI Base Address Register (Offset 28h) .......................................................................................................... 38
4.2.17 PCI Base Address Register (Offset 2Ch).......................................................................................................... 38
4.2.18 PCI Expansion ROM Base Register (Offset 30h).............................................................................................. 39
4.2.19 PCI Interrupt Line Register (Offset 3Ch)........................................................................................................... 39
4.2.20 PCI Interrupt Pin Register (Offset 3Dh) ............................................................................................................ 39
4.2.21 PCI Min_Gnt Register (Offset 3Eh) .................................................................................................................. 40
4.2.22 PCI Max_Lat Register (Offset 3Fh) .................................................................................................................. 40
4.3 LOCAL CONFIGURATION REGISTERS ............................................................................................................................. 41
4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h) ............................................ 41
4.3.2 Local Address Space 0 Local Base Address (Re-map) Register for PCI to Local Bus (PCI 04h) (LOC 84h)........ 41
4.3.3 Local Register (PCI 08h) (LOC 88h)................................................................................................................... 42
4.3.4 Local Register (PCI 0ch) (LOC 8ch) ................................................................................................................... 42
4.3.5 Local Expansion ROM Range Register for PCI to Local Bus (PCI 10h) (LOC 90h)............................................. 42
4.3.6 Local Expansion ROM Local Base Address (Re-map) register for PCI to Local Bus and BREQo Control (PCI
14h) (LOC 94h)........................................................................................................................................................... 42
4.3.7 Local Bus Region Descriptor for PCI to Local Accesses Register (PCI 18h) (LOC 98h) ...................................... 43
4.3.8 Local Range register for Direct Master to PCI (PCI 1Ch) (LOC 9Ch) .................................................................. 44
4.3.9 Local Bus Base Address register for Direct Master to PCI Memory (PCI 20h) (LOC A0h).................................. 44
4.3.10 Local Base Address for Direct Master to PCI IO/CFG Register (PCI 24h) (LOC A4h) ....................................... 44
4.3.11 PCI Base Address (Re-map) register for Direct Master to PCI (PCI 28h) (LOC A8h) ....................................... 45
4.3.12 PCI Configuration Address Register for Direct Master to PCI IO/CFG (PCI 2Ch) (LOC ACh) ........................... 45
4.4 SHARED RUNTIME REGISTERS ..................................................................................................................................... 46
4.4.1 Mailbox Register 0 (PCI 40h) (LOC C0h) ........................................................................................................... 46
4.4.2 Mailbox Register 1 (PCI 44h) (LOC C4h) ........................................................................................................... 46
4.4.3 Mailbox Register 2 (PCI 48h) (LOC C8h) ........................................................................................................... 46
4.4.4 Mailbox Register 3 (PCI 4Ch) (LOC CCh) .......................................................................................................... 46
4.4.5 Mailbox Register 4 (PCI 50h) (LOC D0h) ........................................................................................................... 47
4.4.6 Mailbox Register 5 (PCI 54h) (LOC D4h) ........................................................................................................... 47
4.4.7 Mailbox Register 6 (PCI 58h) (LOC D8h) ........................................................................................................... 47
4.4.8 Mailbox Register 7 (PCI 5Ch) (LOC DCh) .......................................................................................................... 47
________________________________________________________________________________
Page - 3 Version 1.2
Section B
PCI9060
TABLE OF CONTENTS
________________________________________________________________________________
4.4.9 PCI to Local Doorbell Register (PCI 60h) (LOC E0h) ......................................................................................... 48
4.4.10 Local to PCI Doorbell Register (PCI 64h) (LOC E4h)........................................................................................ 48
4.4.11 Interrupt Control/Status (PCI 68h) (LOC E8h) .................................................................................................. 49
4.4.12 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI 6Ch) (LOC ECh).......... 50
4.5 LOCAL DMA REGISTERS ............................................................................................................................................. 51
4.5.1 DMA Channel 0 Mode Register (LOC 100h)...................................................................................................... 51
4.5.2 DMA Channel 0 PCI Address Register (LOC 104h) ............................................................................................ 51
4.5.3 DMA Channel 0 Local Address Register (LOC 108h) ......................................................................................... 52
4.5.4 DMA Channel 0 Transfer Size (Bytes) Register (LOC 10Ch) ............................................................................. 52
4.5.5 DMA Channel 0 Descriptor Pointer Register (LOC 110h) ................................................................................... 52
4.5.6 DMA Channel 1 Mode Register (LOC 114h)....................................................................................................... 53
4.5.7 DMA Channel 1 PCI Data Address Register (LOC 118h).................................................................................... 53
4.5.8 DMA Channel 1 Local Data Address Register (LOC 11Ch)................................................................................. 54
4.5.9 DMA Channel 1 Transfer Size (Bytes) Register (LOC 120h)............................................................................... 54
4.5.10 DMA Channel 1 Descriptor Pointer Register (LOC 124h).................................................................................. 54
4.5.11 DMA Command/Status Register (LOC 128h) .................................................................................................. 55
4.5.12 DMA Arbitration Register 0 (LOC 12Ch)........................................................................................................... 55
4.5.13 DMA Arbitration Register 1 (LOC 130h) ........................................................................................................... 56
5. SECTION 5 - PIN DESCRIPTION.............................................................................................................................. 57
5.1 PIN SUMMARY ............................................................................................................................................................ 57
6. SECTION 6 - ELECTRICAL AND TIMING SPECIFICATIONS .................................................................................. 69
7. SECTION 7 - PACKAGE MECHANICAL DIMENSIONS ............................................................................................ 71
7.1 PACKAGE MECHANICAL DIMENSIONS............................................................................................................................. 72
7.2 TYPICAL PCI BUS MASTER ADAPTER............................................................................................................................ 73
7.3 I960CX MODE PIN OUT ........................................................................................................................................ 74
7.4 I960JX MODE PIN OUT ......................................................................................................................................... 75
7.5 I960SX MODE PIN OUT ........................................................................................................................................ 76
8. SECTION 8- TIMING DIAGRAMS ............................................................................................................................. 77
8.1 LIST OF TIMING DIAGRAMS ........................................................................................................................................... 77
REVISION HISTORY
Date
Revision
03/01/95
1.0
08/15/95
1.1
Comment
1. DEN# is an I/O pin in Jx mode. DEN# should be tied high if unused.
2. For PCI9060 Rev 2A parts or later, A PCI master can access the DMA registers by performing a Direct Slave
access to the local bus. The local address should be that of the desired DMA register.
3. Timing Diagram updates
Corrected typographical errors, Clarified specifications, and Updated Timing Diagrams.
________________________________________________________________________________
Page - 4 Version 1.2
Section B
PCI9060
TABLE OF CONTENTS
________________________________________________________________________________
12/12/95
A. Updates from Rev. 2 chip to Rev. 3 chip : In addition to correcting errata, PLX made changes to the PCI 9060
to improve performance, flexibility and ease of use. The Rev. 3 is also entirely pin and software compatible
with the Rev. 2.
1.2
1. Errata 1 through 13 from Rev. 2 chip were corrected.
2. Direct Slave Read FIFO = 8 Words (32 Bytes) vs. 4 in Rev. 2
Direct Slave Write FIFO = 8 Words (32 Bytes) vs. 4 in Rev. 2
The increase in FIFO depths requires no software or hardware changes. The only difference the user will
observe is an increase in Direct Slave throughput.
3. DMA registers may be accessed from PCI bus as well as local bus as described in Version 1.2 data sheet.
4. 0 ns hold time on all PCI signals.
5. Local pre-fetch can be disabled (PCI disconnect after 1 data read) Default state is pre-fetch enabled. To
disable address space 0 pre-fetch set bit 8, Table 29 to 1. To disable expansion ROM pre-fetch set bit 9,
Table 29 to 1.
6. Many users want to have an option of mapping the entire PCI address space to the local bus. To
accommodate this Rev. 3 acts as follows: If the PCI address space for Direct Master accesses overlaps the
128 byte space for the run time registers, an access to that 128 byte space will access the run-time registers.
No Direct Master access will occur in the run-time address space.
7. For the same reasons as in 6, if the PCI address space for Direct Slave accesses overlaps the space for the
run time registers, an access to that space will access the run-time registers. No Direct Slave access will
occur in the run-time address space.
8. LSERR# is driven high during reset (instead of driven low in Rev. 2), to avoid erroneous LSERR# assertion.
9. Most NC pins in Rev. 3 are driven and must not be connected. In the Rev. 2 chip, most of the NC pins are
floating.
10. In Rev. 2 BREQo was asserted if there was any data in the FIFO during a write and deadlock situation. In
Rev. 3, BREQo is asserted only if DM FIFO is full during a write and deadlock situation.
11. During Direct Slave reads, the 9060 gives up the local bus if BREQi is asserted or it’s internal local bus
latency timer expires. The individual data cycles still need to be completed.
12. The 9060 keeps the local bus until the entire Direct Slave write cycle is complete, not just when the write
FIFO is empty. The 9060 still gives up the local bus if BREQi is asserted or it’s internal local bus latency
timer expires.
B. Revised Local Bus Maximum Setup and Hold times. Refer to Section 6 for complete AC/DC Electrical
Characteristics.
Local Bus Maximum setup and hold time comparison(Version 1.1 vs. 1.2 data sheet).
Signal
ADS#
LAD
LD
RDYi#
BLAST#
LDP
BTERM#
BREQ
HOLDA
DREQ#
Version 1.1
setup time
4
4
4
4
4
4
4
4
4
4
Version 1.1
hold time
3
3
3
3
3
3
3
3
3
3
Version 1.2
setup time
9
3
7
9
6
4
5
N.A.
5
6
Version 1.2
hold time
1
N.A.
1
1
1
1
1
1
1
1
Local Bus Maximum TVALID (Version 1.1 vs. 1.2 data sheet)
Signal
USERo
BREQo
DACK[1:0]#
Version 1.1 TVALID
(MAX) NSEC
Version 1.2 TVALID
(MAX) NSEC
(WORST CASE)
(WORST CASE)
13
18
18
21
21
20
________________________________________________________________________________
Page - 5 Version 1.2
Section B
PCI9060
SECTION 1
GENERAL DESCRIPTION
________________________________________________________________________________
1. SECTION 1 - PCI 9060 GENERAL DESCRIPTION
The PCI9060 is a PCI bus master interface chip that connects a PCI host bus to three local bus types, selected through
mode pins. Each local bus configuration matches the protocol of an Intel 80960 processor, but the PCI 9060 may be
connected to any local bus with a similar design.
Mode
Description
80960 processor
Cx
Jx
Sx
32 bit address / 32 bit data, non-multiplexed
32 bit address / 32 bit data, multiplexed
32 bit address / 16 bit data, multiplexed
Cx, Hx
Jx, Kx
Sx
The PCI9060 bus interface chip offers substantial performance advantages over slave adapters or other bus master
adapters that rely on the local or host processor to transfer large amounts of data to and from the adapter. The PCI9060
provides two independent bi-directional DMA channels each with FIFOs for maximum burst transfers in and out of the
adapter. This feature significantly improves overall performance by greatly reducing local or host processor involvement
with actual data transfers. The FIFOs ensure that data is transferred at maximum bus efficiency and burst rates even when
the local bus is operating at a different (and potentially slower) speed than the PCI bus.
Using the PLX PCI9060 bus master chip also reduces total hardware and software development costs for disk controller,
communication adapter and embedded system designs. The PCI9060 provides a single chip interface solution that
minimizes board space requirements and ensures PCI hardware compatibility compliance. Because the PCI9060 can be
used for all intelligent subsystem designs, common driver and initialization software can be used, thus maximizing
development resources and increasing the quality of the design.
Major Features
Dual independent programmable DMA controllers with bi-directional FIFOs. The PCI9060 provides two independent
programmable DMA controllers with bi-directional FIFOs for each channel. Each channel supports both non-chaining and
chaining DMA modes.
Direct bus master. The PCI9060 supports the direct access of the PCI bus by either a local bus processor or an intelligent
controller. The PCI9060 supports PCI bus interlock ("LOCK#") cycles as well. Bi-directional FIFOs enable high-performance
bursting on the local and PCI bus.
Direct slave. The PCI9060 supports both memory mapped and I/O mapped burst accesses to the local bus from the PCI
bus. Bi-directional FIFOs enable high-performance bursting on the local and PCI bus.
PCI Host Capability. In direct master mode, the PCI9060 can generate type 0 and type 1 PCI configuration cycles.
Interrupt generator. The PCI9060 can generate PCI and local interrupts from several sources.
Clock. The PCI9060 local bus interface runs from a local TTL clock and generates the necessary internal clocks. This
clock can run asynchronously to the PCI clock.
Programmable local bus configurations. The PCI9060 supports: a 32 bit non-multiplexed bus (Cx mode), a 32 bit
multiplexed bus (Jx mode), and a 16 bit multiplexed (Sx mode). The PCI9060 operates in one of three modes, selected
through mode pins, corresponding to three bus types; Cx, Jx and Sx.
Bus drivers. All control, address, and data signals generated by the PCI9060 directly drive the PCI bus, without requiring
any external drivers.
Serial EEPROM interface. The PCI9060 contains an optional serial EEPROM interface that can be used to load
configuration information. This is useful for loading information which is unique to a particular adapter (e.g. Network ID,
Vendor ID, etc.).
Mailbox Registers. The PCI9060 contains eight 32 bit mailbox registers that may be accessed from either the PCI or the
local bus.
Doorbell Registers. The PCI9060 includes two 32 bit doorbell registers. One generates interrupts from the PCI bus to the
local bus. The other generates interrupts from the local bus to PCI bus.
Unaligned DMA Transfer Support. The PCI9060 can transfer data on any byte boundary.
_______________________________________________________________________________
Page - 6 Version 1.2
Section B
PCI9060
SECTION 2
BUS OPERATION
________________________________________________________________________________
2. SECTION 2 - BUS OPERATION
2.1 PCI BUS CYCLES
The PCI9060 is PCI Compliant.
2.1.1 PCI Target Command Codes
As a target, the PCI9060 allows access to the PCI9060 internal registers and the local bus using the following
commands;
Command Type
Code(C/BE[3:0]#)
I/O Read
0010 (2h)
I/O Write
0011 (3h)
Memory Read
0110 (6h)
Memory Write
0111 (7h)
Memory Read Multiple
1100 (Ch)
Memory Read Line
1110 (Eh)
Memory Write and Invalidate
1111 (Fh)
Configuration Read
1010 (Ah)
Configuration Write
1011 (Bh)
All read or write accesses to the PCI9060 can be byte, word or long word accesses. All memory commands are aliased to
the basic memory commands. All I/O accesses to the PCI9060 are decoded to a long word boundary. The byte enables
are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated
with a Target Abort.
2.1.2 PCI Master Command Codes
The PCI9060 can access the PCI bus to perform DMA transfers or Direct Local to PCI bus transfers.
2.1.2.1 DMA Master Command Codes
The PCI9060’s DMA controllers can generate the following memory cycles:
Command Type
Code(C/BE[3:0]#)
Memory Read
0110 (6h)
Memory Write
0111 (7h)
Memory Read Multiple
1100 (Ch)
Memory Read Line
1110 (Eh)
2.1.2.2 Direct Local to PCI Command Codes
For direct local to PCI bus accesses, the PCI9060 can generate the following cycles:
Local to PCI Memory Access
Command Type
Code(C/BE[3:0]#)
Memory Read
0110 (6h)
Memory Write
0111 (7h)
Memory Read Multiple
1100 (Ch)
Memory Read Line
1110 (Eh)
Local to PCI I/O Access
Command Type
Code(C/BE[3:0]#)
0010 (2h)
I/O Read
0011 (3h)
I/O Write
Local to PCI Configuration Access
Command Type
Code(C/BE[3:0]#)
Configuration Memory Read
1010 (Ah)
Configuration Memory Write
1011 (Bh)
________________________________________________________________________________
Page - 7 Version 1.2
Section B
PCI9060
SECTION 2
BUS OPERATION
________________________________________________________________________________
2.2 LOCAL BUS CYCLES
The PCI9060 is a PCI bus master interface chip that connects a PCI host bus to several local processor buses: 32 bit
non-multiplexed (Cx mode), 32 bit multiplexed (Jx mode), and 16 bit multiplexed (Sx mode). The PCI9060 operates in
one of three modes, selected through mode pins, corresponding to three bus types; Cx, Jx and Sx.
2.2.1 Local Bus Slave
As a local bus target, the PCI9060 allows access to the PCI9060 internal registers and PCI bus.
In the Cx and Jx modes, local bus slave accesses to the PCI9060 must be for a 32 bit non-pipelined bus. In the Sx mode,
local bus slave accesses to the PCI9060 must be for a 16 bit non-pipelined bus. The PCI9060 READYo# indicates that a
data transfer has completed.
2.2.2 Local Bus Master
2.2.2.1 Ready/Wait State Control
If the READY input is disabled, the external READY input has no effect on wait states for a local access. Wait states
between data cycles are generated internally by a wait state counter. The wait state counter is initialized with its
configuration register value at the start of each data access.
If the READY input is enabled, the READY input has no effect until the wait state counter is 0. The READY input then
controls the number of additional wait states.
BTERM input is not sampled until the wait state counter is 0.
2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM “Burst Terminate” mode)
Burst Mode
If Bursting is enabled and the BTERM input is not enabled, the PCI9060 emulates the 80960Sx, 80960Jx or 80960Cx
mode of bursting with the exception of the starting burst address. Bursting can start on any boundary and continue up to
an address boundary as described below. After the data at the boundary has been transferred, the PCI9060 generates a
new address cycle (ADS#).
Cx,Jx
Cx,Jx
Cx,Jx
Sx
32 bit bus: 4 Lwords or up to a quad Lword boundary (LA3,LA2 = 11)
16 bit bus: 4 words or up to a quad word boundary (LA2,LA1 = 11)
8 bit bus: 4 bytes or up to a quad byte boundary (LA1,LA0 = 11)
16 bit bus: 8 words or up to a quad Lword boundary (LA3,LA2 = 11)
Continuous Burst Mode (Bterm “Burst Terminate” mode)
BTERM mode enables the PCI9060 to perform long bursts to devices that can accept longer than 4 Lword bursts. The
PCI9060 generates one address cycle and then continues to burst data. If a device requires a new address cycle after a
certain address boundary, it can assert BTERM# input to cause the PCI9060 to generate a new address cycle. BTERM#
input is a ready input that acknowledges the current data transfer and requests that a new address cycle be generated
(ADS#). The address will be for the next data transfer. If BTERM mode is enabled, the PCI9060 asserts BLAST# only if
its FIFOs become FULL/EMPTY or a transfer is complete.
Partial Lwords Accesses
Lword accesses in which not all byte enables are asserted are broken into single address and data cycles.
2.2.2.3 Recovery States
In the Jx and Sx mode, the PCI9060 inserts one recovery state between the last data transfer and the next address cycle.
The PCI9060 does not support the 80960Jx feature of using the READY input to add recovery states. No additional
recovery states are added if the READY input remains asserted during the last data cycle.
________________________________________________________________________________
Page - 8 Version 1.2
Section B
PCI9060
SECTION 2
BUS OPERATION
________________________________________________________________________________
2.2.2.4 Local Bus Read Accesses
For all local bus read accesses, the PCI9060 reads an entire long word. To a 32 bit local bus the PCI9060 performs one
read with all byte enables asserted for each Lword. To a 16 bit local bus, the PCI9060 performs two 16 bit reads for each
Lword. To an 8 bit local bus, the PCI9060 performs four 8 bit reads for each Lword.
In other words, for Direct Slave read accesses, the PCI9060 reads 4 bytes of data starting at an Lword boundary
regardless of the PCI byte enables. For a DMA local bus to PCI bus transfer, the PCI9060 reads 4 bytes of data starting
at an Lword boundary regardless of the DMA start address and DMA byte count.
2.2.2.5 Local Bus Write Accesses
No matter how many bytes, or which byte in the Lword is requested by the PCI bus, the Local Bus always read 4 bytes(32
bits), starting at Lword boundary. For local bus writes, only the bytes specified by a PCI bus master or the PCI9060’s
DMA controller are written. An access to an 8 or 16 bit bus results in the PCI bus Lword being broken into multiple local
bus transfers. For each transfer, the byte enables are encoded as in the 80960Cx to provide local address bits [LA1:LA0].
2.2.2.6 Direct Slave Write Access to 8 and 16 bit bus
A Direct PCI access to an 8 or 16 bit bus results in the PCI bus Lword being broken into multiple local bus transfers. For
each transfer, the byte enables are encoded as in the 80960Cx to provide local address bits [LA1:LA0].
A Direct PCI access to an 8 bit bus with non-adjacent byte enables in a PCI Lword must not be used. Non-adjacent byte
enables cause an incorrect [LA1:LA0] address sequence when bursting to memory. Therefore, for each Lword write to
an 8 bit bus, the PCI9060 does not write data after the first gap. For reads accesses, the PCI9060 reads all bytes of the
Lword. Direct PCI accesses to an 8 bit bus with non-adjacent byte enables are not terminated with a Target Abort.
2.2.2.7 Local Bus Data Parity
There is one data parity pin for each byte lane of the PCI9060 data bus (DP[3:0]). Even data parity is generated for each
lane during local bus reads from the PCI9060 and during PCI9060 master writes to the local bus.
Even data parity is checked during local bus writes to the PCI9060 and during PCI9060 reads from the local bus. Parity is
checked for each byte lane with an asserted byte enable. PCHK# is asserted in the clock cycle following the data being
checked if a parity error is detected.
Generation or use of local bus data parity is optional. The signals on the data parity pins do not effect operation of the
PCI9060. PCI bus parity checking and generation is independent of local bus parity checking and generation.
________________________________________________________________________________
Page - 9 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3. SECTION 3 - FUNCTIONAL DESCRIPTION
3.1 PCI 9060 Initialization
The PCI9060 configuration registers can be programmed by an optional serial EEPROM and/or by a local processor.
EEPROM Initialization
During serial EEPROM initialization, the PCI9060 response to PCI target accesses is RETRYs. During serial EEPROM
initialization, the PCI9060 response to a local processor is to hold off READY.
Local Initialization
The PCI9060 will issue RETRYs to all PCI accesses until the Local Init Done bit in the Init Control Register is set. The Init
Done bit is programmable through local bus configuration accesses. If this bit is not going to be set by a local processor,
then NB# input should be tied low. Holding NB# input low externally forces the Local Init Done bit to 1.
If an EEPROM is not present and the local init status bit is set to "done" by holding the NB# input low, the PCI9060
default values are used.
3.2 RESET
3.2.1 PCI Bus Input RST#
The PCI bus RST# input, causes all PCI bus outputs to float, resets the entire PCI9060 and causes the local reset output
LRESETo# to be asserted.
3.2.2 Local Bus Input LRESETi#
When asserted, the LRESETi# input resets the local bus portion of the PCI9060, clears all local configuration registers,
and causes the LRESETo# output to be asserted.
3.2.3 Local Bus Output LRESETo#
LRESETo# is asserted when PCI bus RST# input is asserted, the LRESETi# input is asserted, or the software reset bit in
the Init Control Register is set to a 1.
3.2.4 Software Reset
A host on the PCI bus can set the software reset bit in the Init Control Register to reset the PCI9060 and assert the
LRESETo# output. The PCI configuration registers will not be reset.
When the software reset bit is set, the PCI9060 responds to PCI accesses but not local bus accesses. The PCI9060
remains in this reset condition until the PCI host clears the bit.
________________________________________________________________________________
Page - 10 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.3 EEPROM
After reset, the PCI9060SD attempts to read the EEPROM to determine its presence. An active low start bit
indicates the EEPROM is present. Refer to the manufacturer’s data sheet for the particular EEPROM being used.
The EEPROM can be read or programmed from the PCI or local bus. Bits 24 through 27 of the EEPROM Control
Register control the PCI9060SD pins which enable the reading or writing of EEPROM bits. Refer to the manufacturer’s
data sheet for the particular EEPROM being used.
3.3.1 SHORT EEPROM LOAD
The following registers are loaded from EEPROM after reset is de-asserted if the SHORT# pin is low.
The bits are organized such that the most significant bit of each 32-bit word is stored first in EEPROM. (The first bit in the
EEPROM is bit 15 of the Device ID). The five 32-bit words are stored sequentially in the EEPROM. Therefore, a 256 bit
device can be used. (Example: National NM93CS06 or compatible. Note: 93C06 is not supported)
EEPROM Offset
EEPROM Value
0
2
4
6
8
A
C
E
10
12
9060
10B5
0680
0002
0000
0100
xxxx
xxxx
xxxx
xxxx
Description
Device ID.
Vendor ID.
Class Code.
Class Code, Revision.
Maximum Latency, Minimum Grant.
Interrupt Pin, Interrupt Line Routing.
MSW of Mailbox 0 (User Defined).
LSW of Mailbox 0 (User Defined).
MSW of Mailbox 1 (User Defined).
LSW of Mailbox 1 (User Defined).
________________________________________________________________________________
Page - 11 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.3.2 LONG EEPROM LOAD
The following registers are loaded from EEPROM after reset is de-asserted if the SHORT# pin is high. The bits
are organized such that the most significant bit of each 16-bit word is stored first in the EEPROM (The first bit in the
EEPROM is bit 15 of the Device ID). The EEPROM value can be entered into a DATA I/O programmer in the order
shown below. The value shown are examples, and will need to be modified for each particular application. The 34 16-bit
words shown above are stored sequentially in the EEPROM. A 1K bit device can be used. (Example: National
NM93CS46 or compatible.) Note: 93CS56 is not supported.
MSW = Most Significant Word(bits 31 - 16)
LSW = Least Significant Word(bits 15 - 0)
EEPROM Offset
EEPROM Value
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
40
42
9060
10B5
0680
0002
0000
0100
xxxx
xxxx
xxxx
xxxx
FF00
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0000
4903
00C3
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Description
Device ID.
Vendor ID.
Class Code.
Class Code, Revision.
Maximum Latency, Minimum Grant.
Interrupt Pin, Interrupt Line Routing.
MSW of Mailbox 0 (User Defined).
LSW of Mailbox 0 (User Defined).
MSW of Mailbox 1 (User Defined).
LSW of Mailbox 1 (User Defined).
MSW of Range for PCI to Local Address Space 0 (16Mbytes).
LSW of Range for PCI to Local Address Space 0 (16Mbytes).
MSW of Local Base Address (Re-Map) for PCI to Local Address Space 0.
LSW of Local Base Address (Re-Map) for PCI to Local Address Space 0
Not Used.
Not Used.
Not Used.
Not Used.
MSW of Range for PCI to Local Expansion ROM.
LSW of Range for PCI to Local Expansion ROM.
MSW of Local Base Address (Re-Map) for PCI to Local Expansion ROM.
LSW of Local Base Address (Re-Map) for PCI to Local Expansion ROM.
MSW of Bus Region Descriptors for PCI to Local Accesses.
LSW of Bus Region Descriptors for PCI to Local Accesses.
MSW of Range for Direct Master to PCI.
LSW of Range for Direct Master to PCI.
MSW of Local Base Address for Direct Master to PCI Memory.
LSW of Local Base Address for Direct Master to PCI Memory.
MSW of Local Base Address for Direct Master to PCI IO/CFG.
LSW of Local Base Address for Direct Master to PCI IO/CFG.
MSW of PCI Base Address (Re-Map) for Direct Master to PCI.
LSW of PCI Base Address (Re-Map) for Direct Master to PCI.
MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG.
LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG.
There are 60 unused bytes in the EEPROM which can be used for user defined applications.
________________________________________________________________________________
Page - 12 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.4 Internal Register Access
The PCI9060 chip provides several internal registers allowing for maximum flexibility in bus interface design and
performance. Among the register types are:
PCI Registers (accessible from PCI bus and Local bus)
Local Configuration Registers (Accessible from PCI and Local bus)
DMA Registers (Accessible from Local bus)
Mailbox Registers (Accessible from PCI and Local bus)
Doorbell Registers (Accessible from PCI and Local bus)
The following figure shows how these registers are accessed:
PCI
Bus
Master
Local
Bus
Master
PCI9060
PCI Registers
Local Configuration
Registers
Accessible through a
Direct Slave Access to
the Local Bus.
Local Address equals
DMA Register’s
Address.(Rev.2A and
above only)
DMA Registers
Mailbox Registers
Set
PCI Interrupt
Clear
PCI to Local
Doorbell Register
Local to PCI
Doorbell Register
Clear
Local Interrupt
Set
Figure 1. PCI9060 Internal Register Access
3.4.1 PCI Bus Access to Internal Registers
The PCI9060 configuration registers can be accessed from the PCI bus via a configuration type 0 cycle.
The PCI9060 local configuration and shared runtime registers can be accessed via a memory cycle with the PCI bus
address matching the base address specified in the PCI9060’s PCI Base Address for Memory Mapped Runtime Register
or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060’s PCI Base Address for I/O
Mapped Runtime Register.
All PCI read or write accesses to the PCI9060 registers can be byte, word or long word accesses. All PCI memory
accesses to the PCI9060 registers can be burst or non-burst. The PCI9060 responds with a PCI Disconnect for all I/O
accesses to the PCI9060 registers.
________________________________________________________________________________
Page - 13 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.4.2 Local Bus Access to Internal Registers
The local processor can access all the internal registers of the PCI9060 through either internal or external address
decode logic. The PCI9060 provides an Address decode Mode Pin (ADMODE) that selects whether the internal address
decode logic is used or whether the designer will supply an external chip select from an external address decoder. The
following Figure shows how the dual address decode logic works.
Address Decode Mode Pin
1
A31
A30
PCI9060
0
S2
compare
PCI9060
S0 (PCI9060 Chip Select)
S1
A29
S0
=
PCI9060
Internal Register
Chip Select
PCI9060
Internal Register
Chip Select
Figure 2. Dual Address Decode Mode
If the Address Decode Mode pin is set to a 1, the internal PCI9060 address decode logic is enabled. In this mode, the
PCI9060 internal registers are selected when local address bits A[31:29] match input address select pins S[2:0]. If the
Address Decode Mode pin is set to a 0, the PCI9060 responds to local bus access when S0 is asserted low through
external chip select logic.
All local read or write accesses to the PCI9060 registers can be byte, word or long word accesses. All local accesses to
the PCI9060 registers can be burst or non-burst.
For the Cx and Jx modes, accesses must be for a 32 bit non-pipelined bus. The PCI9060 READYo# indicates that a data
transfer has completed.
For the Sx mode, accesses must be for a 16 bit non-pipelined bus. The PCI9060 READYo# indicates that a data transfer
has completed.
________________________________________________________________________________
Page - 14 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.5 Direct Data Transfer Modes
The PCI host processor can directly access devices on the local bus for reads and writes. Configuration registers within
the PCI9060 control the decoding and re-mapping of these accesses to the local address space. The local processor (or
intelligent controller) can also directly access the PCI bus. Again, configuration registers within the PCI9060 controls the
decoding and re-mapping of these accesses to the PCI bus address space. Bi-directional FIFOs enable high-performance
bursting on the local and PCI bus.
3.5.1 Direct Bus Master Operation (Local Master to PCI Bus Access)
The PCI9060 supports the direct access of the PCI bus by either the local processor or an intelligent controller. Five
Registers are used to define Local to PCI access; Range, Local Base Address for Direct Master to PCI Memory
Register, Local Base Address for Direct Master to PCI IO/CFG Register, PCI Configuration Address Register, PCI
Base Address.
Decode
The Range register specifies the local address bits that are to be used to decode a Local to PCI access. The local
processor can only perform memory cycles. Therefore, the Local Base Address for Direct Master to PCI Memory
Register is used to decode an access to PCI memory space and the Local Base Address for Direct Master to PCI
IO/CFG Register is used to decode an access to PCI I/O space.
FIFOs
For Local Direct Master memory access to the PCI bus, the PCI9060 has an 8 Lword (32 byte) write FIFO and a 4 Lword
read FIFO. The FIFO enables the local bus to operate independently of the PCI bus and allows high-performance
bursting on the local and PCI bus.
Memory Access
Writes: The PCI9060 continues to accept writes and return READYo# until the write FIFO is full. It then holds off
READYo# until space becomes available in the write FIFO. A programmable Direct Master FIFO ‘almost full’ status
output is provided (DMPAF#).
Reads: The PCI9060 holds off READYo# while gathering an Lword from the PCI bus. A programmable prefetch or
prefetch4 mode is available. In prefetch mode, the PCI9060 continues to prefetch reads while there is space in the read
FIFO. In the prefetch4 mode, the PCI9060 reads only 4 Lwords from the PCI bus. In either mode, the read cycle is
terminated when the local BLAST# input is asserted. Unused read data is flushed from the FIFO.
The PCI9060 does not prefetch read data for single cycle Direct Master reads (local BLAST# input asserted during 1st
data phase). The PCI9060 reads a single PCI Lword.
For all DMA and Direct Master Memory reads, the PCI9060 reads an entire long word (all PCI byte enables are asserted).
IO/CFG Access
For Direct Master I/O or Configuration cycles, the PCI9060 asserts the same PCI bus byte enables as asserted on the
local bus. When a Local Direct Master I/O access to the PCI bus is made, the PCI Configuration Address Register’s
Configuration Enable bit determines if an I/O or Configuration access is to be made to the PCI bus .Local burst accesses
are broken into single PCI I/O address/data cycles. The PCI9060 does not prefetch read data for I/O and CFG reads.
All Direct Master transfers (Cx and Jx) and Local bus accesses to the configuration registers are for a 32 bit data bus.
All Direct Master transfers(Sx mode) and Local bus accesses to the configuration registers are for a 16 bit data bus.
________________________________________________________________________________
Page - 15 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
I/O
If the Configuration Enable bit is clear, a single I/O access is made to the PCI bus. The local address, re-mapped decode
address bits, and the Local byte enables are encoded to provide the address and is output with an I/O read or write
command during the PCI address cycle.
For writes, data is loaded into the write FIFO and READYo# returned to the Local bus. For reads, the PCI9060 holds off
READYo# while gathering a Lword from the PCI bus.
CFG (PCI Configuration Type 0 or Type 1 Cycles)
If the Configuration Enable bit is set, a CFG access is made to the PCI bus. If the PCI configuration Address Register
selects a type 0 command, bits 0-10 from the register are copied to address bits 0-10. Bits 11-15 ‘device number’ are
translated into a single bit being set in PCI address bits 11-31. PCI address bits 11-31 can be used as a device select.
For a type 1 command, bits 0-23 are copied from the register to bits 0-23 of the PCI address. PCI address bits 24-31 are
0. A configuration read or write command code is output with the address during the PCI address cycle.
For writes, local data is loaded into the write FIFO and READYo# returned. For reads, the PCI9060 holds off READYo#
while gathering a Lword from the PCI bus.
Direct Bus Master Lock.
The PCI9060 supports direct local to PCI bus exclusive accesses (locked atomic operations). A locked operation must
start with the local bus input LLOCK# being asserted during a direct local from PCI bus read cycle. Refer to the timing
diagrams included in this specification. Locked operations are enabled or disabled through the PCI Base Address for
Direct Master to PCI Register.
Master/Target Abort.
The PCI9060 Master/Target abort logic enables a local bus master to perform a Direct local bus to PCI bus poll of
devices to determine if they exist (Typically when the local bus performs configuration cycles to the PCI bus).
If a PCI Master, Target Abort, or Retry Time-out is encountered during a transfer, the PCI9060 asserts LSERR# (can be
used as a NMI). If the local bus master is waiting for a READYo#, it is asserted along with BTERMo#. The local
master’s interrupt handler can take the appropriate application specific action. It can then clear the abort bits in the
PCI9060’s PCI Status Register in order to clear the LSERR# interrupt and re-enable Direct Master transfers.
If a local bus master is attempting a burst read from a non-responding PCI device (Master/Target abort ), it receives the
READYo# and BTERMo# for the 1st cycle only. If the local processor cannot terminate its burst cycle, it may cause the
local processor to hang. The local bus will then have to be reset from the PCI bus or by a local watch-dog timer asserting
RESETi#. If the local bus master can not terminate its cycle with BTERMo#, it should not perform burst cycles when
attempting to determine if a PCI device exists.
________________________________________________________________________________
Page - 16 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
PCI
BUS
MASTER
LOCAL
PROCESSOR
1
Initialize Local
Direct Master
Access Registers
Local Range for Direct Master to PCI
Local Base Address for Direct Master to PCI Memory
PCl Base Address (Re-map) for Direct Master to PCI
CFG or I/O
0 = I/O
1 = CFG
Local Base Address for Direct Master to PCI IO/CFG
PCI CFG Address Register for Direct Master to PCI IO/CFG
PCI Command Register
CFG Type
if CFG
enabled
4
PCI Bus Access
3
FIFO
8 Deep Write
4 Deep Read
Local Bus
Access
LOCAL
MEMORY
PCI Address
Space
PCI Base
Address
Local Base Address
for Direct Master To
PCI Memory Space
Range
Memory
Command
Local Base
Address for Direct
Master To PCI
IO/CFG
I/O
Command
PCI Cfg
Command
Type 0 or 1
Range
CFG Address Reg.
0 = I/O
1 = CFG
(Refer to Functional Description)
Figure 3. Local Master Direct Access of PCI Bus
________________________________________________________________________________
Page - 17 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.5.2 Direct Slave Operation (PCI Master to Local Bus Access)
The PCI9060 supports both memory mapped and I/O mapped burst accesses to the local bus from the PCI bus. PCI
Base Address registers are provided to set up the adapter's location in PCI memory and I/O space. In addition, local
mapping registers are provided to allow address translation from PCI address space to local address space.
The PCI9060 disconnects after one transfer for all Direct Slave I/O accesses. Memory access pre-fetching can be
enabled or disabled through the Local Bus Region Descriptor for PCI to Local Accesses Register. If read prefetching is
disabled, the PCI9060 disconnects after one read transfer.
3.5.2.1 PCI to Local Address Mapping
Two local address spaces, space 0 and expansion ROM, are accessible from the PCI bus. Each space is defined by a
set of three registers: Local Address Range, Local Base Address, and PCI Base Address. A fourth register (Bus Region
Descriptors for PCI to Local Accesses Register) defines the local bus characteristics for both regions. Refer to the Figure
5.
Byte Enables (LBE[3:0]#, Pin 139, 140, 141, 142) are encoded based on configured bus width as follows:
32 bit bus:
BE3#
BE2#
BE1#
BE0#
For a 32 bit bus, the four byte enables indicate which of the four bytes are active during a data cycle.
Byte Enable 3 - LD[31:24]
Byte Enable 2 - LD[23-16]
Byte Enable 1 - LD[15-8]
Byte Enable 0 - LD[7-0]
16 bit bus:
BE3#
BE2#
BE1#
BE0#
For a 16 bit bus, BE3#, BE1#, and BE0# are encoded to provide BHE#, LA1, and BLE# respectively.
Byte High Enable (BHE#) - LD[15:8]
not used
Address bit 1 (LA1)
Byte Low Enable (BLE#) - LD[7-0]
8 bit bus:
BE3#
BE2#
BE1#
BE0#
For an 8 bit bus BE1# and BE0# are encoded to provide LA1 and LA0 respectively.
not used
not used
Address bit 1 (LA1)
Address bit 0 (LA0)
Each PCI to Local Address space is defined as part of reset initialization as follows:
Local Bus Initialization Software:
Range: Specifies which PCI address bits are to be used to decode a PCI access to Local bus space. Each of the bits
corresponds to an address bit with Bit 31 corresponds to Address bit 31. A value of 1 should be written to all bits that
should be included in decode and a 0 to all others.
Re-map PCI to Local Addresses into a Local Address space: The bits in this register re-map (replace) the PCI address
bits used in decode as the Local Address bits.
Local Bus Region Description: Specifies the local bus characteristics.
PCI Initialization Software:
PCI reset software determines how much address space is required by writing a value of all ones (1) to a PCI Base
Address register and then reading the value back. The PCI9060 return 0s in don't care address bits, effectively
specifying the address space required. The PCI software then maps the Local Address space into the PCI Address
space by programming the PCI Base Address register.
________________________________________________________________________________
Page - 18 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
PCI
BUS
MASTER
LOCAL
PROCESSOR
1
Initialize Local
Direct Access
Registers
2
Initialize PCI Base
Address
Registers
Range for PCI to Local Address Space 0
Local Base Address (Re-map) for PCI to Local Address Space 0
Bus Region Descriptors for PCI to Local Accesses
Range for PCI to Local Expansion ROM
Local Base Address (Re-map) for PCI to Local Expansion ROM
Bus Region Descriptors for PCI to Local Accesses
Local Bus hardware
characteristics
PCI Base Address to Local Address space 0
PCI Base Address to Local Expansion ROM
3
PCI Bus Access
4
FIFO
8 Deep Write
8 Deep Read
Local Bus
Access
PCI
Address
Space
PCI Base
Address
LOCAL
MEMORY
Local Base
Address
Range
Figure 4. PCI Master Direct Access of Local Bus
________________________________________________________________________________
Page - 19 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
Example: A 1 MB local address space 12300000h through 123FFFFFh is accessible from the PCI bus at PCI addresses
78900000h through 789FFFFFh.
1. Local initialization software sets the Range and Local Base address registers as follows:
Range- FFF00000h (1 MB, decode the upper 12 PCI address bits)
Local Base Address(re-map)- 123XXXXXh (Local Base Address for PCI to Local accesses)
2. PCI Initialization software writes all 1s to the PCI Base Address and then read it back. The PCI9060
returns a value FFF00000h. The PCI software then writes to the PCI Base Address register.
PCI Base Address- 789XXXXXh (PCI Base Address for access to Local Address space)
For PCI direct access to the local bus, the PCI9060 has an 8 Lword (32 byte) write FIFO and a 8 Lword read FIFO. The
FIFO enables the local bus to operate independent of the PCI bus. The PCI9060 can be programmed to return a RETRY
response or to throttle TRDY for any PCI bus transaction that is attempting to write to the PCI9060 local bus when the
FIFO is full.
For PCI read transactions from the PCI9060 local bus, the PCI9060 holds off TRDY while gathering the local bus Lword
to be returned. For read accesses mapped to the PCI memory space, the PCI9060 prefetches up to 4 Lwords from the
local bus. Unused read data is flushed from the FIFO. For read accesses mapped to the PCI I/O space the PCI9060 does
not prefetch read data, it breaks each read of the burst cycle into a single address/data cycle on the local bus.
The period of time that the PCI9060 holds off TRDY can be programmed in the Local Bus Region Descriptor register.
The PCI9060 issues a RETRY to the PCI bus transaction master when the programmed time period expires. This would
happen when the PCI9060 can not gain control of the local bus and return TRDY within the programmed time period.
3.5.2.2 Deadlock and BREQo
A deadlock situation can occur when a master on the PCI bus wants to access the PCI9060 local bus at the same time
that a master on the local PCI9060 bus wants to access the PCI bus. Two types of deadlock situations can occur:
1. A master on the local bus is performing a direct bus master access to a PCI bus device other than the PCI bus device
that is trying to access the local bus at the same time (PARTIAL DEADLOCK).
2. A master on the local bus is performing a direct bus master access to the same PCI bus device that is trying to access
the local bus at the same time (FULL DEADLOCK).
This applies only to direct ("pass through") master and slave accesses through the PCI9060. Deadlock will not occur in
transfers through the PCI9060 DMA controller or the mailboxes.
For PARTIAL DEADLOCK, the PCI access to the local bus times out (programmable through the Local Bus Region
Description for PCI to Local Accesses Register) and the PCI9060 responds with a PCI RETRY. The PCI specification
requires that a PCI master release its request for the PCI bus (deasserts REQ#) for a minimum of 2 PCI clocks after
receiving a RETRY. This allows the PCI bus arbiter to grant the PCI bus to the PCI9060 so that it can complete its direct
master access and free up the local bus. Possible solutions are described below for cases in which the PCI bus arbiter
does not function as described (PCI bus architecture dependent), waiting for a time-out is undesirable, or a FULL
DEADLOCK condition exists.
________________________________________________________________________________
Page - 20 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
Backoff
The PCI9060 contains a pin (BREQo) that indicates that a possible deadlock condition exists. The PCI9060 starts the
BREQo timer (programmable through registers) when it detects the following conditions:
a. A master on the local bus is performing a direct bus master access to the PCI bus.
b. A master on the PCI bus is trying to access memory or an I/O device on the local bus and is not gaining access (i.e.
has not received HOLDA).
If the timer expires and the PCI9060 still has not received HOLDA, the PCI9060 asserts BREQo. External bus logic can
use this as a signal to perform backoff.
A backoff cycle is device/bus architecture dependent. External logic (arbiter) can assert the necessary signals to cause
the local master to release the local bus (backoff). After backing off the local master, it can grant the bus to the PCI9060
(by asserting HOLDA).
The PCI9060 considers the local master to PCI bus access terminated when it detects HOLDA. It then proceeds with the
PCI master to local bus access. When this access is complete and the PCI9060 releases the local bus, the external logic
can release backoff and the local master can resume the cycle that was interrupted by the backoff cycle. The write FIFO
of the PCI9060 retains all the data it has acknowledged (i.e. the last data for which READYo# was asserted and HOLDA
was not asserted).
After the backoff condition ends the local master restarts the last cycle with ADS#. For writes, the data following this
ADS# should be the data that was not acknowledged by the PCI9060 prior to the backoff cycle (i.e. the last data for
which there was no READYo# asserted or HOLDA was asserted).
Software/Hardware Solution for systems without backoff capability
For adapters which do not support backoff, a possible deadlock solution is as follows:
PCI host software, external local bus hardware, general purpose output USERO, and general purpose input (USERI) can
be used by PCI host software to prevent deadlock. USERO can be set to request that the external arbiter not grant the
bus to any local bus master except the PCI9060. A status output from the local arbiter can be connected to general
purpose input USERI to indicate that no local bus master owns the local bus. The input can be read by the PCI host to
determine that no local bus master currently owns the local bus. The PCI host can then do a direct slave access. When
the host is done it clears USERO. For devices that support pre-empt, USERO can be used to pre-empt the current bus
master device. The current local bus master device completes its current cycle and gives up the local bus (deasserts
LHOLD).
Software Solutions to Deadlock
PCI Host Software and Local Bus Software can use a combination of mailbox registers, doorbell registers, interrupts,
direct local to PCI accesses and direct PCI to local accesses to avoid deadlock.
3.5.3 Direct Slave Priority
Direct Slave accesses have higher priority than DMA accesses.
Direct Slave accesses pre-empt DMA transfers. When the PCI9060 DMA controller owns the local bus, its LHOLD output
is asserted, its LDSHOLD output is deasserted and its LHOLDA input is asserted. When a Direct Slave access is made,
the PCI9060 gives up the local bus within two Lword transfers by deasserting LHOLD and floating its local bus outputs.
After the PCI9060 samples its LHOLDA input deasserted, it requests the local bus for a Direct Slave transfer by asserting
LHOLD and LDSHOLD. When the PCI9060 receives LHOLDA it drives the bus and performs the Direct Slave transfer.
Upon completion of the Direct Slave transfer, the PCI9060 gives up the local bus by deasserting LHOLD, deasserting
LDSHOLD and floating its local bus outputs. After the PCI9060 samples its LHOLDA deasserted and its local pause timer
is zero, it requests the local bus for a DMA transfer by re-asserting LHOLD. When it receives LHOLDA it drives the bus
and continues with the DMA transfer.
________________________________________________________________________________
Page - 21 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.6 DMA Operation
The PCI9060 supports two independent DMA channels capable of transferring data from the local bus to the PCI bus or
from the PCI bus to the local bus. Each channel consists of a DMA controller and a bi-directional FIFO. Both channels
support chaining and non-chaining DMA transfers. The DMA registers may be accessed from PCI bus on REV. 3 (some
additional design considerations required.)
3.6.1 Non-Chaining Mode DMA
The local or the host processor sets the local address, PCI address, transfer count, and transfer direction. The local or
the host processor then sets a control bit to initiate the transfer. Once the transfer is complete, the PCI9060 generates
an interrupt to the local processor (programmable). The local interrupt can be routed to the LINTi# input to generate a
PCI interrupt (INTA#).
DMA registers are accessible from the Local and PCI bus. A PCI master can access the DMA registers by performing a
Direct Slave access to the local bus (Rev. 3 only). The local address should be that of the desired DMA register.
PCI HOST
MEMORY
Set DMA mode
to
non-chaining
Mode Register
Memory block
to transfer
Set up transfer
Parameters
PCI Address Register
Local Address Regsiter
LOCAL
MEMORY
Transfer size (byte count) Register
Descriptor Pointer Register
( set direction only )
Memory block
to transfer
Command/Status Register
Setting the Enable and Go
bits in the DMA
Command/Status register
initiates the DMA transfer
Figure 5. Non-Chaining DMA Initialization
________________________________________________________________________________
Page - 22 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.6.2 Chaining Mode DMA
Chaining DMA operates as follows:
The local or the host processor sets up descriptor blocks in local memory which are composed of a PCI address, Local
address, transfer count, transfer direction, and address of the next descriptor block. The local or the host processor then
sets up the initial descriptor block's address in the PCI9060’s descriptor pointer register and initiates the transfer by
setting a control bit. The PCI9060 loads the 1st descriptor block and initiates the data transfer. The PCI9060 continues to
load descriptor blocks and transfer data until it detects the end of chain bit set in the next descriptor pointer register. The
PCI9060 can be programmed to interrupt the local processor upon completion of each block transfer and after all block
transfers have been completed (done).
LOCAL
MEMORY
Set DMA mode
to
chaining
Mode Register
1st PCI Address
1st Local Address
Set up 1st Descriptor
Pointer Register
( 1st only requires
Descriptor Pointer )
1st Transfer size (byte count)
Next Descriptor Pointer
PCI Address
Descriptor Pointer Register
PCI HOST
MEMORY
Local Address
1st Memory block
to transfer
Transfer size (byte count)
Next Descriptor Pointer
Command/Status Register
Setting the Enable and Go
bits in the DMA
Command/Status register
initiates the DMA transfer
End of chain
specification bit
Next Memory block
to transfer
1st Memory block
to transfer
Next Memory block
to transfer
Figure 6. Chaining DMA Initialization
________________________________________________________________________________
Page - 23 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.6.3 DMA Data Transfers
The PCI9060 supports two independent DMA channels (Ch 0 with 64 byte FIFO and Ch 1 with 32 byte FIFO ). Either can
be programmed to transfer data from the PCI bus side to the local bus side or from the local bus side to the PCI bus side.
Refer to the following figures for a description of operation:
3.6.3.1 Local to PCI Bus DMA Transfer
Unload FIFO by PCI Bus
Write Cycles
PCI
Arbitration
•
•
PCI Bus Arbitration
Release control of the PCI bus
whenever the FIFO becomes empty,
the PCI latency timer expires and PCI
GRANT is deasserted, a PCI
Disconnect is received, or a Direct
Local to PCI request is pending.
Rearbitrate for control of the PCI bus
when the pre-programmed # of entries
in the FIFO become available or after 2
PCI clocks if a disconnect was
received.
Load FIFO by Local Bus
Read Cycles
FIFO
Local Bus
Arbitration
•
(Programmable)
Local Interrupt Generation
•
Done
•
Chaining:
Terminal
Count for current
descriptor
Chaining mode Descriptors:
At the start of each block transfer, in
chaining mode only, load the DMA
Registers by reading 4 Lwords from the
address specified in the Next Descriptor
Pointer Register.
GNT# REQ# LHOLDA LHOLD
•
•
Local Bus Arbitration
Release control of the Local bus whenever
the FIFO becomes full, terminal count is
reached, the local latency timer expires, the
BREQ input is asserted, or a Direct PCI to
Local Bus Request is pending.
Rearbitrate for control of the local bus when
the pre-programmed # of empty entries in
the FIFO becomes available. If the latency
timer expired, wait until the pause timer
expires.
Figure 7. Local to PCI Bus DMA Data Transfer Operation
________________________________________________________________________________
Page - 24 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.6.3.2 PCI to Local Bus DMA Transfer
Load FIFO by PCI Bus
Read Cycles
PCI
Arbitration
•
•
PCI Bus Arbitration
Release control of the PCI bus
whenever the FIFO becomes full,
terminal count is reached, the PCI
latency timer expires and PCI GRANT
is deasserted, a PCI Disconnect is
received, or a Direct Local to PCI
request is pending.
Rearbitrate for control of the PCI bus
when the pre-programmed # of empty
entries in the FIFO becomes available
or after 2 PCI clocks if a disconnect
was received.
Unload FIFO by Local
Bus Write Cycles
FIFO
Local Bus
Arbitration
•
(Programmable)
Local Interrupt Generation
•
Done
•
Chaining:
Terminal
Count for current
descriptor
Chaining mode Descriptors:
At the start of each block transfer, in
chaining mode only, load the DMA
Registers by reading 4 Lwords from the
address Specified in the Next Descriptor
Pointer Register.
GNT# REQ# LHOLDA LHOLD
•
•
Local Bus Arbitration
Release control of the Local bus whenever
the FIFO becomes empty, the local latency
timer expires, the BREQ input is asserted,
or a Direct PCI to Local Bus Request is
pending.
Rearbitrate for control of the local bus when
the pre-programmed # of entries becomes
available in the FIFO or the PCI terminal
count is reached. If the latency timer
expired, wait until the pause timer expires.
Figure 8. PCI to Local Bus DMA Data Transfer Operation
________________________________________________________________________________
Page - 25 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.6.3.3 Unaligned Transfers
For unaligned local to PCI transfers, the PCI9060 reads a partial Lword from the local bus. It then continues to read
Lwords from the local bus. The Lwords are assembled, aligned to the PCI bus address and loaded into the FIFO.
For PCI to local transfers, Lwords are read from the PCI bus and loaded into the FIFO. On the local side, the Lwords are
assembled from the FIFO, aligned to the local bus address and written to the local bus. On both the local and PCI buses,
the byte enables for writes determine LA0, LA1 for the start of a transfer. For the last transfer the byte enables specify
the bytes to be written. All reads are Lwords.
All PCI transfers(reads and writes) are Lwords(32 bits).
3.6.4 Demand Mode DMA
A bit in each channel can specify that the channel operate in Demand Mode. In Demand Mode, the user sets up the DMA
controller’s configuration registers and initiates a transfer. Data is transferred when the DMA channels DREQ# input is
asserted. It asserts DACK# to indicate that the current local bus transfer is in response to the DREQ# input. The DMA
controller transfers data until the transfer count is reached. The minimum transfer size per DREQ# input is one Lword
(32bits). This may result in multiple transfers for an 8 or 16 bit bus. Refer to the timing diagrams included in this
specification.
3.6.5 DMA Priority
DMA channel 0 priority, DMA channel 1 priority or rotating priority can be specified in the DMA Arbitration Register.
3.6.6 DMA Arbitration
The PCI9060 DMA controller releases control of the local bus (deassert LHOLD) once its FIFOs are full in a local to PCI
transfer, its FIFOs are empty in a PCI to local transfer, when the local latency timer expires, when the BREQ input is
asserted or a Direct Slave access is pending.
The DMA controller releases control of the PCI bus when the FIFOs are full/empty, when the PCI latency timer expires
and it loses the PCI grant signal, or a Target Disconnect response is received. It de-asserts its PCI bus request (REQ#)
for a minimum of 2 PCI clocks.
3.6.6.1 Local Latency and Pause Timers
A local bus latency timer and local bus pause timer are programmable through the DMA Arbitration Register. If the local
latency timer expires, the PCI9060 completes the current Lword transfer and release LHOLD. After its programmable
Pause Timer expires, it reasserts LHOLD. When it receives LHOLDA, it continues with the transfer. The PCI bus transfer
continues until the FIFO is empty for a local to PCI transfer or until full for a PCI to local transfer.
3.7 BREQ input.
When the PCI9060 owns the local bus, its LHOLD output is asserted and its LHOLDA input is asserted. When the
PCI9060 samples BREQ asserted during a DMA transfer or a Direct Slave read or write transfer, it gives up the local bus
within two Lword transfers by deasserting LHOLD and floating its local bus outputs. The local arbiter can now grant the
local bus to another local master. After the PCI9060 samples that its LHOLDA is deasserted and its local pause timer is
zero, it will re-assert LHOLD to request the local bus. When the PCI9060 receives LHOLDA it will drive the bus and
continue where it left off.
3.8 Doorbell Registers
There are two 32 bit doorbell interrupt/status registers in the PCI9060. One is assigned to the PCI bus interface, while
the other is assigned to the local bus interface.
The local processor can generate a PCI bus interrupt by writing to the PCI doorbell register
A PCI host can generate a local bus interrupt by writing to the local doorbell register.
________________________________________________________________________________
Page - 26 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.9 Mailbox Registers
There are eight 32 bit mailbox registers in the PCI9060 that can be written and read by both buses. These registers can
be used to pass command and status information directly between PCI bus devices and local bus devices.
3.10 Interrupts
3.10.1 PCI Interrupts (INTA#)
The local to PCI doorbell register, local interrupt input, or a master/target abort status condition, can generate a PCI9060
PCI Interrupt (INTA#).
INTA# or individual sources of an interrupt can be enabled or disabled through the PCI9060 Interrupt Control/Status
Register. The Interrupt Control/Status Register also provides interrupt status for each source of the interrupt.
The PCI9060 PCI bus interrupt is an asynchronous level output. An interrupt can be cleared by disabling a sources
interrupt enable bit or clearing the cause of an interrupt.
3.10.1.1 Doorbell Interrupt
A local bus master can generate a PCI bus interrupt by writing to the Local to PCI Doorbell Register. The PCI host
processor can then read the PCI9060 Interrupt Control/Status Register to determine that a doorbell interrupt is pending. It
can then read the PCI9060 Local to PCI Doorbell Register.
Each bit in the Local to PCI Doorbell register is individually controlled. Bits in the Doorbell Register can only be set by
the Local side.. From the local side, writing a 1 to any bit position sets that bit and writing a 0 to a bit position has no
effect. Bits in the Local to PCI Doorbell Register can only be cleared from the PCI side. From the PCI side, writing a 1 to
any bit position clears that bit and writing a 0 to a bit position has no effect.
The interrupt remains asserted as long any of the Local to PCI Doorbell Registers bits is set and the PCI Doorbell
interrupt is enabled.
When the PCI bus is accessing the Doorbell Register (or any configuration register), the Local bus is held off from
accessing the PCI9060 registers and the local READYo# signal is deasserted.
3.10.1.2 Local Interrupt Input
Asserting Local bus input pin LINTi# can generate a PCI bus interrupt. The PCI host processor can read the PCI9060
Interrupt Control/Status Register to determine that an interrupt is pending due to the LINTi# pin being asserted.
The interrupt remains asserted as long as the LINTi# pin is asserted and the Local Interrupt input is enabled. Adapter
specific action can be taken by the PCI host processor to cause the Local bus to release LINTi#.
3.10.1.3 Master/Target Abort Interrupt
The PCI9060 sets the master abort or target abort status bit in the PCI configuration register upon detection of a master
or target abort. These status bits cause PCI INTA# to be asserted if interrupts are enabled.
The interrupt remains asserted as long as the master or target abort bits remain set in the PCI Configuration Status
Register and master/target abort interrupt is enabled. A PCI type 0 configuration access or a local access must be used
to clear the master abort and target abort interrupt bits in the PCI Configuration Status Register.
Bits 24-26 of the Interrupt Control/Status Register are latched at the time of a target abort interrupt or a master abort
interrupt. They provide information as to who was master when an abort occurred. They are updated whenever an abort
occurs. If an abort interrupt is not pending, they have are not defined.
________________________________________________________________________________
Page - 27 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.10.2 Local Interrupts (LINTo#)
The PCI to local doorbell register, a PCI BIST interrupt, DMA channel 0, or DMA channel 1 can generate a PCI9060
local interrupt. (LINT0#)
LINTo# or individual sources of an interrupt can be enabled or disabled through the PCI9060 Interrupt Control/Status
Register. The Interrupt Control/Status Register also provides interrupt status for each source of the interrupt.
The PCI9060 local interrupt is a synchronous level output. An interrupt can be cleared by disabling a source’s interrupt
enable bit or clearing the cause of an interrupt.
3.10.2.1 Doorbell Interrupt
A PCI bus master can generate a local bus interrupt by writing to the PCI to Local Doorbell Register. The Local
processor can then read the PCI9060 Interrupt Control/Status Register to determine that a doorbell interrupt is pending. It
can then read the PCI9060 PCI to Local Doorbell Register.
Each bit in the PCI to Local Doorbell register is individually controlled. Bits in the Doorbell Register can only be set by
the PCI side.. From the PCI side, writing a 1 to any bit position sets that bit and writing a 0 to a bit position has no effect.
Bits in the PCI to Local Doorbell Register can only be cleared from the Local side. From the Local side, writing a 1 to any
bit position clears that bit and writing a 0 to a bit position has no effect.
The interrupt remains asserted as long any of the PCI to Local Doorbell Registers bits is set and the Local Doorbell
interrupt is enabled.
When the Local bus is accessing the Doorbell Register (or any configuration register), the PCI bus is issued a RETRY.
3.10.2.2 Built In Self Test Interrupt (BIST)
A PCI bus master can generate a local bus interrupt by performing a PCI type 0 configuration write to a bit in the PCI
BIST register. The Local processor can then read the PCI9060 Interrupt Control/Status Register to determine that a BIST
interrupt is pending.
The interrupt remains asserted as long as the bit is set and the BIST interrupt is enabled. The Local bus should reset the
bit when BIST is complete. PCI Host software may fail the device if the bit is not reset after 2 seconds.
3.10.2.3 DMA Channel 0/Channel 1 Interrupts
A DMA channel can generate a local bus interrupt when done (transfer complete) or after a transfer is complete for a
descriptor in chaining mode. The Local processor can then read the PCI9060 Interrupt Control/Status Register to
determine that a DMA channel’s interrupt is pending. A Done Status Bit in the Control/Status Register can be used to
determine if the interrupt is a done interrupt or as the result of a transfer for a descriptor in a chain completing.
A channel’s Mode Register is used to enable a done interrupt. In chaining mode, a bit in the channel’s Next Descriptor
Pointer Register (loaded from local memory) specifies if an interrupt should be generated at the end of the transfer for
the current descriptor.
A channel’s interrupt is cleared by writing to a bit in the DMA Command/Status Register.
3.10.3 PCI SERR# (PCI NMI)
The PCI9060 generates an SERR# pulse if parity checking is enabled in the PCI Command Register and it detects an
address parity error or the Generate SERR# Bit in the Interrupt Control/Status Register is 0 and a 1 is written.
The SERR# output can be enabled or disabled through the PCI Command Register.
________________________________________________________________________________
Page - 28 Version 1.2
Section B
PCI9060
SECTION 3
FUNCTIONAL DESCRIPTION
________________________________________________________________________________
3.10.4 Local LSERR# (Local NMI)
The LSERR# interrupt output is asserted if the PCI bus Target Abort or Master Abort status bit is set in the PCI Status
Configuration Register or a parity error status bit is set in the PCI Status Configuration Register.
If parity error checking is enabled in the PCI Command Register, the PCI9060 sets the Master Detected Parity Error
Status bit in the PCI Status Register if it detects a parity error during a PCI9060 master read or it detects the PCI bus
signal PERR# being asserted during a PCI9060 master write.
If the PCI9060 detects a data parity error during a PCI9060 master read, a data parity error during a slave write access
to the PCI9060 or the PCI9060 detects an address parity error, it sets a parity error bit in the PCI Status Register.
The PCI9060 Interrupt Control/Status Register can be used to individually enable or disable LSERR# for an abort or
parity error. LSERR# is a level output which remains asserted as long as the Abort or Parity Error Status Bits are set.
________________________________________________________________________________
Page - 29 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4. SECTION 4 - REGISTERS
4.1 Register Address Mapping
PCI CONFIGURATION REGISTERS
Local
(Offset from
chip select
address)
To ensure software compatibility with other versions of
PCI9060 family and to ensure compatibility with future
enhancement, all unused bits should be written to 0.
31
23
15
7
PCI CFG
register
address
0
00h
Device ID
Vendor ID
00h
04h
Status
Command
04h
08h
0ch
Class Code
BIST
Header Type
Latency Timer
Revision ID
08h
Cache Line
Size
0Ch
10h
PCI Base Address for Memory Mapped Runtime Registers
10h
14h
PCI Base Address for I/O Mapped Runtime Registers
14h
18h
PCI Base Address for Local Address Space 0
18h
1Ch
1Ch
20h
20h
24h
24h
28h
Reserved
28h
2Ch
Reserved
2Ch
30h
PCI Base Address to local Expansion ROM
30h
34h
Reserved
34h
38h
Reserved
38h
3Ch
Max_lat
Min_Gnt
Interrupt Pin
Interrupt Line
3Ch
________________________________________________________________________________
Page - 30 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
LOCAL CONFIGURATION REGISTERS
Local
(Offset from
chip select
address)
To ensure software compatibility with other versions of
PCI9060 family and to ensure compatibility with future
enhancement, all unused bits should be written to 0.
31
PCI
(Offset from
Runtime
Base addr)
0
80h
Range for PCI to Local Address Space 0
00h
84h
Local Base Address (Re-map) for PCI to Local Address Space 0
04h
88h
Reserved
08h
8Ch
Reserved
0Ch
90h
Range for PCI to Local Expansion ROM
10h
94h
Local Base Address (Re-map) for PCI to Local Expansion ROM and BREQo control
14h
98h
Bus Region Descriptors for PCI to Local Accesses
18h
9Ch
Range for Direct Master to PCI
1Ch
A0h
Local Base Address for Direct Master to PCI Memory
20h
A4h
Local Base Address for Direct Master to PCI IO/CFG
24h
A8h
PCI Base Address (Re-map) for Direct Master to PCI
28h
ACh
PCI Configuration Address Register for Direct Master to PCI IO/CFG
2Ch
SHARED RUN TIME REGISTERS
Local
(Offset from
chip select
address)
To ensure software compatibility with other versions of
PCI9060 family and to ensure compatibility with future
enhancement, all unused bits should be written to 0.
31
PCI
(Offset from
Runtime
Base addr)
0
C0h
Mailbox Register 0
40h
C4h
Mailbox Register 1
44h
C8h
Mailbox Register 2
48h
CCh
Mailbox Register 3
4Ch
D0h
Mailbox Register 4
50h
D4h
Mailbox Register 5
54h
D8h
Mailbox Register 6
58h
DCh
Mailbox Register 7
5Ch
E0h
PCI to Local Doorbell Register
60h
E4h
Local to PCI Doorbell Register
64h
E8h
Interrupt Control / Status
68h
ECh
EEPROM Control, PCI Command Codes, User I/O Control, Init Control
6Ch
________________________________________________________________________________
Page - 31 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
LOCAL DMA REGISTERS
Local
(Offset from
chip select
address)
To ensure software compatibility with other versions of
PCI9060 family and to ensure compatibility with future
enhancement, all unused bits should be written to 0.
31
0
PCI
(Offset from
Runtime
Base addr)
(See Note 1)
100h
DMA Ch 0 Mode
100h
104h
DMA Ch 0 PCI Address
104h
108h
DMA Ch 0 Local Address
108h
10Ch
DMA Ch 0 Transfer Byte Count
10Ch
110h
DMA Ch 0 Descriptor Pointer
110h
114h
DMA Ch 1 Mode
114h
118h
DMA Ch 1 PCI Address
118h
11Ch
DMA Ch 1 Local Address
11Ch
120h
DMA Ch 1 Transfer Byte Count
120h
124h
DMA Ch 1 Descriptor Pointer
124h
128h
DMA Command/Status Register
128h
12Ch
DMA Arbitration Register 0
12Ch
130h
DMA Arbitration Register 1
130h
Note 1: The DMA Registers are accessible from the PCI side for the 9060 REV. 3.
The special design consideration requirements are as follows:
Method I: Direct Slave access (Space 0) to DMA Registers.
1. Set the Local Base Address (Re-map) Register (Table 24) for Space 0 to point to the address space in
which the local bus accesses the PCI9060 local register.
2. Program the Local Bus Region Descriptor Register (Table 29) to bit[1:0]=11; 32 bit bus, and bit[7]=0;
Bterm input disabled.
3. If PCI9060 READYo# pin is connected or driven by the PCI9060 READYi#, then set the bit[5:2]=0000; 0
wait state, and bit[6]=1; Ready input enabled, on Table 29(Local Bus Descriptor Register).
4. If PCI9060 READYo# pin does not cause the PCI9060 READYi#, then set the bit[5:2]=0010; 2 wait
states, and bit[6]=0; Ready input disabled, on Table 29(Local Bus Descriptor Register).
5. Read or write the PCI9060 DMA Registers by performing a PCI to Local access to Local Address
Space 0. (Address bits[8:2] specify the DMA Register offset.)
Method II: Direct Slave access (Expansion ROM) to DMA Registers
1. set the Local Base Address (Re-map) Register (Table 28) for the Expansion ROM to point to the
address space in which the local bus accesses the PCI9060 local register.
2. Program the Local Bus Region Descriptor Register (Table 29) to bit[17:16]=11; 32 bit bus, and bit[23]=0;
Bterm input disabled.
3. If PCI9060 READYo# pin is connected or driven by the PCI9060 READYi#, then set the bit[21:18]=0000;
0 wait state, and bit[22]=1; Ready input enabled, on the Table 29(Local Bus Descriptor Register).
4. If PCI9060 READYo# pin does not cause the PCI9060 READYi#, then set the bit[21:18]=0010; 2 wait
states, and bit[22]=0; Ready input disabled, on the Table 29(Local Bus Descriptor Register).
5. Read or write the PCI9060 DMA Registers by performing a PCI to Local access to Local Address
Expansion ROM (Address bits[8:2] specify the DMA Register offset.)
________________________________________________________________________________
Page - 32 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2 PCI Configuration Registers
All registers may be written to or read from in byte, word or long word accesses.
4.2.1 PCI Configuration ID Register (Offset 00h)
________________________________________________________________________________
Table 1: PCI Configuration ID Register Description
Field
15:
0
31:16
Description
Vendor ID - Identifies the manufacturer of the device. Defaults to the PCI
SIG issued vendor ID of PLX (10B5h) if no EEPROM is present and pin
NB# (no local bus initialization) is asserted low.
Device ID - Identifies the particular device. Defaults to the PLX part
number for PCI interface chip (9060h) if no EEPROM is present and pin
NB# (no local bus initialization) is asserted low.
Read
Write
Yes
Local
Bus
Yes
Local
Bus
Value after
Reset
10B5h
or
0
9060h
or
0
4.2.2 PCI Command Register (Offset 04h)
________________________________________________________________________________
Table 2: PCI Command Register Description
Field
0
1
2
3
4
5
6
7
8
9
15:10
Description
I/O Space. A value of 1 allows the device to respond to I/O space
accesses. A value of 0 disables the device from responding to I/O space
accesses.
Memory Space. A value of 1 allows the device to respond to memory
space accesses. A value of 0 disables the device from responding to
memory space accesses.
Master Enable. Controls a device’s ability to act as a master on the PCI
bus. A value of 1 allows the device to behave as a bus master. A value
of 0 disables the device from generating bus master accesses. State after
RST# is 0.
Special Cycle. This bit is not supported.
Memory Write/Invalidate. This bit is not supported.
VGA Palette Snoop. This bit is not supported.
Parity Error Response. A value of 0 indicates that a parity error is ignored
and operation continues. A value of 1 indicates that parity checking is
enabled.
Wait Cycle Control.
Controls whether or not the device does
address/data stepping. A 0 value indicates the device never does
stepping. A value of 1 indicates that the device always does stepping.
This value is hardwired to 0.
SERR# Enable. A value of 1 enables the SERR# driver. A value of 0
disables the driver
Fast Back-to-Back Enable. Indicates what type of fast back-to-back
transfers a Master can perform on the bus. A value of 1 indicates that
fast back-to-back transfers can occur to any agent on the bus. A value of
0 indicates fast back-to-back transfers can only occur to the same agent
as the previous cycle.
Reserved.
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
No
No
No
Yes
0
0
0
0
Yes
No
0
Yes
Yes
0
Yes
No
0
Yes
No
0
________________________________________________________________________________
Page - 33 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.3 PCI Status Register (Offset 06h)
________________________________________________________________________________
Table 3: PCI Status Register Description
Field
6:0
7
8
10:9
11
12
13
14
15
Description
Reserved
Fast Back-to-Back Capable. When this bit is set to a 1, it indicates the
adapter can accept fast back-to-back transactions. A 0 indicates the
adapter cannot.
Master Data Parity Error Detected. This bit is set to a 1 when three
conditions are met: 1) the PCI9060 asserted PERR# itself or observed
PERR# asserted; 2) the PCI9060 was the bus master for the operation in
which the error occurred; 3) the Parity Error Response bit in the
Command Register is set. Writing a 1 to this bit clears the bit (0).
DEVSEL Timing. Indicates timing for DEVSEL# assertion. a value of 01
is medium.
Target Abort. When this bit is set to a 1, this bit indicates the PCI9060
has signaled a target abort. Writing a 1 to this bit clears the bit (0).
Received Target Abort. When set to a 1, this bit indicates the PCI9060
has received a target abort signal. Writing a 1 to this bit clears the bit (0).
Received Master Abort. When set to a 1, this bit indicates the PCI9060
has received a master abort signal. Writing a 1 to this bit clears the bit
(0).
Signaled System Error. When set to a 1, this bit indicates the PCI9060
has reported a system error on the SERR# signal. Writing a 1 to this bit
clears the bit (0).
Detected Parity Error. When set to a 1, this bit indicates the PCI9060 has
detected a PCI bus parity error, even if parity error handling is disabled
(the Parity Error Response bit in the Command Register is clear). One of
three conditions can cause this bit to be set. 1) the PCI9060 detected a
parity error during a PCI address phase; 2) the PCI9060 detected a data
parity error when it was the target of a write; 3) the PCI9060 detected a
data parity error when performing a master read operation. Writing a 1 to
this bit clears the bit (0).
Read
Write
Value after
Reset
Yes
Yes
No
No
0
1
Yes
Yes
0
Yes
No
01
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
4.2.4 PCI Revision ID Register (Offset 08h)
________________________________________________________________________________
Table 4: PCI Revision ID Register Description
Field
7:0
Description
Revision ID. The silicon revision of the PCI9060.
Read
Write
Yes
Local
Bus
Value after
Reset
Current Rev #
________________________________________________________________________________
Page - 34 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.5 PCI Class Code Register (Offset 09 - 0Bh)
________________________________________________________________________________
Table 5: PCI Class Code Register Description
Field
7:0
Description
15:8
Specific register level programming interface (00h).
defined.
Sub-class Encoding (80h). Other bridge device.
23:16
Base Class Encoding other Bridge Device
No interface
Read
Write
Yes
Local
Bus
Local
Bus
Local
Bus
Yes
Yes
Value after
Reset
00
80h
06h
4.2.6 PCI Cache Line Size Register (Offset 0Ch)
________________________________________________________________________________
Table 6: PCI Cache Line Size Register Description
Field
7:0
Description
System cache line size in units of 32-bit words. Not supported.
Read
Write
Value after
Reset
Yes
No
0
4.2.7 PCI Latency Timer Register (Offset 0Dh)
________________________________________________________________________________
Table 7: PCI Latency Timer Register Description
Field
7:0
Description
Latency Timer. Specifies in units of PCI bus clocks, the amount of
time the PCI9060, as a bus master, can burst data on the PCI bus.
Read
Write
Value after
Reset
Yes
Yes
0
4.2.8 PCI Header Type Register (Offset 0Eh)
________________________________________________________________________________
Table 8: PCI Header Type Register Description
Field
6:0
7
Description
Read
Configuration Layout Type. Specifies the layout of bits 10h through 3Fh in
configuration space. Only one encoding 0 is defined. All other encodings
are reserved.
Header Type. A 1 indicates multiple functions, a 0 indicates a single
function.
Write
Value after
Reset
Yes
Local
Bus
0
Yes
Local
Bus
0
________________________________________________________________________________
Page - 35 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.9 PCI Built-In Self Test (BIST) Register (PCI Offset 0Fh)
________________________________________________________________________________
Table 9: PCI Built-in Self Test (BIST) Register Description
Field
3:0
5:4
6
7
Description
A value of 0 means the device has passed its test. Non-zero values mean
the device failed. Device specific failure codes can be encoded in the
non-zero value.
Reserved, Device returns 0.
PCI writes a 1 to invoke BIST. Generates an interrupt to local bus. Local
bus resets the bit when BIST is complete. Software should fail device if
BIST is not complete after 2 seconds.
Refer to run time registers for interrupt control/status.
Return 1 if device supports BIST. Return 0 if the device is not BIST
compatible.
Value after
Reset
Read
Write
Yes
Local
Bus
0
Yes
Yes
No
Yes
0
0
Yes
Local
Bus
0
4.2.10 PCI Base Address Register for Memory Access to Runtime Registers (Offset 10h)
________________________________________________________________________________
Table 10: PCI Base Address Register Description
Field
0
2:1
3
6:4
31:7
Description
Memory space indicator. A value of 0 indicates register maps into
Memory space. A value of 1 indicates the register maps into I/O space.
Location of register:
00 - Locate anywhere in 32 bit memory address space
01 - Locate below 1 MByte memory address space
10 - Locate anywhere in 64 bit memory address space
11 - Reserved
Prefetchable. A value of 1 indicates there are no side effects on reads.
Memory Base Address. Memory base address for access to runtime
registers. (Minimum Back Size = 128 bytes.)
Memory Base Address. Memory base address for access to Local
Configuration and Shared Run Time registers. (Minimum Block Size =
128 bytes.)
Read
Write
Value after
Reset
Yes
No
0
Yes
No
0
Yes
Yes
No
No
0
0
Yes
Yes
0
________________________________________________________________________________
Page - 36 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.11 PCI Base Address Register for I/O Access to Runtime Registers(Offset 14h)
________________________________________________________________________________
Table 11: PCI Base Address Register Description
Field
0
1
6:2
31:7
Description
Memory space indicator. A value of 0 indicates register maps into
Memory space. A value of 1 indicates the register maps into I/O space.
Reserved
I/O Base Address. Base Address for I/O access to runtime registers.
(Minimum Block Size = 128 bytes.)
I/O Base Address. Base Address for I/O access to Local Configuration
and Shared Run Time Registers.
(Minimum Block Size = 128 bytes.)
Read
Write
Value after
Reset
Yes
No
1h
Yes
Yes
No
No
0
0
Yes
Yes
0
4.2.12 PCI Base Address Register for Memory Access to Local Address Space 0 (Offset 18h)
________________________________________________________________________________
Table 12: PCI Base Address Register Description
Field
0
2:1
3
31:4
Description
Memory space indicator. A value of 0 indicates register maps into
Memory space. A value of 1 indicates the register maps into I/O space.
(Specified
in Table 23: Local Address Space 0 Range Register
Description, LOC 80h.)
Location of register:
00 - Locate anywhere in 32 bit memory address space
01 - Locate below 1 MByte memory address space
10 - Locate anywhere in 64 bit memory address space
11 - Reserved
(Specified
in Table 23: Local Address Space 0 Range Register
Description, LOC 80h.)
Prefetchable. A value of 1 indicates there are no side effects on reads.
Refer to bit #3 on the Table 23. (Specified in Table 23: Local Address
Space 0 Range Register Description, LOC 80h.)
Memory Base Address. Memory base address for access to local address
space (Used in conjunction with PCI Configuration Resister LOC 80h).
Read
Write
Value after
Reset
Yes
No
0
Yes
No
0
Yes
No
0
Yes
Yes
0
4.2.13 PCI Base Address Register (Offset 1Ch)
________________________________________________________________________________
Table 13: PCI Base Address Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
0
________________________________________________________________________________
Page - 37 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.14 PCI Base Address Register (Offset 20h)
________________________________________________________________________________
Table 14: PCI Base Address Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
0
4.2.15 PCI Base Address Register (Offset 24h)
________________________________________________________________________________
Table 15: PCI Base Address Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
0
4.2.16 PCI Base Address Register (Offset 28h)
________________________________________________________________________________
Table 16: PCI Base Address Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
0
4.2.17 PCI Base Address Register (Offset 2Ch)
________________________________________________________________________________
Table 17: PCI Base Address Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
0
________________________________________________________________________________
Page - 38 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.18 PCI Expansion ROM Base Register (Offset 30h)
________________________________________________________________________________
Table 18: PCI Expansion ROM Base Register Description
Field
0
10:1
31:11
Description
Address Decode Enable. A value of 1 indicates the device accepts
accesses to the expansion ROM address. A value of 0 indicates the
device does not accept accesses to expansion ROM space. Should be set
to 0 if no Expansion ROM.
Reserved
Expansion ROM Base Address (upper 21 bits)
Read
Write
Value after
Reset
Yes
Yes
1
Yes
Yes
No
Yes
0
0
4.2.19 PCI Interrupt Line Register (Offset 3Ch)
________________________________________________________________________________
Table 19: PCI Interrupt Line Register Description
Field
7:0
Description
Read
Interrupt Line Routing Value. Value indicates which input of the system
interrupt controller(s) the device's interrupt line is connected to.
Yes
Value after
Reset
Write
Yes
0
4.2.20 PCI Interrupt Pin Register (Offset 3Dh)
________________________________________________________________________________
Table 20: PCI Interrupt Pin Register Description
Field
7:0
Description
Interrupt Pin register. Indicates which interrupt pin the device uses.
The following values are decoded:
0 = No Interrupt Pin
1
=
INTA#
2
=
INTB#
3
=
INTC#
4
=
INTD#
Read
Write
Yes
Local
Bus
Value after
Reset
1h
________________________________________________________________________________
Page - 39 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.2.21 PCI Min_Gnt Register (Offset 3Eh)
________________________________________________________________________________
Table 21: PCI Min_Gnt Register Description
Field
7:0
Description
Min_Gnt. Used to specify how long a burst period the device needs
assuming a clock rate of 33 MHz. Value is multiple of 1/4 usec
increments.
Read
Write
Yes
Local
Bus
Value after
Reset
0
4.2.22 PCI Max_Lat Register (Offset 3Fh)
________________________________________________________________________________
Table 22: PCI Max_Lat Register Description
Field
7:0
Description
Max_Lat. Used to specify how often the device needs to gain access to
the PCI bus. Value is multiple of 1/4 usec increments.
Read
Write
Yes
Local
Bus
Value after
Reset
0
________________________________________________________________________________
Page - 40 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.3 Local Configuration Registers
4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h)
________________________________________________________________________________
Table 23: Local Address Space 0 Range Register Description
Field
0
2:1
3
31:4
Description
Memory space indicator. A value of 0 indicates Local address space 0
maps into PCI memory space. A value of 1 indicates address space 0
maps into PCI I/O space.
If mapped into memory space, encoding is as follows:
2/1
Meaning
0 0 locate anywhere in 32 bit PCI address space
0 1 locate below 1 Meg in PCI address space
10 locate anywhere in 64 bit PCI address space
1 1 reserved
If mapped into I/O space,
bit 1 must be a 0.
bit 2 is included with bits 3 through 31 to indicate decoding range.
If mapped into memory space, a 1 indicates that reads are pre-fetch able.
If mapped into I/O space, bit is included with bits 2 through 31 to indicate
decoding range.
Specifies which PCI address bits will be used to decode a PCI access to
local bus space 0. Each of the bits corresponds to an address bit. Bit 31
corresponds to Address bit 31. A value of 1 should be written to all bits
that should be included in decode and a 0 to all others (Used in
conjunction with PCI Configuration register 18h). Default is 1 Meg.
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
FFF0000h
4.3.2 Local Address Space 0 Local Base Address (Re-map) Register for PCI to Local Bus (PCI
04h) (LOC 84h)
________________________________________________________________________________
Table 24: Local Address Space 0 Local Base Address (Re-map) Register Description
Field
0
1
3:2
31:4
Description
Space 0 Enable. A 1 value enables Decode of PCI addresses for Direct
Slave access to local space 0. A value of 0 disables Decode.
Not Used
If local space 0 is mapped into memory space, bits are not used.
If mapped into I/O space, bit is included with bits 4 through 31 for remapping.
Re-map of PCI Address to Local Address Space 0 into a Local Address
Space. The bits in this register re-map (replace) the PCI Address bits
used in decode as the Local Address bits.
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
________________________________________________________________________________
Page - 41 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.3.3 Local Register (PCI 08h) (LOC 88h)
________________________________________________________________________________
Table 25: Local Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
000000FFh
4.3.4 Local Register (PCI 0ch) (LOC 8ch)
________________________________________________________________________________
Table 26: Local Register Description
Field
31:0
Description
Reserved
Read
Write
Value after
Reset
Yes
No
000000FFh
4.3.5 Local Expansion ROM Range Register for PCI to Local Bus (PCI 10h) (LOC 90h)
________________________________________________________________________________
Table 27: Local Expansion ROM Range register Description
Field
Description
10:0
31:11
Not used
Specifies which PCI address bits will be used to decode a PCI to local bus
expansion ROM. Each of the bits corresponds to an Address bit 31. A
value of 1 should be written to all bits that should be included in decode
and a 0 to all others (Used in conjunction with PCI Configuration register
30h). Default is 64 KBytes.
Read
Write
Value after
Reset
Yes
Yes
Yes
Yes
0
FFFF00h
4.3.6 Local Expansion ROM Local Base Address (Re-map) register for PCI to Local Bus and
BREQo Control (PCI 14h) (LOC 94h)
________________________________________________________________________________
Table 28: Local Expansion ROM Local Base Address(Re-map) and BREQo register Description
Field
3:0
4
10:5
31:11
Description
Direct Slave BREQo Delay Clocks . (# of local bus clocks in which a
Direct Slave HOLD request is pending and a Local Direct Master access
is in progress and not being granted the bus (HOLDA) before asserting
BREQo. Once asserted, BREQo remains asserted until the PCI9060
receives HOLDA (LSB= 8 clocks)
Local Bus BREQo Enable. A 1 value enables the PCI9060 to assert the
BREQo output.
Not Used
Re-map of PCI Expansion ROM space into a Local address space. The
bits in this register re-map (replace) the PCI address bits used in decode
as the Local address bits.
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
No
Yes
0
0
________________________________________________________________________________
Page - 42 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.3.7 Local Bus Region Descriptor for PCI to Local Accesses Register (PCI 18h) (LOC 98h)
________________________________________________________________________________
Table 29: Local Bus Region Descriptor for PCI to Local Accesses Register Description
Field
1:0
5:2
6
7
8
9
15:10
17:16
21:18
22
23
24
25
26
27
31:28
Description
Memory Space 0 Local Bus Width.
Programmable for the Cx and Jx modes only.
A value of 00 indicates a bus width of 8 bits, a value of 01 indicates a bus
width of 16 bits, a value of 10 or 11 indicates a bus width of 32 bits.
The bus width is forced to 16 bits for the Sx mode
Memory Space 0 Internal Wait States (data to data).
Memory Space 0 Ready Input Enable. A 1 value enables Ready input. A
value of 0 disables the Ready input.
Memory Space 0 Bterm Input Enable. A 1 value enables Bterm input. A
value of 0 disables the Bterm input.
Memory Space 0 Prefetch Disable. If mapped into memory space, a 0
enables read pre-fetching, a value of 1 disables prefetching. If prefetching is disabled, the PCI9060 will disconnect after each memory read.
Expansion ROM Space Prefetch Disable. A 0 enables read pre-fetching, a
value of 1 disables prefetching. If pre-fetching is disabled, the PCI9060
will disconnect after each memory read.
Not Used
Expansion ROM Space Local Bus Width.
Programmable for the Cx and Jx modes only.
A value of 00 indicates a bus width of 8 bits, a value of 01 indicates a bus
width of 16 bits, a value of 10 or 11 indicates a bus width of 32 bits.
The bus width is forced to 16 bits for the Sx mode.
Expansion ROM Space Internal Wait States (data to data).
Expansion ROM Space Ready Input Enable. A 1 value enables Ready
input. A value of 0 disables the Ready input.
Expansion ROM Space Bterm Input Enable. A 1 value enables Bterm
input. A value of 0 disables the Bterm input.
Memory Space 0 Burst Enable. A 1 value enables bursting. A value of 0
disables bursting.
Not Used
Expansion ROM Space Burst Enable. A 1 value enables bursting. A value
of 0 disables bursting.
Direct Slave PCI write mode. A 0 indicates that the PCI9060 should
disconnect when the Direct Slave write FIFO is full. A 1 indicates that the
PCI9060 should de-assert TRDY when the write FIFO is full.
PCI Target Retry Delay Clocks. Contains the value (multiplied by 8) of the
# of PCI bus clocks after receiving a PCI-Local read or write access and
not successfully completing a transfer. Only pertains to Direct Slave
writes when bit 27 is set to 1.
Value after
Reset
Read
Write
Yes
Yes
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Sx mode 01
Jx mode 11
Cx mode 11
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Sx mode 01
Jx mode 11
Cx mode 11
4
(32 clocks)
________________________________________________________________________________
Page - 43 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.3.8 Local Range register for Direct Master to PCI (PCI 1Ch) (LOC 9Ch)
________________________________________________________________________________
Table 30: Local Range register for Direct Master to PCI Description
Field
Description
15:0
31:16
Not Used (64KByte increments)
Specifies which Local address bits will be used to decode a Local to PCI
bus access. Each of the bits corresponds to an address bit. Bit 31
corresponds to Address bit 31. A value of 1 should be written to all bits
that should be included in decode and a 0 to all others.
Read
Write
Value after
Reset
Yes
Yes
No
Yes
0
0
4.3.9 Local Bus Base Address register for Direct Master to PCI Memory (PCI 20h) (LOC A0h)
________________________________________________________________________________
Table 31: Local Bus Base Address register for Direct Master to PCI Memory
Field
Description
15:0
31:16
Not Used.
Assigns a value to the bits which will be used to decode a Local to PCI
memory access.
Read
Write
Value after
Reset
Yes
Yes
No
Yes
0
0
4.3.10 Local Base Address for Direct Master to PCI IO/CFG Register (PCI 24h) (LOC A4h)
________________________________________________________________________________
Table 32: Local Base Address for Direct Master to PCI IO/CFG Register
Field
Description
15:0
31:16
Not Used
Assigns a value to the bits which will be used to decode a Local to PCI
I/O or configuration access
Read
Write
Value after
Reset
Yes
Yes
No
Yes
0
0
________________________________________________________________________________
Page - 44 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.3.11 PCI Base Address (Re-map) register for Direct Master to PCI (PCI 28h) (LOC A8h)
________________________________________________________________________________
Table 33: PCI Base Address (Re-map) register for Direct Master to PCI Description
Field
0
1
2
3
4
7:5
15:8
31:16
Description
Direct Master Memory Access Enable. A 1 value enables decode of Direct
Master Memory accesses. A value of 0 disables decode of Direct Master
Memory accesses.
Direct Master I/O Access Enable. A 1 value enables decode of Direct
Master I/O accesses. A value of 0 disables decode of Direct Master I/O
accesses.
LOCK Input Enable. A 1 value enables LOCK input, enabling PCI locked
sequences. A value of 0 disables the LOCK input.
Direct Master Read Prefetch Size control.
If set to a value of 0, the PCI9060 continues to prefetch read data until
the Direct Master access is finished. This may result in an additional 4 unneeded Lwords being pre-fetched from the PCI bus.
If set to a value of 1 the PCI9060 reads up to 4 Lwords from the PCI bus
for each Direct Master burst read access. This mode must not be used
for direct master burst reads that exceed 4 Lwords.
Direct Master PCI read mode. A value of 0 indicates that the PCI9060
should release the PCI bus when the read FIFO becomes full. A value of
1 indicates that the PCI9060 should keep the PCI bus and de-assert IRDY
when the read FIFO becomes full.
Programmable Almost Full Flag. When the number of entries in the 8
deep direct master write FIFO exceed this value, the output pin DMPAF#
is asserted low.
Not Used.
Re-map of Local to PCI space into a PCI address space. The bits in this
register re-map (replace) the Local address bits used in decode as the
PCI address bits.
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
No
Yes
0
0
4.3.12 PCI Configuration Address Register for Direct Master to PCI IO/CFG (PCI 2Ch) (LOC
ACh)
________________________________________________________________________________
Table 34: PCI Configuration Address Register for Direct Master to PCI IO/CFG
Field
Description
1:0
7:2
10:8
15:11
23:16
30:24
31
Configuration Type. 00=Type 0 01=Type 1
Register Number
Function Number
Device Number
Bus Number
Reserved
Configuration Enable. A value of 1 allows Local to PCI I/O accesses to be
converted to a PCI configuration cycle. The Parameters in this table are
used to generate the PCI configuration address.
Read
Write
Value after
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0
0
0
0
0
0
0
________________________________________________________________________________
Page - 45 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.4 Shared Runtime Registers
4.4.1 Mailbox Register 0 (PCI 40h) (LOC C0h)
________________________________________________________________________________
Table 35: Mailbox Register 0 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
4.4.2 Mailbox Register 1 (PCI 44h) (LOC C4h)
________________________________________________________________________________
Table 36: Mailbox Register 1 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
4.4.3 Mailbox Register 2 (PCI 48h) (LOC C8h)
________________________________________________________________________________
Table 37: Mailbox Register 2 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
4.4.4 Mailbox Register 3 (PCI 4Ch) (LOC CCh)
________________________________________________________________________________
Table 38: Mailbox Register 3 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
________________________________________________________________________________
Page - 46 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.4.5 Mailbox Register 4 (PCI 50h) (LOC D0h)
________________________________________________________________________________
Table 39: Mailbox Register 4 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
4.4.6 Mailbox Register 5 (PCI 54h) (LOC D4h)
________________________________________________________________________________
Table 40: Mailbox Register 5 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
4.4.7 Mailbox Register 6 (PCI 58h) (LOC D8h)
________________________________________________________________________________
Table 41: Mailbox Register 6 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
4.4.8 Mailbox Register 7 (PCI 5Ch) (LOC DCh)
________________________________________________________________________________
Table 42: Mailbox Register 7 Description
Field
31:0
Description
32 bit mailbox register
Read
Write
Value after
Reset
Yes
Yes
0
________________________________________________________________________________
Page - 47 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.4.9 PCI to Local Doorbell Register (PCI 60h) (LOC E0h)
________________________________________________________________________________
Table 43: PCI to Local Doorbell Register Description
Field
31:0
Description
Doorbell register. A PCI master can write to this register and it will
generate a local interrupt to the local processor. The local processor
can then read this register to determine which doorbell bit was
asserted. The PCI master sets a doorbell by writing a 1 to a
particular bit. The local processor can clear a doorbell bit by writing
a 1 to that bit position.
Read
Write
Value after
Reset
Yes
Yes
0
4.4.10 Local to PCI Doorbell Register (PCI 64h) (LOC E4h)
________________________________________________________________________________
Table 44: Local to PCI Doorbell Register Description
Field
31:0
Description
Doorbell register. The local processor can write to this register and it
will generate a PCI interrupt. A PCI master can then read this
register to determine which doorbell bit was asserted. The local
processor sets a doorbell by writing a 1 to a particular bit. The PCI
master can clear a doorbell bit by writing a 1 to that bit position.
Read
Write
Value after
Reset
Yes
Yes
0
________________________________________________________________________________
Page - 48 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.4.11 Interrupt Control/Status (PCI 68h) (LOC E8h)
________________________________________________________________________________
Table 45: Interrupt Control/Status
Field
0
1
2
7:3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
31:28
Description
Enable Local bus LSERR#. A value of 1 will enable the PCI9060 to assert LSERR#
interrupt output when the PCI bus Target Abort or Master Abort status bit is set in the
PCI Status Configuration Register.
Enable Local bus LSERR# when a PCI parity error occurs during a PCI9060 Master
Transfer or a PCI9060 Slave access.
Generate PCI bus SERR#. When this bit is 0, writing a 1 generates a PCI bus SERR#.
Not Used
PCI interrupt enable. A value of 1 will enable PCI interrupts .
PCI doorbell interrupt enable. A value of 1 will enable doorbell interrupts . Used in
conjunction with PCI interrupt enable. Clearing the doorbell interrupt bits causing the
interrupt will clear the interrupt.
PCI Abort interrupt enable. A value of 1 will enable a master abort or master detect of a
target abort to generate a PCI interrupt . Used in conjunction with PCI interrupt enable.
Clearing the abort status bits will clear the PCI interrupt.
PCI local interrupt enable. A value of 1 will enable a local interrupt input to generate a
PCI interrupt . Use in conjunction with PCI interrupt enable. Clearing the local bus
cause of the interrupt will clear the interrupt.
Retry Abort Enable. A value of 1 will enable the PCI9060 to treat 256 Master
consecutive retries to a Target as a Target Abort. A value of 0 will enable the PCI9060
to attempt Master Retries indefinitely.
A value of 1 indicates that the PCI doorbell interrupt is active.
A value of 1 indicates that the PCI abort interrupt is active.
A value of 1 indicates that the local interrupt input is active.
Local interrupt output enable. A value of 1 will enable Local interrupt output .
Local doorbell interrupt enable. A value of 1 will enable doorbell interrupts . Used in
conjunction with Local interrupt enable. Clearing the Local doorbell interrupt bits
causing the interrupt will clear the interrupt.
Local DMA channel 0 interrupt enable. A value of 1 will enable DMA channel 0
interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA status bits
will clear the interrupt.
Local DMA channel 1 interrupt enable. A value of 1 will enable DMA channel 1
interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA status bits
will clear the interrupt.
A value of 1 indicates that the Local doorbell interrupt is active.
A value of 1 indicates that the DMA ch 0 interrupt is active.
A value of 1 indicates that the DMA ch 1 interrupt is active.
A value of 1 indicates that the BIST interrupt is active.
The BIST (built in self test) interrupt is generated by writing a 1 to bit 6 of the PCI
Configuration BIST register. Clearing bit 6 clears the interrupt. Refer to the BIST
register for a description of self test.
A value of 0 indicates that a Direct Master was the bus master during a Master or
Target abort.
A value of 0 indicates that DMA CH 0 was the bus master during a Master or Target
abort.
A value of 0 indicates that a DMA CH 1 was the bus master during a Master or Target
abort.
A value of 0 indicates that a Target Abort was generated by the PCI9060 after 256
consecutive Master retries to a Target.
Not Used
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
0
0
1
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
0
0
0
1
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
No
No
No
No
0
0
0
0
Yes
No
0
Yes
No
0
Yes
No
0
Yes
Yes
0
Yes
No
0
________________________________________________________________________________
Page - 49 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.4.12 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI
6Ch) (LOC ECh)
________________________________________________________________________________
Table 46: EEPROM Control, PCI Command Codes, User I/O Control, Init Control
Field
3:0
7:4
11:8
15:12
16
17
23:18
24
Description
PCI Read Command Code for DMA
PCI Write Command Code for DMA
PCI Memory Read Command Code for Direct Master
PCI Memory Write Command Code for Direct Master
General Purpose Output. A value of 1 will cause the USERO output to go
high . A value of 0 will cause the output to go low.
General Purpose Input. A value of 1 indicates that USERI input pin is
high. A value of 0 indicates that USERI pin is low.
Not Used
EEPROM clock for Local or PCI bus reads or writes to EEPROM.
Toggling this bit generates an EEPROM clock. Refer to the
Read
Write
Value after
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1110
0111
0110
0111
1h
Yes
No
--
Yes
Yes
No
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
No
--
Yes
Yes
No
Yes
0
0
Yes
Yes
0
Yes
Yes
0
manufacturer’s data sheet for the particular EEPROM being used.
25
26
27
28
29
30
31
EEPROM chip select. For Local or PCI bus reads or writes to EEPROM,
setting this bit to a 1 provides the EEPROM chip select.
Write bit to EEPROM. For writes, this output bit is the input to the
EEPROM. It is clocked into the EEPROM by the EEPROM clock.
Read EEPROM data bit. For reads, this input bit is the output of the
EEPROM. It is clocked out of the EEPROM by the EEPROM clock.
EEPROM present. A 1 in this bit indicates that an EEPROM is present.
Reload Configuration Registers. When this bit is 0, writing a 1 causes the
PCI9060 to reload the PCI configuration registers from EEPROM.
PCI Adapter Software Reset. A value of 1 written to this bit will hold the
local bus logic in the PCI9060 reset and LRESETO# asserted. The
contents of the PCI configuration registers and Shared Run Time registers
will not be reset. Software Reset can only be cleared from the PCI bus.
Local Init Status 1 = local init done. Responses to PCI accesses will be
RETRYs until this bit is set. While Input NB# is asserted low this bit will
be forced to 1.
________________________________________________________________________________
Page - 50 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.5 Local DMA Registers
4.5.1 DMA Channel 0 Mode Register (LOC 100h)
________________________________________________________________________________
Table 47: DMA Channel 0 Mode Register Description
Field
1:0
5:2
6
7
8
9
10
11
12
31:13
Description
Local DMA Bus Width.
Programmable for the Cx and Jx modes only.
A value of 00 indicates a DMA bus width of 8 bits, a value of 01 indicates
a DMA bus width of 16 bits, a value of 11 indicates a DMA bus width of 32
bits(or 10 for 32 bit aligned only).
The bus width is forced to 16 bits for the Sx mode.
Internal Wait States (data to data).
Ready Input Enable. A 1 value enables Ready input. A value of 0 disables
the Ready input.
Bterm Input Enable. A 1 value enables Bterm input. A value of 0 disables
the Bterm input.
Burst Enable. A 1 value enables bursting. A value of 0 disables bursting.
Chaining. A 0 value indicates non-chaining mode enabled. A 1 value
indicates chaining mode enabled. For chaining mode, Descriptor must
be in memory rather than the registers in the Tables 48, 49, and 50.
Done Interrupt Enable. A 1 value enables interrupt when done. A 0 value
disables interrupt when done.
Local Addressing Mode. A 1 value indicates local address LA [31:2] to be
held constant. A 0 value indicates local address is incremented.
Demand Mode. A value of 1 causes the DMA controller to operate in
demand mode. In demand mode the DMA controller transfers data when
its DREQ# input is asserted. It asserts DACK# to indicate that the current
local bus transfer is in response to the DREQ# input. The DMA controller
transfers Lwords (32bits) of data. This may result in multiple transfers for
an 8 or 16 bit bus.
Reserved
Value after
Reset
Read
Write
Yes
Yes
Sx mode 01
Jx mode 11
Cx mode 11
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
No
0
4.5.2 DMA Channel 0 PCI Address Register (LOC 104h)
________________________________________________________________________________
Table 48: DMA Channel 0 PCI Address Register Description
Field
31:0
Description
PCI Address Register. This indicates where in the PCI memory space the
DMA transfers (reads or writes) will start from.
Read
Write
Value after
Reset
Yes
Yes
0
________________________________________________________________________________
Page - 51 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.5.3 DMA Channel 0 Local Address Register (LOC 108h)
________________________________________________________________________________
Table 49: DMA Channel 0 Local Address Register Description
Field
31:0
Description
Local Address Register. This indicates where in the local memory
space the DMA transfers (reads or writes) will start from.
Read
Write
Value after
Reset
Yes
Yes
0
4.5.4 DMA Channel 0 Transfer Size (Bytes) Register (LOC 10Ch)
________________________________________________________________________________
Table 50: DMA Channel 0 Transfer Size (Bytes) Register Description
Field
22:0
31:23
Description
DMA Transfer Size (Bytes). Indicates number of bytes to be
transferred during DMA operation.
Not Used
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
4.5.5 DMA Channel 0 Descriptor Pointer Register (LOC 110h)
________________________________________________________________________________
Table 51: DMA Channel 0 Descriptor Pointer Register Description
Field
0
1
2
3
31:4
Description
Reserved
End of Chain. A 1 value indicates end of chain. A 0 value indicates not
end of chain descriptor. Note: 0 chaining mode implies that there is no
chain (Same as Non-Chaining Mode.)
Interrupt after Terminal Count. A 1 value causes an interrupt to be
generated after the terminal count for this descriptor is reached. A 0
value disables interrupts from being generated.
Direction of transfer. A 1 value indicates transfers from local bus to PCI
bus. A 0 value indicates transfers from PCI bus to local bus.
Next Descriptor Address. Quad word aligned(Bit[3:0] = 0000).
Read
Write
Value after
Reset
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
________________________________________________________________________________
Page - 52 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.5.6 DMA Channel 1 Mode Register (LOC 114h)
________________________________________________________________________________
Table 52: DMA Channel 1 Mode Register Description
Field
1:0
5:2
6
7
8
9
10
11
12
31:13
Description
Local Bus Width.
Programmable for the Cx and Jx modes only. A value of 00 indicates a
bus width of 8 bits, a value of 01 indicates a bus width of 16 bits, a value
of 11 indicates a bus width of 32 bits(or 10 for 32 bit aligned only).
The bus width is forced to 16 bits for the Sx mode.
Internal Wait States (data to data).
Ready Input Enable. A 1 value enables Ready input. A value of 0 disables
the Ready input.
Bterm Input Enable. A 1 value enables Bterm input. A value of 0 disables
the Bterm input.
Local Burst Enable. A 1 value enables Local bursting. A value of 0
disables Local bursting.
Chaining. A 1 value indicates chaining mode enabled. A 0 value indicates
non-chaining mode enabled.
Done Interrupt Enable. A 1 value enables interrupt when done. A 0 value
disables interrupt when done.
Local Addressing Mode. A 1 value indicates local address LA[31:2] to be
held constant. A 0 value indicates local address is incremented.
Demand Mode. A value of 1 causes the DMA controller to operate in
demand mode. In demand mode the DMA controller transfers data when
its DREQ# input is asserted. It asserts DACK# to indicate that the current
local bus transfer is in response to the DREQ# input. The DMA controller
transfers Lwords (32bits) of data . This may result in multiple transfers for
an 8 or 16 bit bus.
Reserved
Value after
Reset
Read
Write
Yes
Yes
Sx mode 01
Jx mode 11
Cx mode 11
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
No
0
4.5.7 DMA Channel 1 PCI Data Address Register (LOC 118h)
________________________________________________________________________________
Table 53: DMA Channel 1 PCI Data Address Register Description
Field
31:0
Description
PCI Data Address Register. This indicates where in the PCI memory
space the DMA transfers (reads or writes) will start from.
Read
Write
Value after
Reset
Yes
Yes
0
________________________________________________________________________________
Page - 53 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.5.8 DMA Channel 1 Local Data Address Register (LOC 11Ch)
________________________________________________________________________________
Table 54: DMA Channel 1 Local Data Address Register Description
Field
31:0
Description
Local Data Address Register. This indicates where in the local memory
space the DMA transfers (reads or writes) will start from.
Read
Write
Value after
Reset
Yes
Yes
0
4.5.9 DMA Channel 1 Transfer Size (Bytes) Register (LOC 120h)
________________________________________________________________________________
Table 55: DMA Channel 1 Transfer Size (Bytes) Register Description
Field
22:0
31:23
Description
DMA Transfer Size (Bytes). Indicates number of bytes to be transferred
during DMA operation.
Not Used
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
4.5.10 DMA Channel 1 Descriptor Pointer Register (LOC 124h)
________________________________________________________________________________
Table 56: DMA Channel 1 Descriptor Pointer Register Description
Field
0
1
2
3
31:4
Description
Reserved
End of Chain. A 1 value indicates end of chain. A 0 value indicates not
end of chain descriptor.
Interrupt after Terminal Count. A 1 value causes an interrupt to be
generated after the terminal count for this descriptor is reached. A 0
value disables interrupts from being generated.
Direction of transfer. A 1 value indicates transfers from local bus to PCI
bus. A 0 value indicates transfers from PCI bus to local bus.
Next Descriptor Address. Quad word aligned.
Read
Write
Value after
Reset
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
________________________________________________________________________________
Page - 54 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.5.11 DMA Command/Status Register (LOC 128h)
________________________________________________________________________________
Table 57: DMA Command/Status Register Description
Field
0
1
2
3
4
7:5
8
9
10
11
12
15:13
31:16
Description
Channel 0 Enable. A 1 value enables the channel to transfer data. A 0
value disables the channel from starting a DMA transfer and if in the
process of transferring data suspend transfer ( Pause).
Channel 0 Control. Writing a 1 to this bit causes the channel to start
transferring data if the channel is enabled.
Channel 0 Control. Writing a 1 to this bit causes the channel to abort the
current transfer. The channel enable bit must be cleared. The channel
complete bit is set when the abort has completed.
Writing a 1 to this bit clears channel 0 interrupts
Channel 0 Done. A 1 value indicates this channels transfer is complete. A
0 value indicates the channel transfer is not complete.
User Defined
Channel 1 Enable. A 1 value enables the channel to transfer data. A 0
value disables the channel from starting a DMA transfer and if in the
process of transferring data suspend transfer ( Pause).
Channel 1 Control. Writing a 1 to this bit causes the channel to start
transferring data if the channel is enabled.
Channel 1 Control. Writing a 1 to this bit causes the channel to abort the
current transfer. The channel enable bit must cleared. The channel
complete bit is set when the abort has completed.
Writing a 1 to this bit clears channel 1 interrupts
Channel 1 Done. A 1 value indicates this channel's transfer is complete. A
0 value indicates the channel transfer is not complete.
User Defined
Not Used
Read
Write
Value after
Reset
Yes
Yes
0
No
Yes
0
No
Yes
0
No
Yes
Yes
No
0
1
Yes
Yes
Yes
Yes
0
0
No
Yes
0
No
Yes
0
No
Yes
Yes
No
0
1
Yes
Yes
Yes
No
0
0
4.5.12 DMA Arbitration Register 0 (LOC 12Ch)
________________________________________________________________________________
Table 58: DMA Arbitration Register 0 Description
Field
7:0
15:8
16
17
18
20:19
31:21
Description
Local Bus Latency Timer. Number of local bus clock cycles before
deasserting HOLD and releasing the local bus.
Local Bus Pause Timer. Number of local bus clock cycles before
reasserting HOLD after releasing the local bus.
Local Bus Latency Timer Enable. A 1 value enables the latency timer.
Local Bus Pause Timer Enable. A 1 value enables the pause timer (Used
for DMA only.)
Local Bus BREQ Enable. A 1 value enables the local bus BREQ input.
When the BREQ input is active, the PCI9060 de-asserts HOLD and
releases the local bus.
DMA Channel Priority. A value of 00 indicates a rotational priority
scheme. A value of 01 indicates channel 0 has priority. A value of 10
indicates channel 1 has priority. A 11 value is reserved
Not Used
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
Yes
Yes
0
0
Yes
Yes
0
Yes
Yes
0
Yes
No
--
________________________________________________________________________________
Page - 55 Version 1.2
Section B
PCI9060
SECTION 4
REGISTERS
________________________________________________________________________________
4.5.13 DMA Arbitration Register 1 (LOC 130h)
________________________________________________________________________________
Table 59: DMA Arbitration Register 1 Description
Field
3:0
7:4
11:8
15:12
18:16
19
22:20
23
26:24
27
30:28
31
Description
DMA Channel 0 PCI to Local Almost Full (C0PLAF):
# of Full Entries (minus 1) in FIFO before Requesting Local Bus for
Writes.
(C0PLAF+1) + (C0PLAE+1) should be <= FIFO Depth of 16
DMA Channel 0 Local to PCI Almost Empty (C0LPAE):
# of Empty Entries (minus 1) in FIFO before Requesting Local Bus for
Reads.
(C0LPAF+1) + (C0LPAE+1) should be <= FIFO depth of 16
DMA Channel 0 Local to PCI Almost Full (C0LPAF):
# of Full Entries (minus 1) in FIFO before Requesting PCI Bus for Writes.
DMA Channel 0 PCI to Local Almost Empty (C0PLAE):
# of Empty Entries (minus 1) in FIFO before Requesting PCI Bus for
Reads.
DMA Channel 1 PCI to Local Almost Full (C1PLAF):
# of Full Entries (minus 1) in FIFO before Requesting Local Bus for
Writes .
(C1PLAF+1) + (C1PLAE+1) should be <= FIFO depth of 8
Reserved
DMA Channel 1 Local to PCI Almost Empty (C1LPAE):
# of Empty Entries (minus 1) in FIFO before Requesting Local Bus for
Reads.
(C1PLAF+1) + (C1PLAE+1) should be <= FIFO depth of 8
Reserved
DMA Channel 1 Local to PCI Almost Full (C1LPAF):
# of Full Entries (minus 1) in FIFO before Requesting PCI Bus for Writes.
Reserved
DMA Channel 1 PCI to Local Almost Empty (C1PLAE):
# of Empty Entries (minus 1) in FIFO before Requesting PCI Bus for
Reads.
Reserved
Read
Write
Value after
Reset
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
0
Yes
Yes
No
Yes
0
0
Yes
Yes
No
Yes
0
0
Yes
Yes
No
Yes
0
0
Yes
No
0
________________________________________________________________________________
Page - 56 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
5. SECTION 5 - PIN DESCRIPTION
5.1 Pin Summary
The following tables describe the PCI9060 pins. The pins in the following tables are common to all three local bus
modes of operation (i.e. Cx mode, Jx mode, and Sx mode):
PCI System Bus Interface Pin Description
Local Bus Mode and Processor Independent Interface Pin Description
EEPROM interface Pin Description
Power and Ground Pin Description
The following tables correspond to the local bus mode of the PCI9060:
Cx Bus Mode Interface Pin Description (i960Cx and Hx processors)
Jx Bus Mode Interface Pin Description (i960Jx and Kx processors)
Sx Bus Mode Interface Pin Description (i960Sx processor)
Unspecified pins are no connects.
The following abbreviations are used:
I/O I
O TS OC TP STS DTS-
Input and Output Pin
Input Pin Only
Output Pin Only
Tri-state Pin
Open Collector Pin
Totem Pole Pin
Sustained Tri-state Pin, driven high for 1 CLK before float
Driven Tri-state Pin, driven high for 1/2 CLK before float
All local bus inputs (Pin Type I) are internally connected to Vcc through a 10k ohm pull-up resistor.
All Local tristate I/O pins should have pull-ups.
Design Notes: PULL up/down ( use 3k - 10kΩ
Ω ).
For PCI Pins, DO NOT pull up/down any pins unless you are using PCI9060 for an embedded design.
Please refer to “PCI Local Bus Specification”, Revision 2.1, pg123.
________________________________________________________________________________
Page - 57 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
Table 60 Power and Ground Pin Description
Symbol
TEST
Signal Name
Test
VDD
Power
VSS
Ground
Total
Pins
1
Pin
Type
I
Pin
Number
49
12
I
1,38,53,
60,68,83,
105,124,
144,157,
167,184
22,37,45,
52,59,67,
75,82,90,
98,104,
114,123,
134,143,
156,166,
183,193,
208
20
I
Function
Test Pin. Pull high for test,
low for normal
operation. When TEST is pulled high, all outputs
except USERO (pin 27) are placed in tri-state.
USERO provides a NAND-TREE output when TEST
is pulled high.
Five volt power supply pins.
Liberal .01 uF to .1 uF decoupling capacitors should
be placed near the PCI9060.
Ground pins.
Table 61 EEPROM Interface Pin Description
Total
Pins
1
Pin
Type
I
Pin
Number
170
1 MHz Clock
EEPROM
Chip
Select
1
1
175
176
EEDI
EEPROM Data IN
1
172
Write data to EEPROM
EEDO
1
171
Read data from EEPROM
EESK
EEPROM
Data
OUT
Serial Data Clock
I
O
TP
6 mA
O
TP
6 mA
I
Function
When set to 0 EE1MC will be used to clock the
EEPROM. When set to 1 an internally generated
clock will be used to clock the EEPROM. The clock
is generated from the PCI Clock.
Optional EEPROM clock source
EEPROM chip select
173
EEPROM Clock
SHORT#
Load Short
1
O
TP
6 mA
I
174
When active low only five 32-bit registers are
loaded from the EEPROM. When active high all
local configuration registers are also loaded from
EEPROM.
Symbol
CLKSEL
Signal Name
Clock Select
EE1MC
EECS
1
________________________________________________________________________________
Page - 58 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
Table 62 PCI System Bus Interface Pin Description
Symbol
Signal Name
Total
Pins
32
Pin
Type
I/O
TS
6mA
AD[31:0]
Address and Data
C/BE[3:0]#
Pin
Number
32-36,
39-44,4647, 7681,84-89,
91-97
Bus
Command
and Byte Enables
4
I/O
TS
6mA
70,71,72,
73
CLK
Clock
1
I
54
DEVSEL#
Device Select
1
I/O
STS
6mA
64
FRAME#
Cycle Frame
1
I/O
STS
6mA
57
GNT#
Grant
1
I
51
IDSEL
1
I
63
INTA#
Initialization
Device Select
Interrupt A
1
55
IRDY#
Initiator Ready
1
LOCK#
Lock
1
PAR
Parity
1
O
OC
6mA
I/O
STS
6mA
I/O
STS
6mA
I/O
TS
6mA
PERR#
Parity Error
1
I/O
STS
6mA
65
61
69
74
Function
These are multiplexed on the same PCI pins. A bus
transaction consists of an address phase followed by
one or more data phases. The PCI9060 supports
both read and write bursts.
These are multiplexed on the same PCI pins. During
the address phase of a transaction C/BE[3::0]# define
the bus command.
During the data phase
C/BE[3::0]# are used as Byte Enables. Refer to PCI
spec for further detail if needed.
This provides timing for all transactions on PCI and is
an input to every PCI device. PCI operates up to
33MHz.
When a device has decoded its address as the target
of the current access, the device asserts DEVSEL#.
As an input, DEVSEL# indicates whether any device
on the bus has been selected.
This is driven by the current master to indicate the
beginning and duration of an access. FRAME# is
asserted to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue.
When FRAME# is deasserted, the transaction is in
the final data phase.
This indicates to the agent that access to the bus has
been granted. Every master has its own REQ# and
GNT#.
This is used as a chip select during configuration read
and write transactions.
This is used to request an interrupt.
This indicates the initiating agent's (bus master's)
ability to complete the current data phase of the
transaction.
Lock indicates an atomic operation that may require
multiple transactions to complete.
This is even parity across AD[31::00] and C/BE[3::0]#.
Parity generation is required by all PCI agents. PAR
is stable and valid one clock after the address phase.
For data phases PAR is stable and valid one clock
after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction. Once
PAR is valid, it remains valid until one clock after the
completion of the current data phase.
This is only the reporting of data parity errors during
all PCI transactions except a Special Cycle.
________________________________________________________________________________
Page - 59 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
REQ#
Request
1
O
6mA
50
RST#
Reset
1
I
56
SERR#
Systems Error
1
66
STOP#
Stop
1
TRDY#
Target Ready
1
O
OC
6mA
I/O
STS
6mA
I/O
STS
6mA
62
58
This indicates to the arbiter that this agent desires use
of the bus. Every master has its own GNT# and
REQ#.
This is used to bring PCI-specific registers,
sequencers, and signals to a consistent state.
This is for reporting address parity errors, data parity
errors on the Special Cycle command, or any other
system error where the result will be catastrophic.
This indicates the current target is requesting the
master to stop the current transaction.
This indicates the target agent's (selected device's)
ability to complete the current data phase of the
transaction.
________________________________________________________________________________
Page - 60 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
Table 63 Local Bus Mode and Processor Independent Interface Pin Description
Symbol
ADMODE
Total
Pins
1
Pin
Type
I
Pin
Number
1
I
169
BREQ
Signal Name
Address Decode
Mode
Bus Request
BREQo
Bus Request Out
1
O
TP
6 mA
21
BTERMo#
Burst
Out
Terminate
1
28
DACK[1:0]#
DMA
outputs
request
2
O
DTS
6mA
O
TP
6 mA
DMPAF#
Direct Master
Programmable
almost full
Data Parity
1
DREQ[1:0]#
DMA
inputs
request
2
I
24,29
LDSHOLD
Direct
Slave
HOLD Request
1
165
LINTi#
LINTo#
Local Interrupt In
Local Interrupt Out
1
1
O
TP
6mA
I
O
TP
6 mA
LRESETi#
Local Reset In
1
DP[3:0]
4
O
TP
6 mA
I/O
TS
6 mA
I
20
25,30
8
12,13,14,
15
151
152
150
Function
Determines how S[2:0] are used to access the
PCI9060 internal registers
BREQ is asserted to indicate that a local bus master
requires the bus. If enabled through the PCI9060
configuration registers, the PCI9060 will release the
bus during a DMA transfer if this signal is asserted.
BREQo is asserted to indicate that the PCI9060
requires the bus to perform a direct PCI to local bus
access while a Direct Master access is pending on
the Local bus. It can be used with external logic to
generate backoff to a Local bus Master.
Its
operational parameters are set up through PCI9060
configuration registers.
BTERMo# is asserted along with READYo# to
request that a burst be broken up and that a new
address cycle be started. (Abort only)
When a channel is programmed through the
configuration registers to operate in demand mode,
its DACK output indicates a DMA transfer is being
executed. DACK0# corresponds to PCI9060 DMA
channel 0 and DACK1# to DMA channel 1.
Direct Master write FIFO almost full status output.
Programmable through a configuration register.
Parity is even for each of up to 4 byte lanes on the
local bus. Parity is checked for writes to the
PCI9060 or reads by the PCI9060. Parity is
generated for reads from the PCI9060 or writes by
the PCI9060.
When a channel is programmed through the
configuration registers to operate in demand mode,
its DREQ input serves as a DMA request. DREQ0#
corresponds to PCI9060 DMA channel 0 and
DREQ1# to DMA channel 1.
Asserted coincident with LHOLD to indicate that the
PCI9060 is requesting use of the Local Bus in order
to perform a Direct Slave transfer.
When asserted low causes a PCI interrupt.
The interrupt output is a synchronous level output.
The output will remain asserted as long as an
interrupt condition exists. If an edge level interrupt is
required, disabling and then enabling local interrupts
though the interrupt/control status register will create
an edge if an interrupt condition still exists or a new
interrupt condition occurs.
This pin resets the local bus portion of the PCI9060
chip and causes the local reset output to be
asserted.
________________________________________________________________________________
Page - 61 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
LSERR#
System Error
1
O
TP
6mA
23
MODE[1:0]
Bus Mode
2
I
9,10
NB#
No Local
Initialization
Bus
1
I
26
PCHK#
Data Parity Check
1
O
TP
6 mA
16
S[2:0]
Address Select
3
I
17,18,19
USERI
User Input
1
I
31
USERO
User Output
1
27
WAITO#
Wait Out
1
O
TP
24 mA
O
TS
6 mA
149
The LSERR# interrupt output is a synchronous level
output. LSERR# interrupt output is asserted when
the PCI bus Target Abort or Master Abort status bit
is set in the PCI Status Configuration Register. If an
edge level interrupt is required, disabling and then
enabling
LSERR#
interrupts
though
the
interrupt/control status will create an edge if an
interrupt condition still exists or a new interrupt
condition occurs.
Selects the bus operation mode of the PCI9060:
bit 1 bit 0 Bus Mode
0
0
C
0
1
J
1
0
S
1
1
Reserved
Pull up if PCI9060 Local_Init_Done_Bit will be set
by local processor. Otherwise, this pin must be 0 in
order to work properly.
See Note 1. at the bottom.
Parity is checked for writes to the PCI9060 or reads
by the PCI9060. Parity is checked for each byte lane
with its byte enable asserted. PCHK# is asserted in
the clock cycle following the data being checked if a
parity error is detected.
If ADMODE is high, internal PCI9060 registers are
selected when A[31:29] match S[2..0].
If ADMODE is low, the internal PCI9060 registers
are selected when S0 is asserted low.
This is a general purpose input that can be read
from the PCI9060 configuration registers.
This is a general purpose output controlled from the
PCI9060 configuration registers.
This output indicates the PCI9060 programmable
wait state generator status. WAITO# is asserted
when wait states are being caused by the internal
wait state generator. It can be thought of as an
output providing ready out status.
Note 1:
When pulled down, this pin externally forces Local Init Done bit in the Init Control Register to 1. If NB# is pulled
up, the Init Done bit is programmable through local bus configuration accesses. The PCI9060 will issue RETRYs to all
PCI accesses until the Local Init Done bit is set. If this bit is not going to be set by a local processor, then NB# must be
tied low. Please refer to Section 3.1 on page 10 for further information.
________________________________________________________________________________
Page - 62 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
Table 64 Cx Bus Mode Interface Pin Description
Symbol
Signal Name
Total
Pins
1
Pin
Type
I/O
TS
24 mA
I/O
TS
6 mA
I
Pin
Number
154
O
TS
24 mA
O
TS
24 mA
145
I/O
TS
24 mA
I
137
136,135,
133-125,
122-115,
113-106,
103-101
177-182,
185-192,
194-207,
2-5
ADS#
Address Strobe
BLAST#
Burst Last
1
BTERM#
Burst Terminate
1
DEN#
Data Enable
1
DT/R#
Data
Transmit/Receive
1
LW/R#
Write/Read
1
LLOCK#
Bus Lock
1
LA[31:2]
Address Bus
30
I/O
TS
6 mA
LD[31:0]
Data Bus
32
I/O
TS
6 mA
155
146
138
153
Function
Address strobe indicates valid address and the start
of a new bus access. ADS# is asserted for the first
clock of a bus access.
BLAST# is a signal driven by the current local bus
master to indicate the last transfer in a bus access.
The i960Cx processor bursts up to 4 Lwords. If
BTERM# is disabled through the PCI9060
configuration registers, the PCI9060 will also burst up
to 4 Lwords. If enabled, the PCI9060 will continue to
burst until a BTERM# input is asserted. BTERM# is a
ready input that breaks up a burst cycle and causes
another address cycle to occur. BTERM# is used in
conjunction with the PCI9060 programmable wait
state generator.
DT/R# is used in conjunction with DEN# to provide
control for data transceivers attached to the local bus.
DT/R# is used in conjunction with DEN# to provide
control for data transceivers attached to the local bus.
When asserted the signal indicates that the PCI9060
receives data.
LW/R# is asserted low for reads and is high for writes.
Lock indicates an atomic operation that may require
multiple transactions to complete. Used by the
PCI9060 for direct local access to the PCI bus.
Address bus carries the upper 30 bits of the physical
address bus. During bursts LA3 and LA2 increment to
indicate successive data cycles.
Data bus carries 32,16, or 8 bit data quantities
depending on bus width configuration.
________________________________________________________________________________
Page - 63 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
LBE[3:0]#
Byte Enables
4
I/O
TS
24 mA
139,140,
141,142
The byte enables are encoded based on configured
bus width as follows:
32 bit bus:
For a 32 bit bus, the four byte enables indicate which
of the four bytes are active during a data cycle.
BE3# Byte Enable 3 - LD[31:24]
BE2# Byte Enable 2 - LD[23-16]
BE1# Byte Enable 1 - LD[15-8]
BE0# Byte Enable 0 - LD[7-0]
16 bit bus:
For a 16 bit bus, BE3#, BE1#, and BE0# are encoded
to provied BHE#, LA1, and BLE# respectively.
BE3# Byte High Enable (BHE#) - LD[15:8]
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Byte Low Enable (BLE#) - LD[7-0]
LCLK
1
I
160
LHOLD
local
Processor
clock
Hold Request
1
158
LHOLDA
Hold Acknowledge
1
O
TP
6 mA
I
LRESETo#
Local Reset Out
1
READYi#
Ready In
1
READYo#
Ready Out
1
O
TP
6 mA
I
O
DTS
6 mA
159
11
147
148
8 bit bus:
For an 8 bit bus BE1# and BE0# are encoded to
provide LA1 and LA0 respectively.
BE3# not used
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Address bit 0 (LA0)
Local clock or i960Cx processor PCLK1 or PCLK2
output
The PCI9060 asserts LHOLD to request use of the
local bus. The i960Cx processor or local bus arbiter
asserts LHOLDA when control has been granted.
The PCI9060 asserts LHOLD to request use of the
local bus. The i960Cx processor or local bus arbiter
asserts LHOLDA when control has been granted. The
bus should not be granted to the PCI9060 unless
requested by LHOLD.
This pin is the Local bus reset output. It is asserted
when the PCI9060 chip is reset. It is used to drive the
RESET# input of the local processor.
When the PCI9060 is a bus master, READYi# is used
to indicate that read data on the bus is valid or that a
write data transfer has completed. READYi# is used
in conjunction with the PCI9060 programmable wait
state generator.
When a local bus access is made to the PCI9060,
READYo# is used to indicate that read data on the
bus is valid or that a write data transfer has
completed. READYo# can be connected to READYi#.
________________________________________________________________________________
Page - 64 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
Table 65 Jx Mode Bus Interface Pin Description (Also used for Kx processor interface)
Pin
Type
O
TS
6 mA
I/O
TS
24 mA
I/O
TS
6 mA
I
Pin
Number
1
I/O
TS
24 mA
145
Data
Transmit/Receive
1
O
TS
24 mA
138
LW/R#
Write/Read
1
137
LABS[3:2]
Address Bus Burst
2
LAD[31:0]
Address/Data Bus
32
I/O
TS
24 mA
I/O
TS
6 mA
I/O
TS
6 mA
Total
Pins
1
Symbol
ALE
Signal Name
Address
Latch
Enable
ADS#
Address Strobe
1
BLAST#
Burst Last
1
BTERM#
Burst Terminate
1
DEN#
Data Enable
DT/R#
161
154
155
146
162,163
136,135
133-125,
122-115,
113-106,
103-99
Function
ALE is asserted during the address phase and
deasserted before the data phase.
Address strobe indicates valid address and the start
of a new bus access. ADS# is asserted for the first
clock of a bus access.
BLAST# is a signal driven by the current local bus
master to indicate the last transfer in a bus access.
The i960Jx processor bursts up to 4 Lwords. If
BTERM# is disabled through the PCI9060
configuration registers, the PCI9060 will also burst
up to 4 Lwords. If enabled, the PCI9060 will continue
to burst until a BTERM# input is asserted. BTERM#
is a ready input that breaks up a burst cycle and
causes another address cycle to occur. BTERM# is
used in conjunction with the PCI9060 programmable
wait state generator.
As an input, DEN# must only be asserted during
data phases. In i960Kx systems, DEN# is used
internally to block i960Kx processor assertions of
ADS# during data phases of a burst. For non
i960Kx processor systems or systems in which
ADS# is not asserted during the data phase, DEN#
can be pulled high.
As an output, DT/R# is used in conjunction with
DEN# to provide control for data transceivers
attached to the local bus.
DT/R# is used in conjunction with DEN# to provide
control for data transceivers attached to the local
bus. When asserted the signal indicates that the
PCI9060 receives data.
LW/R# is asserted low for reads and is high for
writes.
Carries the word address of the 32 bit memory
address. These bits are incremented during a burst
access.
During the address phase the bus carries the upper
30 bits of the physical address bus. During the data
phase, the bus carries 32 bits of data.
________________________________________________________________________________
Page - 65 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
LBE[3:0]#
Byte Enables
4
I/O
TS
24 mA
139,140,
141,142
The byte enables are encoded based on configured
bus width as follows:
32 bit bus:
For a 32 bit bus, the four byte enables indicate which
of the four bytes are active during a data cycle.
BE3# Byte Enable 3 - LAD[31:24]
BE2# Byte Enable 2 - LAD[23-16]
BE1# Byte Enable 1 - LAD[15-8]
BE0# Byte Enable 0 - LAD[7-0]
16 bit bus:
For a 16 bit bus, BE3#, BE1#, and BE0# are
encoded to provied BHE#, LA1, and BLE#
respectively.
BE3# Byte High Enable (BHE#) - LAD[15:8]
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Byte Low Enable (BLE#) - LAD[7-0]
8 bit bus:
For an 8 bit bus BE1# and BE0# are encoded to
provide LA1 and LA0 respectively.
BE3# not used
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Address bit 0 (LA0)
LCLK
LHOLD
System Clock
Hold Request
1
1
160
158
1
I
O
TP
6 mA
I
LHOLDA
Hold Acknowledge
LLOCK#
Bus Lock
1
I
153
LRESETo#
Local Reset Out
1
11
READYi#
Ready In
1
O
TP
6 mA
I
READYo#
Ready Out
1
O
DTS
6 mA
159
147
148
Local clock or i960Jx processor clock.
The PCI9060 asserts LHOLD to request use of the
local bus. The i960Jx processor or local bus arbiter
asserts LHOLDA when control has been granted.
The PCI9060 asserts LHOLD to request use of the
local bus. The i960Jx processor or local bus arbiter
asserts LHOLDA when control has been granted.
The bus should not be granted to the PCI9060
unless requested by LHOLD.
Lock indicates an atomic operation that may require
multiple transactions to complete. Used by the
PCI9060 for direct local access to the PCI bus.
This pin is the Local bus reset output. It is asserted
when the PCI9060 chip is reset.
When the PCI9060 is a bus master, READYi# is
used to indicate that read data on the bus is valid or
that a write data transfer has completed. READYi# is
used in conjunction with the PCI9060 programmable
wait state generator.
When a local bus access is made to the PCI9060,
READYo# is used to indicate that read data on the
bus is valid or that a write data transfer has
completed. READYo# can be connected to
READYi#.
________________________________________________________________________________
Page - 66 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
Table 66 Sx Mode Interface Pin Description
Total
Pins
1
Symbol
ALE
Signal Name
Address
Latch
Enable
AS#
Address Strobe
1
BLAST#
Burst Last
1
BTERM#
Burst Terminate
1
DEN#
Data Enable
1
DT/R#
Data
Transmit/Receive
1
LA[31:16]
Address Bus
16
LABS[3:1]
Address Bus Burst
3
Address/Data Bus
16
Byte Enables
2
LAD[15:1],D0
LBE[1:0]#
LCLK
System Clock
1
LHOLD
Hold Request
1
Pin
Type
O
TS
6 mA
I/O
TS
24 mA
I/O
TS
6 mA
I
Pin
Number
161
O
TS
24 mA
O
TS
24 mA
145
I/O
TS
6 mA
I/O
TS
6 mA
I/O
TS
6 mA
I/O
TS
24 mA
I
O
TP
6 mA
154
155
146
138
136,135
133-125
122-118
162-164
117-115
113-106
103-99
141,142
160
158
Function
ALE is asserted during the address phase and
deasserted before the data phase.
Address strobe indicates valid address and the start
of a new bus access. AS# is asserted for the first
clock of a bus access.
BLAST# is a signal driven by the current local bus
master to indicate the last transfer in a bus access.
The i960Sx processor does not use a BTERM#
input. It bursts up to 8 words. If BTERM# is
disabled through the PCI9060 configuration
registers, the PCI9060 will also burst up to 8 words.
If enabled, the PCI9060 will continue to burst until a
BTERM# input is asserted. BTERM# breaks up a
burst cycle and causes another address cycle to
occur. BTERM# is used in conjunction with the
PCI9060 programmable wait state generator.
DT/R# is used in conjunction with DEN# to provide
control for data transceivers attached to the local
bus.
DT/R# is used in conjunction with DEN# to provide
control for data transceivers attached to the local
bus. When asserted the signal indicates that the
PCI9060 receives data.
Carries the upper 32 bits of the address.
Carries the word address of the 32 bit memory
address. These bits are incremented during a burst
access.
During the address phase the bus carries the lower
physical address bits. During the data phase, the
bus carries 16 bits of data.
Byte enables indicate which of the two bytes are
active during a data cycle.
i960Sx processor’s CLK2 input. The i960Sx
processor’s RESET# input must be connected to the
PCI9060 LRESETo# output. This enables the
PCI9060 to determine the phase of the 2x clock
processor.
The PCI9060 asserts LHOLD to request use of the
local bus. The i960Sx processor or local bus
arbiter asserts LHOLDA when control has been
granted.
________________________________________________________________________________
Page - 67 Version 1.2
Section B
PCI9060
SECTION 5
PIN DESCRIPTION
________________________________________________________________________________
LHOLDA
Hold Acknowledge
1
I
159
LLOCK#
Bus Lock
1
I
153
LRESETo#
Local Reset Out
1
O
TP
6 mA
11
LW/R#
Write/Read
1
137
READYi#
Ready In
1
I/O
TS
24 mA
I
READYo#
Ready Out
1
O
DTS
6 mA
147
148
The PCI9060 asserts LHOLD to request use of the
local bus. The i960Sx processor or local bus
arbiter asserts LHOLDA when control has been
granted. The bus should not be granted to the
PCI9060 unless requested by LHOLD.
Lock indicates an atomic operation that may require
multiple transactions to complete. Used by the
PCI9060 for direct local access to the PCI bus.
This pin is the Local bus reset output. It is asserted
when the PCI9060 chip is reset.
Note: this output must be used to drive the Reset
Input of the i960Sx processor. This enables the
PCI9060 to determine the phase of the 2x clock
processor.
LW/R# is asserted low for reads and is high for
writes.
When the PCI9060 is a bus master, READYi# is
used to indicate that read data on the bus is valid or
that a write data transfer has completed. READYi#
is used in conjunction with the PCI9060
programmable wait state generator.
When a local bus access is made to the PCI9060,
READYo# is used to indicate that read data on the
bus is valid or that a write data transfer has
completed. READYo# can be connected to
READYi#.
________________________________________________________________________________
Page - 68 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
6. SECTION 6 - ELECTRICAL AND TIMING SPECIFICATIONS
Absolute Maximum Ratings
-65 °C to +150 °C
Storage Temperature
Ambient
Applied
Operating Ranges
Temperature
with
Power
Ambient
Temp.
-55 °C to +125 °C
Supply Voltage to Ground
-0.5V to +7.0V
Input Voltage (VIN)
VSS
VDD
-0.5V
+ 0.5V
Output Voltage (VOUT)
VSS
VDD
-0.5V
+ 0.5V
Junction
Supply
Voltage
(VDD)
Input
Voltage
(VIN)
5V +/- 5%
Min =
VSS
Max =
VDD
Temp.
0 °C to
115 °C
+70 °C
Maximum
Capacitance (sample tested only)
Parameter
Test Conditions
Pin Type
Typical Value
Units
CIN
VIN = 2.0V
f = 1 MHz
Input
5
pF
COUT
VOUT = 2.0V
f = 1 MHz
Output
10
pF
Electrical Characteristics Tested Over Operating Range
Parameter
Description
VOH
Output High Voltage
VDD = Min,
IOH = -4.0 mA
VOL
Output Low Voltage
VIN = VIH or VIL
IOL per Tables
VIH
Input High Level
VIL
Input Low Level
ILI
Input Leakage Current
VSS ≤ VIN ≤ VDD
VDD = Max
IOZ
Tri-state Output Leakage Current
VDD = Max
VSS ≤ VIN ≤ VDD
ICC
Power Supply Current
Test Conditions
Min
Max
2.4
Units
V
0.4
2.0
V
V
0.8
V
-10
+10
µA
-10
+10
µA
VDD=5.25V,
130 mA
PCLK=LCLK=33Mhz
________________________________________________________________________________
Page - 69 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
LOCAL
CLOCK
TVALID
(MAX)
TVALID
(MIN)
VALID
OUTPUTS
Figure 9. PCI9060 Local Output Delay
AC Electrical Characteristics (Local Outputs) Measured Over Operating Range
Signals (Synchronous Outputs)
CL = 50 pF, VCC = 5.0 ± 5%
LHOLD
LDSHOLD
ADS#
BLAST# *(see note below)
LBE[3:0]#
LW/R#
LD[31:0]
LA[31:0]
DT/R#
DEN#
READYO#
DP[3:0]
LRESETO#
LAD[31:0] (Jx,Sx Mode)
LABS[3:1] (Jx,Sx Mode)
BTERMo#
BREQo
LINTO
LSERR#
PCHK#
USERO
WAITO
DACK[1:0]#
DMPAF#
LALE
(Jx,Sx Mode) (address setup and
hold relative to LALE negative edge)
TVALID
(MIN) NSEC
TVALID
(MAX) NSEC
(HOLD)
(WORST CASE)
5
5
6
8
8
6
9
8
6
5
5
12
5
9
8
8
5
5
9
6
5
6
6
5
5
17
16
13
16
16
17
20
20
17
13
14
20
17
20
20
19
21
16
16
20
21
14
20
17
---
Specification Changes
Direct Slave Write BLAST# Tvalid: If the PCI 9060 is performing a Direct Slave burst write to the local bus, write cycles
in which not all byte enables are asserted are broken into single address and data cycles. In this case, the Tvalid time
to the BLAST# signal preceding the single cycle (BLAST# prior to the new ADS#) can be as much as 25 ns
________________________________________________________________________________
Page - 70 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
LOCAL
CLOCK
THOLD
TSETUP
VALID
INPUTS
Figure 10. PCI9060 Local Input Setup and Hold Waveform
AC Electrical Characteristics (Local Inputs) Measured Over Operating Range
Signals (Synchronous Inputs)
CL = 50 pF, VCC = 5.0 ± 5%
LHOLDA
ADS#
BLAST#
LD[31:0]
LAD[31:0]
DP[3:0]
BTERM#
DREQ[1:0]#
READYi#
TSETUP (nsec)
Local Clock Input Frequency
PCI Clock Input Frequency
5
9
6
7
3
4
5
6
9
THOLD (nsec)
(worst case)
1
1
1
1
1
1
1
1
Min
0
0
Max
40 MHz
33 MHz
________________________________________________________________________________
Page - 71 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
7. SECTION 7 - PACKAGE MECHANICAL DIMENSIONS
7.1 Package Mechanical Dimensions
For 208 PQFP, θJC = 5°C/Watt
________________________________________________________________________________
Page - 72 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
7.2 Typical PCI Bus Master Adapter
________________________________________________________________________________
Page - 73 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
7.3 I960Cx
 MODE PIN OUT
________________________________________________________________________________
Page - 74 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
7.4 I960Jx
 MODE PIN OUT
________________________________________________________________________________
Page - 75 Version 1.2
Section B
PCI9060
SECTION 7
PACKAGE SPECIFICATIONS
________________________________________________________________________________
7.5 I960Sx
 MODE PIN OUT
________________________________________________________________________________
Page - 76 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
8. SECTION 8- TIMING DIAGRAMS
The PCI9060 operates in three modes, selected through mode pins, corresponding to three processor types; Cx, Jx and Sx.
Timing Diagrams are provided for the three operating modes. For some functions, a timing diagram may only be provided for
one mode of operation. Even though a different mode is used, that timing diagram can be used to determine functionality.
8.1 List of Timing Diagrams
Timing Diagram 1. Initialization from Serial EEPROM..........................................................................................................78
Timing Diagram 2. PCI9060 Local bus Arbitration ................................................................................................................79
Timing Diagram 3. Local LINTi# Input Asserting PCI Output INTA# .....................................................................................79
Timing Diagram 4. (CX,JX Mode) PCI RST# Asserting Local Output LRESETO# .................................................................79
Timing Diagram 5. (CX Mode) Local Bus Write to PCI9060 Configuration Register.............................................................80
Timing Diagram 6. (CX Mode) Local Bus Read from PCI9060 Configuration Register.........................................................80
Timing Diagram 7. (CX Mode) Local Bus Direct Master Memory Write Cycles to PCI Bus...................................................81
Timing Diagram 8. (CX Mode) Local Bus Direct Master Memory Read from PCI Bus..........................................................82
Timing Diagram 9. (CX Mode) Local Bus Direct Master Locked Read Followed by Write and Release................................83
Timing Diagram 10. (CX Mode) Direct Slave PCI to Local burst Read of 5..........................................................................84
Timing Diagram 11. (CX Mode) BREQO & Deadlock ...........................................................................................................85
Timing Diagram 12. (CX Mode) Direct Slave PCI to Local burst write..................................................................................86
Timing Diagram 13. (CX Mode) PCI9060 DMA or Direct Slave Burst Write, Bterm Enabled................................................87
Timing Diagram 14. (CX Mode) PCI9060 DMA or Direct Slave Burst Write, Bterm Disabled ...............................................87
Timing Diagram 15. (CX Mode) Direct Slave or DMA Burst Read from Local Bus (1 Wait State ) ......................................88
Timing Diagram 16. (CX Mode) Burst Read from Local Bus (1 Wait State Programmed) ...................................................88
Timing Diagram 17. (CX Mode) DMA or Direct Slave 2 Lword Burst Write to 8 Bit Local Bus...............................................89
Timing Diagram 18. (CX Mode) PCI9060 Read of DMA Chaining Parameters from Local Bus ............................................90
Timing Diagram 19. (CX Mode) Single Cycle DMA Demand Mode PCI to Local..................................................................91
Timing Diagram 20. (CX Mode) Multiple Cycle DMA Demand Mode PCI to Local ...............................................................91
Timing Diagram 21. (JX Mode) Local Bus Write to PCI9060 Configuration Register.............................................................92
Timing Diagram 22. (JX Mode) Local Bus Read from PCI9060 Configuration Register.........................................................92
Timing Diagram 23. (JX Mode) Local Bus Direct Master Locked Read Followed by Write and Release................................93
Timing Diagram 24. (JX Mode) DMA or Direct Slave Burst Write, Bterm Enabled ................................................................94
Timing Diagram 25. (JX Mode) DMA or Direct Slave Burst Write, Bterm Disabled ...............................................................94
Timing Diagram 26. (JX Mode) DMA or Direct Slave Burst Read, Bterm Enabled ................................................................95
Timing Diagram 27. (JX Mode) DMA Burst Write to 32 Bit Local Bus Suspended by BREQ input.........................................96
Timing Diagram 28. (JX Mode) Read of DMA Chaining Parameters from Local Bus ............................................................97
Timing Diagram 29. (SX Mode) Two Phase Clock Synchronization using LRESETO#..........................................................98
Timing Diagram 30. (SX Mode) Local Bus Write to Configuration Register...........................................................................99
Timing Diagram 31. (SX Mode) Local Bus Read from Configuration Register.......................................................................99
Timing Diagram 32. (SX Mode) Direct Slave or DMA Burst Write to Local Bus ..................................................................100
________________________________________________________________________________
Page - 77 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0us
5us
10us
15u
20us
25us
EESK
LRESETO#
EECS
EEDI
0
1
1
0
0
0
0
0
0
0
EEDO
INTERNALLY PULLED UP
D15
0
START BIT 0 INDICATES EEPROM PRESENT ----|
D14
D13
D12
D1
1
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BITS 31-16 CFG REGISTER 0
HEX
.
EESK
EEDO
D15 D14
D13
D12
D1
1
D10
.
D9
D8
D7
D6
D4
D5
D3
D2
D1
D0
D1
D0
BITS 15-0 CFG REGISTER 0
HEX
D15
D14
D13
D8 D7
D12 D1
D6
D10 D9
1
BITS 31-16 OF CFG REGISTER 8
HEX
D5
D4
.
CONTINUES
.
EESK
EECS
EEDO
D15 D14
D13 D12
D1
1
LAST WORD
D10
D9
D8
D7
D6
D5
D4
D3
D2
EESK, EEDO,EECS FROM CFG
REGISTERS
AFTER COMPLETION OF READ
SHORT: BITS 15-0 MAILBOX 1 LOC C4
HEX
LONG: BITS 15-0 LOC REGISTER 2C
Timing Diagram 1. Initialization from Serial EEPROM
________________________________________________________________________________
Page - 78 Version 1.2
Section B
PCI9060
D3
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
600ns
LCLK
LHOLD
WILL NOT BE REASSERTED UNITL LHOLDA GOES LOW
LDSHOLD
HIGH IF DIRECT SLAVE REQUEST
|--- CAN GO HIGH
LHOLDA
MUST REMAIN HIGH UNTIL LHOLD GOES LOW
LOCAL BUS
PCI9060 DRIVES BUS
PCI9060 always gives up bus between different local bus accesses:
different direct slave access, different DMA access, between direct slave/DMA accesses
Timing Diagram 2. PCI9060 Local bus Arbitration
0ns
25ns
50ns
75ns
10
LOCAL LINTi#
[3,15]
PCI INTA#
[3,15]
Timing Diagram 3. Local LINTi# Input Asserting PCI Output INTA#
0ns
PCI RST#
50ns
100ns
150ns
200ns
ASYNCHRONOUS
LCLK
LRESETO#
Timing Diagram 4. (CX,JX Mode) PCI RST# Asserting Local Output LRESETO#
________________________________________________________________________________
Page - 79 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
450ns
500ns
LCLK
LA[31..0]
ADDR
LD[31..0]
DATA 0
CS OR
DATA 1
DATA
CS OR A31-29 MATCH S2-0
A31-29 MATCH S2-0
CS#
ADS#
LBE[3..0]#
DATA
0
BYTE ENABLES
DATA
1
BYTE ENABLES
LW/R#
BLAST#
READYO#
PCHK#
PCHK1
PCHK0
BURST ACCESS
SINGLE ACCESS
note: 1st READYo# will be delayed for access to shared registers
Timing Diagram 5. (CX Mode) Local Bus Write to PCI9060 Configuration Register
0ns
50ns
100ns
150ns
200ns
250ns
LCLK
LA[31..0]
LD[31..0]
DATA 0
DATA 1
CS OR A31-29 MATCH S2-0
CS#
ADS#
LBE[3..0]#
LW/R#
BLAST#
DP[3..0]
DP0
DP1
READYO#
note: 1st READYo# will be delayed for access to shared registers
Timing Diagram 6. (CX Mode) Local Bus Read from PCI9060 Configuration Register
________________________________________________________________________________
Page - 80 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
600ns
LCLK
LA[31:2]
A1
A
<--- LOCAL ADDRESS MATCHES LOCAL DIRECT MASTER BASE ADDRESS
LD[31:0]
LBE[3:0]#
D0
D0 BE3-0
D1
D2
D3
D4
D4 BE3-0
LW/R#
ADS#
BLAST#
READYO#
PCHK#
PCI_CLK-33
REQ#
GNT#
FRAME#
RE-MAPPED A -->
AD[31:0]
C/BE[3:0]#
R-A
D0
D1
D2
D3
R-A1
D4
CMD
D0 BE
D1 BE
D2 BE
D3 BE
CMD
D4 BE
DEVSEL#
IRDY#
TRDY#
Note: The PCI9060 will accept local bus bursts longer than 4 Lwords
Timing Diagram 7. (CX Mode) Local Bus Direct Master Memory Write Cycles to PCI Bus
________________________________________________________________________________
Page - 81 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
LCLK
A[31:2]
A
LW/R#
ADS#
BLAST#
READYO#
LD[31:0]
D0
D1
D2
D3
PCI_CLK-33
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]#
A0
CMD
D0
0
D1
D2
D3
0
0
0
DEVSEL#
IRDY#
TRDY#
(PCI preread 4 mode)
Note: Unused read data is flushed in cases in which more read data is prefetched than used
Timing Diagram 8. (CX Mode) Local Bus Direct Master Memory Read from PCI Bus
________________________________________________________________________________
Page - 82 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
250ns
500ns
750ns
LCLK
A[31:2]
WA
RA
LW/R#
UNLOCK -->
LLOCK#
<-- LOCK
KEEP LOCK -->
ADS#
BLAST#
READYO#
LD[31:0]
D0
WD
PCI_CLK-33
REQ#
GNT#
FRAME#
AD[31:0]
R-RA
D0
D1
D2
D3
R-WA
0
0
0
CMD
C/BE[3:0]#
CMD
0
WD
DEVSEL#
IRDY#
TRDY#
LOCK#
(1 Lword burst read, PCI preread 4 mode)
Timing Diagram 9. (CX Mode) Local Bus Direct Master Locked Read Followed by Write and Release
________________________________________________________________________________
Page - 83 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
600ns
700ns
80
PCI CLK
FRAME#
AD[31:0]
ADDR
D0
D1
D2
D4
D3
C/BE#
CMD
BYTE ENABLES
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:2]
ADDR
+4
LD[31:0]
D0
D1
+8
D2
+12
+16
D3
D4
+20
+24
+28
D5
D6
D7
READYI#
unused read data is flushed
(no wait states, 32 bit bus, burst enabled)
Timing Diagram 10. (CX Mode) Direct Slave PCI to Local burst Read of 5
________________________________________________________________________________
Page - 84 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
250ns
TITLE
BUS SIGNALS FOR BACKOFF
500ns
750ns
(PCI9060 C_DSRB.TD) (03/06/95)
PCI CLK
FRAME#
AD[31:0]
C/BE#
DIRECT SLAVE READ
ADDR
CMD
D0
D1
D2
BYTE ENABLES
IRDY#
DEVSEL#
TRDY#
DIRECT MASTER WILL NOT GAIN PCI BUS UNTIL DIRECT SLAVE ACCESS COMPLETES
(GNT# ASSERTED , FRAME# DEASSERTED, IRDY# DEASSERTED)
REQ#
LCLK
LHOLD
<-- DIRECT SLAVE- BREQ TIMER STARTS
LHOLDA
DIRECT SLAVE PROCEEDS
ADS#
LA[31:2]
DIRECT MASTER READ
ADDR
LD[31:0]
READYO#
D0
D1
D2
D3
NO DIRECT MASTER READY
READYI#
BREQO
BREQO timer expires and asserts BREQO --->|
to indicate potential deadlock condition
External logic backs off Direct Master transfer and
asserts LHOLDA to grant the local bus for a Direct
Slave transfer.
LHOLDA causes the PCI9060 local logic to abort the
Local side of the Direct Master Read
note: For partial deadlock PCI retry timer bits 31:28 of the
Local Bus Region Descriptor Register can be used to issue
RETRYs to the PCI Master attempting the Direct Slave access.
Refer to section 3 for a description of DEADLOCK
At completion of the Direct Slave Transfer, LHOLD is
deasserted which enables External backoff logic to
restart the Direct Master transfer. If the previous PCI
read access has already started, the read data is flushed
and a new PCI Direct Master read cycle is started.
Timing Diagram 11. (CX Mode) BREQO & Deadlock
________________________________________________________________________________
Page - 85 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
450ns
50
PCI CLK
FRAME#
AD[31::0]
C/BE[3:0]#
ADDR
DATA0
DATA1
CMD
D0 BE
D1 BE
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
L W/R#
LA[31:2]
+4
ADDR
LD[31:0]
DATA0
+8
DATA1
DT/R#
DEN#
READYI#
(no wait states, 32 bit bus, burst enabled)
Timing Diagram 12. (CX Mode) Direct Slave PCI to Local burst write
________________________________________________________________________________
Page - 86 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
600ns
LCLK
<---
PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3..0]#
0000,
DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
LW/R#
LD[31..0]
D0
LA[31:2]
D1
D2
A+4
A
D3
A+8
A+12
D4
D5
A+16
A+20
D6
A+24
D8
D7
A+28
D9
A+36
A+32
D10
A+40
DT/R#
DEN#
BTERM# FORCES NEW ADS# -->
BTERM#
READYI#
note: BTERM# is a ready input which also causes a new ADS# cycle
note: not all byte enables asserted will cause a new ADS# cycle
(no wait states, 32 bit bus,burst enabled, BTERM enabled)
Timing Diagram 13. (CX Mode) PCI9060 DMA or Direct Slave Burst Write, Bterm Enabled
0ns
100ns
200ns
300ns
400ns
500ns
600
LCLK
<---
PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3..0]#
XXX1
0000, DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
LW/R#
LD[31..0]
LA[31:2]
D0
A[3:2]=11
A
D1
A[3:2]=00
A+4
D2
01
A+8
D3
10
A+12
D4
A[3:2]=11
A+16
D5
D6
D7
D8
A+24
A+28
A+32
A[3:2]=00
A+20
DT/R#
DEN#
BTERM#
READYI#
note: not all byte enables asserted or a quad boundary LA[3:2]=11 results in a new ADS#
(no wait states, 32 bit bus,burst enabled,bterm disabled)
Timing Diagram 14. (CX Mode) PCI9060 DMA or Direct Slave Burst Write, Bterm Disabled
________________________________________________________________________________
Page - 87 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
50ns
100n
150n
200ns
250ns
300ns
350ns
400ns
450ns
500ns
LCLK
<--- PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LDSHOLD
HIGH FOR DIRECT SLAVE ACCESS
LHOLDA
ADS#
BLAST#
LBE[3..0]#
0000
LW/R#
LD[31..0
D0
LA[31:2]
D2
D1
A+4
A
A+8
D3
A+12
A+16
DT/R#
DEN#
BTERM#
READYI#
(32 Bit Local Bus, burst enabled, Bterm Disabled)
Timing Diagram 15. (CX Mode) Direct Slave or DMA Burst Read from Local Bus (1 Wait State )
0ns
50ns
100n
150n
200ns
250ns
300ns
350ns
400ns
450ns
500ns
LCLK
<--- PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LDSHOLD
HIGH FOR DIRECT SLAVE ACCESS
LHOLDA
ADS#
BLAST#
LBE[3..0]#
0000
LW/R#
LD[31..0
LA[31:2]
D0
D1
A+4
A
D2
A+8
D3
A+12
A+16
DT/R#
DEN#
BTERM#
WAITO#
If ready input is enabled in bus region register, additional wait states can be asserted externally
(32 Bit Local Bus, burst enabled, Bterm Disabled)
Timing Diagram 16. (CX Mode) Burst Read from Local Bus (1 Wait State Programmed)
________________________________________________________________________________
Page - 88 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
50ns
100n
150n
200ns
250ns
300ns
350ns
400ns
450ns
500n
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:0]
LBE[3.:0]=A[1:0]
LD[7:0]
A
A+4
BE=A1,0=00
0-7
01
10
8-15
16-23
1
1
24-31
00
01
0-7
8-15
10
16-23
1
1
24-31
READYI#
(no wait states, 8 bit bus,burst enabled)
Timing Diagram 17. (CX Mode) DMA or Direct Slave 2 Lword Burst Write to 8 Bit Local Bus
________________________________________________________________________________
Page - 89 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
60
LCLK
<---
PCI9060 DRIVES BUS
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3:0]#
ALL ZERO
LW/R#
LA[31:2]
A
LD[31:0]
A+4
D0
A+8
D1
A+12
D2
D3
DT/R#
DEN#
READYI#
(no wait states, 32 bit bus)
1st Address A are bits 4..31 of the next descriptors pointer register
D0: PCI Start Address, D1: Local Start Address, D2: Transfer Count (bytes), D3: Next Descriptor Pointer
Timing Diagram 18. (CX Mode) PCI9060 Read of DMA Chaining Parameters from Local Bus
________________________________________________________________________________
Page - 90 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
50ns
100ns
150ns
200ns
250ns
30
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3..0]#
LW/R#
LD[31..0
D0
LA[31:2]
A
DREQ# MUST BE DEASSERTED TO PREVENT BURST -->
DREQ#
DACK#
READYI#
(no wait states, 32 bit local bus)
Timing Diagram 19. (CX Mode) Single Cycle DMA Demand Mode PCI to Local
0ns
50ns
100ns
150ns
200ns
250ns
300ns
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3..0]#
LW/R#
LD[31..0]
D0
LA[31:2]
A
D1
A+4
CURRENT DATA + LAST DATA TRANSFERRED AFTER DREQ# IS DEASSERTED
DREQ#
DACK#
READYI#
(no wait states,burst enabled,bterm enabled, 32 bit local bus)
Timing Diagram 20. (CX Mode) Multiple Cycle DMA Demand Mode PCI to Local
________________________________________________________________________________
Page - 91 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
450ns
500ns
LCLK
LAD[31..0]
ADDR
CS OR
DATA 0
ADDR
DATA 1
A31-29 MATCH S2-0
DATA
CS OR A31-29 MATCH S2-0
CS#
ADS#
FOR DATA
FOR DATA
0
1
LBE[3..0]#
LW/R#
DEN#
BLAST#
READYO#
PCHK#
PCHK1
PCHK0
BURST ACCESS
SINGLE ACCESS
note: If not used DEN# can be pulled high
note: 1st READYo# will be delayed for access to shared registers
Timing Diagram 21. (JX Mode) Local Bus Write to PCI9060 Configuration Register
0ns
50ns
100ns
150ns
200ns
250ns
LCLK
LAD[31..0]
ADDR
DATA 0
DATA 1
CS OR A31-29 MATCH S2-0
CS#
ADS#
LBE[3..0]#
LW/R#
DEN#
BLAST#
DP[3..0]
DP0
DP1
READYO#
note: If not used DEN# can be pulled high
note: 1st READYo# will be delayed for access to shared registers
Timing Diagram 22. (JX Mode) Local Bus Read from PCI9060 Configuration Register
________________________________________________________________________________
Page - 92 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
250ns
500ns
750ns
LCLK
LAD[31:0]
RA
D0
WA
WD
LW/R#
UNLOCK -->
LLOCK#
<-- LOCK
KEEP LOCK -->
ADS#
DEN#
BLAST#
READYO#
PCI_CLK-33
REQ#
GNT#
FRAME#
AD[31:0]
R-RA
D0
D1
D2
D3
R-WA
0
0
0
CMD
C/BE[3:0]#
CMD
0
WD
DEVSEL#
IRDY#
TRDY#
LOCK#
(1 Lword burst read, PCI preread 4 mode)
Timing Diagram 23. (JX Mode) Local Bus Direct Master Locked Read Followed by Write and Release
________________________________________________________________________________
Page - 93 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
60
LCLK
<---
PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LHOLDA
ADS#
ALE
BLAST#
LBE[3..0]#
DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
LW/R#
LAD[31..0]
A
LBA[3:2]
D0
D1
D2
D4
D3
A+20
LAD[3:2]
D5
D6
D7
LAD[3:2]
DT/R#
DEN#
BTERM#
READYI#
note BTERM# is a ready input which also causes a new ADS# cycle
(no wait states, 32 bit bus,burst enabled)
Timing Diagram 24. (JX Mode) DMA or Direct Slave Burst Write, Bterm Enabled
0ns
100ns
200ns
300ns
400ns
500ns
60
LCLK
<---
PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LHOLDA
ADS#
ALE
BLAST#
LBE[3..0]#
DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
LW/R#
LAD[31..0]
LBA[3:2]
A
00
D0
D1
01
D2
10
A+16
D3
11
00
D4
D5
01
D6
10
D7
11
DT/R#
DEN#
BTERM#
READYI#
Note: When Bterm is disabled, a new ADS (address) cycle starts every quad word boundary
(no wait states, 32 bit bus,burst enabled)
Timing Diagram 25. (JX Mode) DMA or Direct Slave Burst Write, Bterm Disabled
________________________________________________________________________________
Page - 94 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
60
LCLK
LHOLD
<---
PCI9060 FLOATS BUS -->
PCI9060 DRIVES BUS
LHOLDA
ADS#
ALE
BLAST#
LBE[3..0]#
DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
LW/R#
LAD[31..0]
A
LBA[3:2]
00
D0
D2
D1
01
10
D4
D3
11
00
A+20
01
D6
D5
10
D7
11
DT/R#
DEN#
BTERM#
READYI#
(no wait states, 32 bit bus,burst enabled, BTERM enabled)
Timing Diagram 26. (JX Mode) DMA or Direct Slave Burst Read, Bterm Enabled
________________________________________________________________________________
Page - 95 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
600ns
70
LCLK
<---
PCI9060 DRIVES BUS
PCI9060 FLOATS BUS -->
LHOLD
LHOLDA
ADS#
ALE
BLAST#
LBE[3..0]#
DOES NOT CHG, UNALIGNED HAS OWN CYCLE WITH ADS
LW/R#
LAD[31..0]
LBA[3:2]
A
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A+40
D10
LAD[3:2]
DT/R#
DEN#
BTERM#
READYI#
BREQ
OWNED BY
i960JX OR
ANOTHER
BUS MASTER
DMA CONTINUES
WHERE IT LEFT OFF
(no wait states, 32 bit bus,burst enabled, BTERM enabled)
Timing Diagram 27. (JX Mode) DMA Burst Write to 32 Bit Local Bus Suspended by BREQ input
________________________________________________________________________________
Page - 96 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
0ns
100ns
200ns
300ns
400ns
500ns
60
LCLK
<---
PCI9060 DRIVES BUS
LHOLD
LHOLDA
ADS#
ALE
BLAST#
LBE[3..0]#
ALL ZERO
LW/R#
LAD[31..0]
A
D0
A+4
D1
A+8
D2
A+12
D3
DT/R#
DEN#
READYI#
(no wait states, 32 bit bus)
1st Address A are bits 4..31 of the next descriptors pointer register
D0: PCI Start Address, D1: Local Start Address, D2: Transfer Count (bytes), D3: Next Descriptor Pointer
Timing Diagram 28. (JX Mode) Read of DMA Chaining Parameters from Local Bus
________________________________________________________________________________
Page - 97 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
FIRST
A
B
C
D
CLK
LRESETO#
AS#
LA[31:16]
ADDR
LAD[15:1],D0
ADDR
DATA
LRESETO# must be used to establish phase A relationship as shown
Timing Diagram 29. (SX Mode) Two Phase Clock Synchronization using LRESETO#
________________________________________________________________________________
Page - 98 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
A
B
C
D
CLK
LA[31:16]
ADDR
LAD[15,1],D0
ADDR
LABS{3:2]
DATA 0
DATA 1
ADDR
LABS[1]
START WORD ADDR
CS#
NEXT WORD ADDR
CS OR
A31-29 MATCH S2-0
AS#
LBE[1..0]#
BYTE ENABLES FOR DATA WORD 1
BYTE ENABLES FOR DATA WORD 0
LW/R#
BLAST#
READYO#
PCHK#
PCHK1
PCHK0
Timing Diagram 30. (SX Mode) Local Bus Write to Configuration Register
A
B
C
D
LCLK
LA[31:16]
LAD[15:1],D0
LABS[1]
CS#
ADDR
DATA 0
ADDR
DATA 1
NEXT WORD ADDR
START WORD ADDR
CS OR A31-29 MATCH S2-0
ADS#
LBE[1..0]#
LW/R#
BLAST#
DP[3..0]
DP0
DP1
READYO#
Timing Diagram 31. (SX Mode) Local Bus Read from Configuration Register
________________________________________________________________________________
Page - 99 Version 1.2
Section B
PCI9060
SECTION 8
TIMING DIAGRAMS
________________________________________________________________________________
A
LCLK
LHOLD
LHOLDA
AS#
BLAST#
LA[31:16]
A+4
A
A + 8
A+12
LBE[1:0]#
LABS[3:1]
LAD[16:1],D0
A
A
A+2
0-15
16-31
A+4
0-15
A+6
16-31
A+8
0-15
A+10
16-31
A+12
A+14
0-15
16-31
BTERM#
READYI#
note: not all byte enables asserted results in a new AS#
(no wait states, bus,burst enabled, BTERM enabled)
Timing Diagram 32. (SX Mode) Direct Slave or DMA Burst Write to Local Bus
________________________________________________________________________________
Page - 100 Version 1.2
Section B
PCI9060