NTD12N10 Power MOSFET 12 Amps, 100 Volts N−Channel Enhancement−Mode DPAK http://onsemi.com Features • Source−to−Drain Diode Recovery Time Comparable to a Discrete • • • • Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Mounting Information Provided for the DPAK Package These are Pb−Free Devices V(BR)DSS RDS(on) TYP ID MAX 100 V 165 mW @ 10 V 12 A N−Channel D Typical Applications • PWM Motor Controls • Power Supplies • Converters G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Unit Drain−to−Source Voltage VDSS 100 Vdc Drain−to−Source Voltage (RGS = 1.0 MW) VDGR 100 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 30 Vdc Vpk ID ID 12 7.0 36 Adc PD 56.6 0.38 1.76 1.28 W W/°C W W TJ, Tstg −55 to +175 °C EAS 75 mJ Drain Current − Continuous @ TA = 25°C − Continuous @ TA =100°C − Pulsed (Note 3) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance − Junction to Case − Junction to Ambient (Note 1) − Junction to Ambient (Note 2) Maximum Temperature for Soldering Purposes, 1/8 in from case for 10 seconds IDM May, 2010 − Rev. 8 4 Drain 4 1 2 2 1 3 Drain Gate Source 2.65 85 117 TL 260 4 Drain 4 1 RqJC RqJA RqJA 3 DPAK CASE 369C (Surface Mount) STYLE 2 Apk DPAK CASE 369D (Straight Lead) STYLE 2 2 3 °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 0.5 sq in pad size. 2. When surface mounted to an FR4 board using the minimum recommended pad size. 3. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%. © Semiconductor Components Industries, LLC, 2010 MARKING DIAGRAMS & PIN ASSIGNMENTS 1 YWW T12 N10G Value YWW T12 N10G Symbol Rating 1 2 3 Gate Drain Source Y WW T12N10 G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: NTD12N10/D NTD12N10 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 100 − − 135 − − − − − − 5.0 50 − − ± 100 2.0 − 3.1 −7.5 4.0 − − − 0.130 0.250 0.165 0.400 − 1.62 2.16 gFS − 7.0 − mhos pF OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = 10 Vdc, ID = 6.0 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 125°C) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 12 Adc) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) Vdc mV/°C W Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance Ciss − 390 550 Coss − 115 160 Crss − 35 70 td(on) − 11 20 SWITCHING CHARACTERISTICS (Notes 4 & 5) Turn−On Delay Time Rise Time (VDD = 80 Vdc, ID = 12 Adc, VGS = 10 Vdc, RG = 9.1 W) Turn−Off Delay Time Fall Time Total Gate Charge (VDS = 80 Vdc, ID = 12 Adc, VGS = 10 Vdc) Gate−to−Source Charge Gate−to−Drain Charge ns tr − 30 60 td(off) − 22 40 tf − 32 60 Qtot − 14 20 Qgs − 3.0 − Qgd − 7.0 − VSD − − 0.95 0.80 1.0 − Vdc trr − 85 − ns ta − 60 − tb − 28 − QRR − 0.3 − nC BODY−DRAIN DIODE RATINGS (Note 4) Diode Forward On−Voltage Reverse Recovery Time (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 125°C) (IS = 12 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge mC 4. Indicates Pulse Test: P.W. = 300 ms max, Duty Cycle = 2%. 5. Switching characteristics are independent of operating junction temperature. ORDERING INFORMATION Package Shipping† NTD12N10G DPAK (Pb−Free) 75 Units/Rail NTD12N10−1G DPAK−3 (Pb−Free) 75 Units/Rail NTD12N10T4G DPAK (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTD12N10 TYPICAL ELECTRICAL CHARACTERISTICS 24 VGS = 10 V 7V 9V 20 TJ = 25°C ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 24 6.5 V 8V 16 6V 7.5 V 12 5.5 V 8 5V 4 4.5 V 0 0 8 9 1 2 3 4 5 6 7 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS ≥ 10 V 20 16 12 8 TJ = 25°C 4 10 0 1 2 3 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 0.4 TJ = 100°C TJ = 25°C 0.1 0 TJ = −55°C 0 4 8 12 16 ID, DRAIN CURRENT (AMPS) 20 24 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.5 0.2 0.2 TJ = 25°C 0.175 VGS = 10 V 0.15 VGS = 15 V 0.125 0.1 0 Figure 3. On−Resistance versus Drain Current and Temperature 3 2.5 10 Figure 2. Transfer Characteristics 4 12 16 8 ID, DRAIN CURRENT (AMPS) 20 24 Figure 4. On−Resistance versus Drain Current and Gate Voltage 10000 ID = 6 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.3 TJ = −55°C TJ = 100°C 0 2 1.5 1 VGS = 0 V TJ = 150°C 1000 100 TJ = 100°C 0.5 0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 10 175 20 Figure 5. On−Resistance Variation with Temperature 40 50 60 70 80 90 100 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 NTD12N10 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1000 VDS = 0 V TJ = 25°C Ciss 800 C, CAPACITANCE (pF) VGS = 0 V 600 Crss Ciss 400 Coss 200 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 100 18 90 QT 16 80 VDS 14 70 12 60 10 VGS 8 Q1 6 50 40 Q2 30 4 20 ID = 12 A TJ = 25°C 2 0 0 2 4 6 8 10 QG, TOTAL GATE CHARGE (nC) 10 0 14 12 1000 VDD = 80 V ID = 12 A VGS = 10 V 100 t, TIME (ns) 20 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTD12N10 tr tf td(off) td(on) 10 1 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (W) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 12 VGS = 0 V TJ = 25°C 10 8 6 4 2 0 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 NTD12N10 ID, DRAIN CURRENT (AMPS) 100 VGS = 20 V SINGLE PULSE TC = 25°C 10 ms 10 100 ms 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 0.1 10 ms dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 80 ID = 12 A 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 1.0 50 75 100 125 175 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 0.00001 t1 t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01 t, TIME (s) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 1 10 NTD12N10 PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C−01 ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE −T− E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN RECOMMENDED FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD12N10 PACKAGE DIMENSIONS DPAK−3 (SINGLE GAUGE) CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 0.13 (0.005) INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL M DIM A B C D E F G H J K R S V Z T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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