ETC NTD3055L104-1

NTD3055L104
Power MOSFET
12 Amps, 60 Volts, Logic Level
N–Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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Features
•
•
•
•
•
12 AMPERES
60 VOLTS
RDS(on) = 104 mΩ
Lower RDS(on)
Lower VDS(on)
Tighter VSD Specification
Lower Diode Reverse Recovery Time
Lower Reverse Recovery Stored Charge
N–Channel
D
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
4
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
60
Vdc
Drain–to–Gate Voltage (RGS = 10 MΩ)
VDGR
60
Vdc
VGS
VGS
15
20
ID
ID
12
10
45
Adc
PD
48
0.32
2.1
1.5
W
W/°C
W
W
TJ, Tstg
–55 to
+175
°C
EAS
61
mJ
Rating
Gate–to–Source Voltage
– Continuous
– Non–Repetitive (tp10 ms)
Drain Current
– Continuous @ TA = 25°C
– Continuous @ TA = 100°C
– Single Pulse (tp10 µs)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH
IL(pk) = 11 A, VDS = 60 Vdc)
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient (Note 1)
– Junction–to–Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
1 2
3
Apk
1
CASE 369A
DPAK
(Bent Lead)
STYLE 2
Vdc
IDM
S
NTD3055L104
Y
WW
3.13
71.4
100
°C/W
TL
260
°C
1. When surface mounted to an FR4 board using 1″ pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
= Device Code
= Year
= Work Week
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
YWW
NTD
3055L104
1
Gate
2
Drain
3
Source
1
Gate
ORDERING INFORMATION
Device
NTD3055L104
NTD3055L104T4
September, 2001 – Rev. 2
1
3
Source
2
Drain
Package
Shipping
DPAK
75 Units/Rail
DPAK
NTD3055L104–1
Straight Lead
 Semiconductor Components Industries, LLC, 2001
3
CASE 369
DPAK
(Straight Lead)
STYLE 2
YWW
NTD
3055L104
RθJC
RθJA
RθJA
2
DPAK
75 Units/Rail
2500/Tape & Reel
Publication Order Number:
NTD3055L104/D
NTD3055L104
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
–
70
62.9
–
–
–
–
–
–
1.0
10
–
–
±100
1.0
–
1.6
4.2
2.0
–
–
89
104
–
–
0.98
0.86
1.50
–
gFS
–
9.1
–
mhos
Ciss
–
316
440
pF
Coss
–
105
150
Crss
–
35
70
td(on)
–
9.2
20
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–Resistance (Note 3)
(VGS = 5.0 Vdc, ID = 6.0 Adc)
RDS(on)
Static Drain–to–Source On–Voltage (Note 3)
(VGS = 5.0 Vdc, ID = 12 Adc)
(VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 6.0 Adc)
Vdc
mV/°C
mOhm
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 30 Vdc, ID = 12 Adc,
VGS = 5.0 Vdc, RG = 9.1 Ω) (Note 3)
Fall Time
Gate Charge
(VDS = 48 Vdc,
Vd ID = 12 Adc,
Ad
VGS = 5.0 Vdc) (Note 3)
ns
tr
–
104
210
td(off)
–
19
40
tf
–
40.5
80
QT
–
7.4
20
Q1
–
2.0
–
Q2
–
4.0
–
VSD
–
–
0.95
0.82
1.2
–
Vdc
trr
–
35
–
ns
ta
–
21
–
tb
–
14
–
QRR
–
0.04
–
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 12 Adc, VGS = 0 Vdc) (Note 3)
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 12 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
µC
NTD3055L104
24
16
4.5 V
6V
4V
12
8
3.5 V
4
3V
0
1
3
2
4
5
6
7
16
12
8
TJ = 25°C
4
TJ = 100°C
1
8
TJ = –55°C
2
2.5
3
3.5
4
4.5
5
5.5
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
VGS = 5 V
0.28
0.24
TJ = 100°C
0.20
0.16
TJ = 25°C
0.12
TJ = –55°C
0.08
0.04
0
0
4
8
16
12
20
24
6
0.32
VGS = 10 V
0.28
0.24
0.20
TJ = 100°C
0.16
0.12
TJ = 25°C
0.08
TJ = –55°C
0.04
0
0
4
8
12
16
20
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus
Gate–to–Source Voltage
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2
24
10,000
VGS = 0 V
ID = 6 A
VGS = 5 V
IDSS, LEAKAGE (nA)
1.8
1.5
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0.32
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
VDS ≥ 10 V
20
0
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
0
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
8V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
20
24
5V
VGS = 10 V
1.6
1.4
1.2
1
1000
TJ = 150°C
100
TJ = 100°C
10
0.8
0.6
–50 –25
1
0
25
50
75
100
125
150
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
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3
60
NTD3055L104
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
C, CAPACITANCE (pF)
1000
800
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
600
Crss
400
Ciss
200
Coss
Crss
0
10
0
5
VGS
10
5
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
6
1000
QT
5
Q1
Q2
4
3
t, TIME (ns)
VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)
NTD3055L104
VGS
2
100
tr
tf
td(off)
10
td(on)
VDS = 30 V
ID = 12 A
VGS = 5 V
ID = 12 A
TJ = 25°C
1
0
1
0
2
4
6
QG, TOTAL GATE CHARGE (nC)
8
1
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
16
VGS = 0 V
14
12
10
TJ = 150°C
8
TJ = 25°C
6
4
2
0
0.3
0.5
0.4
0.6
0.7
0.8
0.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTD3055L104
I D, DRAIN CURRENT (AMPS)
100
VGS = 15 V
SINGLE PULSE
TC = 25°C
10 µs
10
100 µs
1 ms
1
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10
1
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.1
100
EAS , SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
70
ID = 11 A
60
50
40
30
20
10
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0
25
175
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P(pk)
0.1 0.05
0.02
t1
0.01
SINGLE PULSE
t2
DUTY CYCLE, D = t1/t2
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RθJC(t)
0.01
0.00001
0.0001
0.001
0.01
t, TIME (µs)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1
10
NTD3055L104
PACKAGE DIMENSIONS
DPAK
CASE 369A–13
ISSUE AA
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
–T–
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
H
D
2 PL
0.13 (0.005)
G
M
T
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
--0.030
0.050
0.138
---
STYLE 2:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
--0.77
1.27
3.51
---
GATE
DRAIN
SOURCE
DRAIN
DPAK
CASE 369–07
ISSUE M
C
B
V
E
R
4
A
1
2
3
S
–T–
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.090 BSC
0.034
0.040
0.018
0.023
0.350
0.380
0.175
0.215
0.050
0.090
0.030
0.050
STYLE 2:
PIN 1.
2.
3.
4.
T
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7
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.46
1.27
2.28
0.77
1.27
NTD3055L104
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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8
NTD3055L104/D