AD ADP5588

Keypad I/O Expander
ADP5588
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADP5588
REF
VOLTAGE
GND 19
VCC
21
SCL 23
SDA 22 CONTROL
REGISTERS
RST 20
CONTROL
INTERFACE
C9
C9
C8
C8
C9
18
REF
VOLTAGE
C8
17
R2
R1
11
12
13
14
15
16
07673-001
R3
10
C7
R4
9
C6
R5
8
C5
7
C4
6
C3
5
C2
4
C1
3
C0
2
R0
1
R6
INT 24
R7
18-GPIO port expander or 10 × 8 keypad matrix
GPIOs configurable to GPIs, GPOs, and keypad rows or
columns
Dual light sensor inputs (C8 and C9)
I2C interface
I2C register read autoincrement
1.8 V to 3.0 V operation
Keypad lock capability
Open-drain interrupt output
Key press and key release interrupts
GPI interrupt with level programmability
Programmable pull-ups
Key event counter with overflow interrupt
50 μs debounce on the reset line and GPIs
1 μA typical idle current, 55 μA typical polling current drain
for one key press
Small 4 mm × 4 mm LFCSP package
Figure 1.
APPLICATIONS
Keypad and I/O expander designed for QWERTY type phones
that require a large keypad matrix
GENERAL DESCRIPTION
The ADP5588 is an I/O port expander and keypad matrix
designed for QWERTY type phones that require a large keypad
matrix and expanded I/O lines. I/O expander ICs are used in
mobile platforms as a solution to the limited number of GPIOs
available in the main processor.
In its small 4 mm × 4 mm package, the ADP5588 contains
enough power to handle all key scanning and decoding and flag
the processor of key presses and releases via the I2C® interface
and interrupt. It frees the main microprocessor from having to
monitor the keypad, thereby minimizing current drain and
increasing processor bandwidth. It is also equipped with a
buffer/FIFO and key event counter to handle and keep track of
up to 10 unprocessed key or GPI events with overflow wrap and
interrupt capability.
The ADP5588 has a keylock capability with an option to trigger
or not trigger an interrupt at key presses and releases. All communication to the main processor is done using one interrupt line
and two I2C-compatible interface lines. The ADP5588 can be
configured to have a keypad matrix of up to 8 rows × 10 columns
(a maximum of 80 keys).
When used for smaller keypad matrices, unused row and
column pins can be reconfigured to act as general-purpose
inputs, outputs, or light sensor inputs. R0, R1, R2, R3, R4, R5,
R6, and R7 denote the row pins of the matrix, while C0, C1, C2,
C3, C4, C5, C6, C7, C8, and C9 denote the column pins. At
power-up, all rows and columns default as GPIs and must be
programmed to function as part of the keypad matrix, GPOs, or
light sensor inputs. In addition to keypad and GPIO functionalities,
C8 and C9 can also be configured as light sensor inputs.
When configured as keypad lines, the function of the C8 and
C9 lines is straightforward: the control interface disconnects
these lines from the comparator inputs, disables the light sensor
comparator, and connects them to the keypad columns of the
keypad matrix. When used as light sensor comparator inputs,
the control interface disconnects these pins from the keypad,
enables the comparators, and connects these lines to the comparator inputs. Two external capacitors (0.1 μF) are required
when these pins are configured as light sensor inputs. When
used as GPIOs, these pins are removed from the keypad and the
light sensor interface, and the light sensor comparators are
disabled, along with the logic for the sensors.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADP5588
TABLE OF CONTENTS
Features .............................................................................................. 1 Keypad Operation .........................................................................7 Applications ....................................................................................... 1 General-Purpose Inputs and Outputs ........................................9 Functional Block Diagram .............................................................. 1 I C Programming and Digital Control ........................................ 14 General Description ......................................................................... 1 Registers ....................................................................................... 15 Revision History ............................................................................... 2 Register Descriptions ................................................................. 16 Specifications..................................................................................... 3 Comparator Register Descriptions .......................................... 21 DC Electrical Characteristics ...................................................... 3 Applications Information .............................................................. 24 Absolute Maximum Ratings............................................................ 5 Applications Overview .............................................................. 24 Thermal Resistance ...................................................................... 5 Keypad Current .......................................................................... 24 ESD Caution .................................................................................. 5 Backlight Control Application.................................................. 24 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 26 Theory of Operation ........................................................................ 7 Ordering Guide .......................................................................... 26 2
REVISION HISTORY
11/08—Rev. Sp0 to Rev. A
Rev. A | Page 2 of 28
ADP5588
SPECIFICATIONS
TA = TJ = −40°C to +85°C, unless otherwise noted.
DC ELECTRICAL CHARACTERISTICS
Table 1. General DC Electrical Characteristics
Parameter
SUPPLY VOLTAGE
VCC Input Voltage Range
Photosensor Voltage
Supply Current 1
With One Key Press
With One Key Press
With GPI Low (Pull-Up Enabled) 2
With GPI Low (Pull-Up Disabled)
With One GPO Active 3
AMBIENT LIGHT SENSOR (CMP_IN1, CMP_IN2)
Maximum Sensor Range
Sensor Supply Current (One Comparator
Enabled, 0 Minimum Input Current) 4
Sensor Current (One Comparator Enabled,
Maximum Input Current)4
Sensor Current (Both Comparators Enabled,
Minimum Input Current)4
Sensor Current (Both Comparators Enabled,
Maximum Input Current)4
OSCILLATOR CURRENT
Oscillator Current (Enabled)
Symbol
Conditions
Min
Typ
Max
Unit
3.0
VCC + 0.2
10
90
200
50
10
50
V
μA
μA
μA
μA
μA
μA
1.0
100
1.15
150
mA
μA
VCC
VPHOTOSENSOR
ICC
ICC
ICC
ICC
ICC
ICC
1.7
VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C
VCC = 1.8 V, TA = −40°C to +85°C
VCC = 3.0 V, TA = −40°C to +85°C
VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C
VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C
VCC = 1.8 V, TA = −40°C to +85°C
ISENSOR
ICC
VCC = 1.8 V to 3.0 V, TA = 25°C
VCC = 1.8 V to 3.0 V
ICC
VCC = 1.8 V to 3.0 V
160
200
μA
ICC
VCC = 1.8 V to 3.0 V
130
180
μA
ICC
VCC = 1.8 V to 3.0 V
240
400
μA
ICC
VCC = 1.8 V to 3.0 V
40
1
55
100
20
2
0.85
μA
1
Operating current measured with I/Os defaulting as GPIs with all pull-ups enabled and all inputs open.
With one GPI low.
Load = 100 k.Ω
4
Photosensor maximum voltage = VCC + 0.2.
2
3
Table 2. I/O DC Electrical Characteristics
Parameter
INPUT LOGIC LEVELS (SCL, SDA, RST, C0 to C9, R0 to R7) 1
Logic Low Input Voltage
Logic High Input Voltage
Schmitt Trigger Hysteresis
Input Leakage Current
OUTPUT LOGIC LEVELS (C0 to C9, R0 to R7)
Logic Low Output Voltage
Output High Voltage
OUTPUT LOGIC LEVELS (INT, SDA)
Output Low Voltage
Symbol
Conditions
Min
VIL
VIH
VHYST
VI-LEAKAGE
1.7 V ≤ VIO ≤ 3.0 V
1.7 V ≤ VIO ≤ 3.0 V
0.65 x VCC
1.7 V ≤ VIO ≤ 3.0 V
−1
VOL
VOH
ISINK = 1 mA
ISOURCE = 1 mA
VOL
Output High Voltage
Logic High Leakage Current
PULL-UP RESISTANCE FOR GPIOs (C0 to C9, R0 to R7) 2
VOH
VO-LEAKAGE
RPULL-UP
ISINK = 3 mA
1.7 V ≤ VCC ≤ 3.0 V
1.7 V ≤ VCC ≤ 3.0 V
1.7 V ≤ VCC ≤ 3.0 V
1
2
Typ
Max
Unit
0.2 x VCC
V
V
V
μA
0.10
Power-up default current. All I/Os default as GPIs and are open; C8 and C9 default as GPIs; I2C is idle.
GPIO internal pull-ups are designed to 100 kΩ.
Rev. A | Page 3 of 28
1
0.40
V
V
0.40
V
1
V
μA
kΩ
VCC − 0.3 V
0.95 × VCC
0.1
100
ADP5588
Table 3. Comparator Input Capacitor
Parameter
Comparator Input Capacitor Value
Symbol
CCOMP
Min
Typ
0.1
Max
Unit
μF
Symbol
CIN
COUT
CB 2
Min
Typ
1
Max
10
50
400
Unit
pF
pF
pF
Symbol
RSTD
TKUT
TKIMT
TD
TTTR
Min
60
Typ
Max
Unit
μs
sec
sec
μs
sec
Symbol
fSCL
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
tSP
Min
Table 4. Capacitance Loading 1
Parameter
I/O Input Capacitance
I/O Output Loading Capacitance
Capacitive Load for Each Bus Line
1
2
Guaranteed by design.
CB = total capacitance of one bus line in picofarads.
Table 5. AC Characteristics 1
Parameter
Delay from Reset Deassertion to I2C Access
Keypad Unlock Timer
Keypad Interrupt Mask Timer
Debounce
Filter Time
1
7
31
50
0.070
12
Guaranteed by design.
Table 6. I2C AC Electrical Characteristics 1
Parameter
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time for Stop and Start
Setup Time for Stop Condition
Rise Time for SCL and SDA 2
Fall Time for SCL and SDA2
Pulse Width of Suppressed Spike
2
Max
400
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20 + 0.1 CB
20 + 0.1 CB
0
0.9
300
300
50
Unit
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
ns
μs
Guaranteed by design.
tR and tF are measured between 0.3 × VCC and 0.7 × VCC.
SDA
tLOW
tR
tF
tSU, DAT
tF
tHD, STA
tSP
tBUF
tR
SCL
S
tHD, DAT
tHIGH
tSU, STA
Sr
tSU, STO
P
S
07673-002
1
Typ
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Figure 2. I2C Interface Timing Diagram
Rev. A | Page 4 of 28
ADP5588
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
VCC
R0 to R7, C0 to C9
SCL
SDA
RST
INT
GND
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
ESD Machine Model
ESD Human Body Model
ESD Charged Device Model
Soldering Condition
Rating
−3 V to +4.0 V
−3 V to VCC + 0.3 V
−3 V to VCC+ 0.3 V
−3 V to VCC + 0.3 V
−3 V to VCC + 0.3 V
−3 V to VCC + 0.3 V
−0.3 V to +0.3 V
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
±200 V
±2000 V
±1000 V
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8. Thermal Resistance
Package Type
24-Lead LFCSP_VQ
Maximum Power
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 5 of 28
θJA
57.8
600
θJC
9.4
Unit
°C/W
mW
ADP5588
24
23
22
21
20
19
INT
SCL
SDA
VCC
RST
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
PIN 1
INDICATOR
ADP5588
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
CMP_IN2/C9
CMP_IN1/C8
C7
C6
C5
C4
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
07673-003
R1
R0
C0
C1
C2
C3
7
8
9
10
11
12
R7
R6
R5
R4
R3
R2
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
R7
R6
R5
R4
R3
R2
R1
R0
C0
C1
C2
C3
C4
C5
C6
C7
CMP_IN1/C8
CMP_IN2/C9
GND
RST
21
22
23
24
VCC
SDA
SCL
INT
EP
EPAD
Description
GPIO, Row 7 in the Keypad Matrix.
GPIO, Row 6 in the Keypad Matrix.
GPIO, Row 5 in the Keypad Matrix.
GPIO, Row 4 in the Keypad Matrix.
GPIO, Row 3 in the Keypad Matrix.
GPIO, Row 2 in the Keypad Matrix.
GPIO, Row 1 in the Keypad Matrix.
GPIO, Row 0 in the Keypad Matrix.
GPIO, Column 0 in the Keypad Matrix.
GPIO, Column 1 in the Keypad Matrix.
GPIO, Column 2 in the Keypad Matrix.
GPIO, Column 3 in the Keypad Matrix.
GPIO, Column 4 in the Keypad Matrix.
GPIO, Column 5 in the Keypad Matrix.
GPIO, Column 6 in the Keypad Matrix.
GPIO, Column 7 in the Keypad Matrix.
GPIO, Column 8 in the Keypad Matrix; Comparator Input for Photosensor 1.
GPIO, Column 9 in the Keypad Matrix; Comparator Input for Photosensor 2.
Ground.
Hardware Reset (Active Low). This bit resets the device to the power default conditions. The reset pin must be
driven for a minimum of 50 μs to be valid and to prevent falsing due to ESD glitches or noise in the system. If
not used, RST must be tied high with a pull-up.
VCC = 1.7 V to 3.3 V.
I2C Serial Data (Open Drain Requires External Pull-up).
I2C Clock.
Processor Interrupt, Active Low, Open Drain. This pin can be pulled up to 2.7 V or 1.8 V for selection flexibility in
the processor GPIO supply group.
Exposed Pad. The exposed pad must be connected to ground.
Rev. A | Page 6 of 28
ADP5588
THEORY OF OPERATION
CONTROL
INTERFACE
REF
VOLTAGE
20
C9
C9
C8
C8
C9
0.1µF
C8
17
0.1µF
8
9
10
11
12
13
14
15
16
C7
7
C6
6
C5
5
C4
4
C3
3
C2
2
C1
1
C0
24
R0
RST
INT
22
R1
SCL
SDA
CONTROL
REGISTERS
R2
INT
18
23
R3
RST
VCC
R4
SDA
ADP5588
21
R5
SCL
R6
VCC
REF
VOLTAGE
19
R7
GND
VCC
A7 A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
C7 C6 C5 C4 C3 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
E7 E6 E5 E4 E3 E2 E1 E0
F7 F6 F5 F4 F3 F2 F1 F0
G7 G6 G5 G4 G3 G2 G1 G0
H7 H6 H5 H4 H3 H2 H1 H0
I6
I5
I4
I3
I2
I1
I0
07673-009
I7
J7 J6
J5 J4 J3 J2 J1 J0
Figure 4. Typical Operating Circuit
The ADP5588 is a GPIO expander that can be configured either
as an 18-I/O port expander or as a 10 column × 8 row keypad
matrix (80 keys maximum). It is ideal for cellular phone designs
and other portable devices that require a large extended keypad
and/or expanded I/Os (see the Applications Information section
for various configurations). When smaller size keypads are
required, unused GPIOs in the keypad matrix can be used as
I/Os (GPOs and GPIs). Two of the columns (C8 and C9) can
also be configured as comparator inputs for single or dual light
sensors. All GPIOs (rows and columns) default as GPIs at powerup with pull-ups and debounce enabled.
KEYPAD OPERATION
Any number of rows and columns, up to 10 columns × 8 rows,
can be configured to be part of the keypad matrix. The rows
and columns that make up the keypad matrix must be configured by setting the corresponding bits in Register 0x1D
through Register 0x1F. Keys on the keypad matrix appear on
the key event table with a decimal value of 1 (0x01 hexidecimal
or 0000001 binary) and run through 80 decimals (0x50 hexidecimal or 1010000 binary). See Table 10 for key event number
assignments. The keypad, in idle mode, is configured with
columns being driven low and rows as inputs high with pullups.
Table 10. Key Event Number Assignment Table
Row
R0
R1
R2
R3
R4
R5
R6
R7
C0
1
11
21
31
41
51
61
71
C1
2
12
22
32
42
52
62
72
C2
4
13
23
33
43
53
63
73
C3
4
14
24
34
44
54
64
74
C4
5
15
25
35
45
55
65
75
C5
6
16
26
36
46
56
66
76
C6
7
17
27
37
47
57
67
77
C7
8
18
28
38
48
58
68
78
C8
9
19
29
39
49
59
69
79
C9
10
20
30
40
50
60
70
80
When one key press or multiple key presses (short between
coumn and row) occur, the internal state machine checks the
row pins to determine which one is driven low and then triggers
an interrupt. The state machine then starts a key scan cycle to
determine which keys are pressed. After a key has been pressed
for 25 ms, the state machine sets the appropriate key(s) in the
key event status register with the key-pressed bits set (the MSB
in the key event register) in the order detected. If the KE_IEN
field in Register 0x01 is set, the state machine then sets the
KE_INT field in Register 0x01 and generates an interrupt to the
host processor.
Rev. A | Page 7 of 28
ADP5588
The first read of any of the FIFO registers displays the first
event that happened and its status. Subsequent reads of the
same register replace the register data with the next event that
happens. If tracking of all the events is important, it is best to
used a single register per event. After all the events in the FIFO
are read, reading of any of the event registers yields a zero value.
To prevent glitches or narrow press times registering as valid
key presses, the key scanner requires the key to be pressed for
two scan cycles. The key scanner has a sampling period of 25 ms,
so the key must be pressed and held for at least 25 ms to register
as pressed. If the key is continuously pressed, the key scanner
continues to sample every 25 ms. If a key that was pressed is
released for 25 ms or greater, the state machine sets the appropriate keys in the key event status register with the key pressed
bits cleared in the order detected. Because the release of a key is
not necessarily in sync with the key scan sampling period, it may
take between 25 ms and 50 ms for a key to register as released.
After the key is registered as released, the key scanner goes back
to idle mode. Figure 5 shows the row and column pins
connected to a typical 10 × 8, 80-switch keypad matrix.
Table 11 and Table 12 show the event sequences as they are
logged in and read from the FIFO. The 10 FIFO registers are
labeled A through J, and keys are labeled A0 through J7.
Table 11. Example of Event Sequence
Key Pressed/Released
A0
B1
A0
C2
B1
D3
C2
E4
E4
D3
D0_PULL
KEYPAD SCAN AND DECODE
D1_PULL
D2_PULL
D4_PULL
D3_PULL
D5_PULL
D6_PULL
D7_PULL
VCC
R7 R6 R5 R4 R3 R2 R1 R0
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
B7 B6 B5 B4 B3 B2 B1 B0
C7 C6 C5 C4 C3 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
E7 E6 E5 E4 E3 E2 E1 E0
F7 F6 F5 F4 F3 F2 F1 F0
G7 G6 G5 G4 G3 G2 G1 G0
I6
I5
I4
I3
I2
I1
I0
J6
J5
J4
J3
J2
J1
J0
07673-010
H7 H6 H5 H4 H3 H2 H1 H0
I7
Key Event Counter
1
2
3
4
5
6
7
8
9
10
Table 12. Interpretation of FIFO Event Reading
A7 A6 A5 A4 A3 A2 A1 A0
J7
Status
Pressed
Pressed
Released
Pressed
Released
Pressed
Released
Pressed
Released
Released
10 × 8 KEYPAD MATRIX
Key Event
Counter
10
9
8
7
6
5
4
3
2
1
0
1
Figure 5. Keypad Decode Configuration
Key Event
Register
Read
Key Event Register Content
(Binary)1
Key Event
Register
Interpretation
D
E
C
F
G
A
B
H
J
I
1 0000000
1 0000001
0 0000000
1 0000010
0 0000001
1 0000011
0 0000010
1 0001000
0 0000100
0 0000011
Key A0 pressed
Key B1 pressed
Key A0 released
Key C2 pressed
Key B1 released
Key D3 pressed
Key C2 released
Key E4 pressed
Key E4 released
Key D3 released
The first number indicates a key press or key release in Bit 7 of the key event
register: 1 = key press; 0 = key release.
Key Event Tracking
Key Event Overflow
The 10-key event registers are set to act as a FIFO, meaning that
reading any of the 10-key event registers yields the key events in
the order they were pressed and released.
The ADP5588 is equipped with an overflow feature to handle
key events beyond the FIFO capacity. When all events are filled, any
additional events set the OVR_FLOW_INT bit in Register 0x02;
if the OVR_FLOW_IEN bit in Register 0x01 is set, the host
processor is also interrupted when overflow occurs. When the
FIFO is not full, new events are added as the last events.
Tracking of key events is done with the help of the key event
counter (the KEC field in Register 0x03) and the FIFO/key
event registers (Register 0x04 through Register 0x0D). The KEC
count increases as keys are pressed and released; up to 10 events
can be logged in the counter. The FIFO/key event registers, on
the other hand, display the key events and their status (pressed
or released) as they are read out of the FIFO. The FIFO registers
are made of eight bits, with the MSB dedicated as the status bit
(1 indicates a press and 0 indicates a release); the remaining
seven bits are used to display binary representation of the keys
that are pressed or released.
The OVR_FLOW_M bit in Register 0x01 sets the mode of
operation during overflows. Clearing the OVR_FLOW_M bit
causes new incoming events to be discarded, and setting this bit
rolls over and overwrites old data with new data starting at the
first event.
Rev. A | Page 8 of 28
ADP5588
Autoincrement
2
The ADP5588 features automatic increment during I C read
access. This allows the user to increment the address pointer
without having to send a read command for subsequent
addresses. This minimizes processor intervention and, therefore,
saves processor bandwidth and current drain. Bit 7 of Register 0x01
must be set to initiate autoincrement (see Figure 16 for the full
write and read sequence).
Key Event Interrupt
On a key event (KE) interrupt, the processor reads the interrupt
register to determine the cause of the interrupt. If the KE_INT
bit in Register 0x02 is the cause of the interrupt, the state
machine sets the KE_INT bit and reads the key event count
from the KEC[3:0] field in Register 0x03 to determine the number
of events. It then reads the INT_STAT register (Register 0x02)
to make sure that no new events have come in. After all the
events are read, the KEC field is decremented to zero (KEC =0)
and the KE_INT bit can be cleared by writing a 1 to it. Both key
presses and key releases are capable of generating key event
interrupts. The KE_INT bit cannot be cleared, and the INT pin
cannot be deasserted, until the FIFO is cleared of all events.
REG. 0x1D
THROUGH 0x1F
KP_MODE
AND
REG. 0x03
READ KE(s) TO CLEAR
KEC
The state of the keypad lock interrupt mask bit (Register 0x01,
Bit 2) in the configuration register determines whether the
interrupt pin is asserted when the keylock interrupt status bit
(Register 0x02, Bit 2) is set. Setting the keylock interrupt mask
bit causes the INT pin to be asserted when the keylock interrupt
status bit is set in Register 0x02; clearing that bit masks the
interrupt, causing the interrupt pin not to respond to the keylock
interrupt status bit. The mask interrupt timer should be set for
the time that it takes for the LCD to dim or turn off so that, if a
key is pressed, the backlight is set to bright mode again or reset
to turn on the LCD.
When the unlock mask interrupt timer equals 0, only the
correct unlock sequence can generate an interrupt. Disabling
the unlock mask interrupt timer allows the processor to remain
undisturbed for situations in which the user has the phone in a
pocket or purse and the keys are constantly pressed. The flow
chart in Figure 6 shows the interaction of the interrupt mask
timer and interrupt generation.
GENERAL-PURPOSE INPUTS AND OUTPUTS
INT DRIVE
The ADP5588 supports up to 18 programmable GPIOs that can
be configured to address a variety of uses. Figure 7 shows the
makeup of a typical GPIO block where GPIOx represents any of
the 18 I/O lines.
Figure 6. Key Event Interrupt Generation
Keypad Lock/Unlock Feature
VCC
The ADP5588 has a locking feature that allows the user to lock
the keypad or GPIs (configured to be part of the event table).
Once enabled, the keypad lock can prevent generation of key
event interrupts and key events to be recorded in the key event
table. This feature comprises the Unlock Key 1 and Unlock Key 2
registers (Register 0x0F and Register 0x10), the keypad lock
interrupt mask, the keypad unlock timers (Register 0x0E),
and the LCK1 and LCK2 bits, and the keylock enable bit
(Register 0x03).
The unlock keys can be programmed with any value of the keys
in the keypad matrix or any GPI values that are part of the key
event table. When the keypad lock interrupt mask timer is
enabled, the user must press two specific keys before a keylock
interrupt is generated or keypad events are recorded. After the
keypad is locked (set Bit 6, Register 0x03 to enable the lock), the
first time that the user presses any key, a key event interrupt is
generated. No additional interrupt is generated unless both
unlock key sequences are correct; then a keylock interrupt is
generated.
If the correct unlock keys are not pressed before the mask timer
expires, the state machine starts over. The first key event
interrupt is generated to allow the software to see that the user
has pressed a key so that the host can turn on the LCD and
Dx_PULL
Dx_IN_DBNC
Dx_IN
DEBOUNCE
VCC
GPIOx
Dx_OUT
07673-012
REG. 0x02
WRITE 1 TO CLEAR
KE_INT
07673-011
REG. 0x01
KE_IEN
display the unlock message. The host then reads the lock status
register to see if the keypad is unlocked. After the first key event
interrupt, the state machine does not interrupt the processor
again unless the correct sequence is keyed. The state machine
resets if the correct sequences are not keyed before the keypad
lock interrupt mask timer expires.
Dx_DIR
Figure 7. Typical GPIO Block
General Purpose Inputs (GPI)
The ADP5588 allows the user to configure all or some of its
GPIOs into GPIs (general-purpose inputs). After the GPIOs are
configured as GPIs, the user can opt to also turn on pull-up
resistors and interrupt generation capability, thus reducing the
amount of software monitoring and processor interaction and
saving power.
The programmed level of the GPI interrupt determines the
active level of the GPI pin. For example, if a GPI interrupt level
Rev. A | Page 9 of 28
ADP5588
is programmed as high, a high on that pin is considered active
and meets the interrupt requirement. If the interrupt is programmed as low, a low on that pin is considered active and
meets the interrupt requirement.
GPI data and interrupt status are reflected in the GPIO interrupt
and data status registers (Register 0x11 through Register 0x16).
Caution must be taken during software implementation because
an interrupt may be set immediately after register settings. To
prevent this, correct logic levels must be present at the GPIs,
and the GPIO interrupt level must be set before GPIO interrupt
enable or GPI event FIFO enable registers are set. Figure 8 shows
the interrupt generation scheme, where Dx represents any one
of the 18 GPIOs.
REG. 0x23
THROUGH 0x25
Dx_IN
AND
REG. 0x11
THROUGH 0x13 REG. 0x02
READ TWICE
WRITE 1
TO CLEAR
TO CLEAR
Dx_IN_ISTAT
GPI_INT
INT
DRIVE
07673-013
INTERRUPT
REG. 0x26
CONDITION
THROUGH 0x28
DECODE
Dx_ILVL
REG. 0x01
Dx_IN_IEN
Figure 8. GPIO Interrupt Generation
GPI Events
A column or row configured as a GPI can be programmed to be
part of the key event table and therefore also capable of generating a key event interrupt. A key event interrupt caused by a
GPI follows the same process flow as a key event interrupt
caused by a key press. GPIs configured as part of the key event
table allow single key switches and other GPI interrupts to be
monitored. As part of the event table, GPIs are represented by
the decimal value 97 (0x61 or 1100001) through the decimal
value 114 (0x72 or 1110010). See Table 13 and Table 14 for GPI
event number assignments for rows and columns.
Table 13. GPI Event Number Assignments for Rows
R0
97
R1
98
R2
99
R3
100
R4
101
R5
102
R6
103
Table 14. GPI Event Number Assignments for Columns
C0
105
C1
106
C2
107
C3
108
C4
109
C5
110
C6
111
C7
112
C9
114
When the GPI_EM_REGx bit in Register 0x20 through Register
0x22 is set, GPI events are not tracked when the keypad is
locked. The GPIEM_CFG bit (Register 0x01, Bit 6) must be
cleared for the GPI events to be tracked in the event counter
and event table when the keypad is locked.
50 Microsecond Interrupt Configuration
The ADP5588 gives the user the flexibility of deasserting the
interrupt for 50 μs while there is a pending event. When the
INT_CFG bit in Register 0x01 is set, any attempt to clear the
interrupt bit while the interrupt pin is already asserted results in
a 50 μs deassertion. When the INT_CFG bit is cleared, processor
interrupt remains asserted if the host tries to clear the interrupt.
This feature is particularly useful for software development and
edge triggering applications.
VCC
GPIO INTERRUPT
KEYLOCK INTERRUPT
OR
C8
113
For a GPI that is set as active high, and is enabled in the key
event table, the state machine adds an event to the event count
and event table whenever that GPI goes high. If the GPI is set to
active low, a transition from high to low is considered a press
and is also added to the event count and event table. After the
interrupt state is met, the state machine internally sets an
interrupt for the opposite state programmed in the register to
prevent polling for the released state, thereby saving current.
After the released state is achieved, it is added to the event table.
The press and release are still indicated by Bit 7 in the event
register (Register 0x04 through Register 0x0D). The GPI events
can also be used as unlocked sequences.
KEY EVENT INTERRUPT
OVERFLOW INTERRUPT
R7
104
INT
LOGIC
INT
COMPARATOR 1 INTERRUPT
COMPARATOR 2 INTERRUPT
GPIEM_ OVR_FLOW_ K_LCK_IM GPI_IEN KE_IEN K_LCK_EN
CFG
IEN
07673-014
KEYPAD LOCK INTERRUPT MASK TIMER
INTERRUPT CONFIGURATION
Figure 9. INT Pin Drive
Rev. A | Page 10 of 28
ADP5588
START
NO
NO
KEY PRESS
DETECTED
MASK TIMER = 0
YES
YES
KEY PRESS
DETECTED
NO
YES
GENERATE
KE INTERRUPT
FIRST UNLOCK
KEY DETECTED
START MASK TIMER
NO
YES
YES
MASK TIMER
EXPIRES
START UNLOCK1 TO UNLOCK2
NO
NO
UNLOCK1 TO
UNLOCK2
TIMER EXPIRES
FIRST UNLOCK
KEY DETECTED
YES
NO
YES
START UNLOCK1 TO UNLOCK2
SECOND UNLOCK
KEY DETECTED
UNLOCK1 TO
UNLOCK2
TIMER EXPIRES
YES
YES
GENERATE
KEYLOCK INTERRUPT
NO
YES
NO
MASK TIMER
EXPIRES
NO
NO
SECOND UNLOCK
KEY DETECTED
07673-015
YES
GENERATE
KEYLOCK INTERRUPT
Figure 10. Keypad Lock Interrupt Mask Timer Flowchart
Debouncing
Power-On Reset
The ADP5588 has a 50 μs debounce time for GPIOs configured
as GPIs and rows in keypad scanning mode. The reset line
always has a 50 μs debounce time.
For built-in power-up initialization for applications lacking a
power-on reset signal, a reset pin, RST, allows the user to reset
the registers to default values in the event of a brownout or
other reset conditions.
General Purpose Outputs (GPOs)
The ADP5588 allows the user to configure all or some of its
GPIOs as GPOs. These GPOs can be used as extra enables for
the host processor or simply as trigger outputs. When configured
as an output (GPO), a digital buffer drives the pin to 0 V for a 0
and to VCC for a 1. To set any GPIO as a GPO, make sure that
the corresponding bits in Register 0x1D through Register 0x1F are
set for GPIO mode; then use Register 0x23 through Register 0x25
to set the corresponding bits for GPO mode.
Ambient Light Sensing
The ADP5588 has built in light sensor comparator inputs to
detect ambient light conditions. An ADC samples the output of
external photosensors connected to the comparator inputs, and
the result is fed into programmable trip comparators. The ADC
has an input range of 0 μA to 1000 μA (typical). The device can
handle up to two photosensors (use Register 0x30 through
Register 0x3A to configure the photosensor inputs).
Rev. A | Page 11 of 28
ADP5588
Each light sensor input has two built-in comparators (the L2
comparator and the L3 comparator) with two programmable
trip points, L2 and L3. The trip points are used to select among
three operation modes based on ambient lighting conditions:
outdoor, office, and dark modes.
L2 = 1
L2 = 1
L2 = 0
L3 = 1
L3 = 0
L3 = 0
1 kLUX
1000µA
0 LUX
DARK
OFFICE
L3
OUTDOOR
07673-016
0µA
L2
BRIGHTNESS
Figure 11. Light Sensor Comparator Modes and Trip Points
L2 Comparator
The L2 comparator is used to detect when the photosensor
output drops below the programmable L2_TRIP point. When
this event occurs, the L2_OUT status signal is set. L2_CMPR
contains programmable hysteresis, meaning that the photosensor output must rise above L2_TRIP + L2_HYS before
L2_OUT is cleared.
L2_CMPR is enabled via the L2_EN bit (Bit 0, Register 0x31 for
Sensor 1 and Bit 0, Register 0x32 for Sensor 2). The L2_TRIP
and L2_HYS values of L2_CMPR can be set between 0 μA and
1000 μA in steps of 4 μA.
L3 Comparator
The L3 comparator is used to detect when the photosensor
output drops below the programmable L3_TRIP point. When
this event occurs, the L3_OUT status signal is set. L3_CMPR
contains programmable hysteresis, meaning that the photosensor output must rise above L3_TRIP + L3_HYS before
L3_OUT is cleared. L3_CMPR is enabled via the L3_EN bit.
The L3_TRIP and L3_HYS values of L3_CMPR can be set
between 0 μA and 127.5 μA in steps of 0.5 μA.
The L2_CMPR and L3_CMPR comparators can be enabled
independently of each other, and the ADC and comparator(s)
run continuously when L2_EN and/or L3_EN is set.
Photosensor Operation
The comparator inputs remain idle until enabled, at which
point they detect lighting conditions from the photosensor
output. Depending on lighting conditions, and where the L2
and L3 trip points are set in the comparator level trip registers
(Register 0x33 through Register 0x3A), the comparators set a
value of 1 or 0 to L2_OUT and L3_OUT. The values of L2 and
L3 determine what mode or setting adjustment is required for a
particular lighting condition. Figure 11, Figure 12, and Table 15
summarize the mode settings and logical values of L2 and L3.
Table 15. L2_OUT and L3_OUT Comparator Mode
Combination
L3
0
0
1
L2
0
1
1
Mode
Outdoor
Office
Dark
It is also possible to use the light sensor comparators in singleshot mode. A single-shot measurement is done when the
FORCE_RD bit in Register 0x31 is set. After the single-shot
measurement is completed, the internal state machine clears the
FORCE_RD bit. It takes 80 ms for a complete conversion. To
reduce the potential for flickering, the sensors can be programmed
for a number of sequential readings. The filter settings in
Register 0x31 and Register 0x32 determine the number of
sequential readings needed by the user; these settings range
from 80 ms to 10.24 sec.
L2_EN
L2_HYST
L2_TRIP
VCC
PHOTOSENSOR
COMP
INPUT
L2_CMP
L2_OUT
L3_CMP
L3_OUT
FILTER
SETTING
ADC
L3_HYST
L3_TRIP
L2_TRIP
L2_HYST
L3_EN
Figure 13. Light Sensor and Trip Points Block Diagram
1
10
100
ADC RANGE (µA)
1000
07673-017
L3_TRIP
L3_HYST
Figure 12. Comparator Ranges
Rev. A | Page 12 of 28
07673-018
Light Sensor Inputs
ADP5588
Comparator Interrupt
in Register 0x02. If the comparator interrupt enable bits are set,
the interrupt pin is asserted every time the comparator
interrupt bits are set. The comparator interrupt flag can be
cleared only by writing a 1 to it.
The ADP5588 allows the user to trigger an interrupt based on
the light sensor comparator inputs. Changes in lighting condition
that cause the settings of L2 and L3 to jump from one mode to
another (dark, office, outdoor) set the comparator interrupt bits
Table 16. Device Configuration
Keypad
GPIO
Matrix
10 × 8
8×8
Active Pins
C0 to C9, R0 to R7
C0 to C7, R0 to R7
Number of Keys
80
64
8×7
C0 to C7, R0 to R6
56
8×6
C0 to C7, R0 to R5
48
8×5
C0 to C7, R0 to R4
40
7×7
C0 to C6, R0 to R6
49
7×6
C0 to C6, R0 to R5
42
7×5
C0 to C6, R0 to R4
35
6×6
C0 to C5, R0 to R5
36
6×5
C0 to C5, R0 to R4
30
6×4
C0 to C5, R0 to R3
24
…
0×0
…
None
…
0
Available GPIO
0
0
C8
C9
R7
C8, R7
R7, C8, C9
R6, R7
R6, R7, C8
R6, R7, C8, C9
R5, R7
R5 to R7, C8
R5 to R7, C8 to C9
R7, C7
R7, C7 to C8
R7, C7 to C9
R6 to R7, C7
R6 to R7, C7 to C8
R6 to R7, C7 to C9
R5 to R7, C7
R5 to R7, C7 to C8
R5 to R7, C7 to C9
R6 to R7, C6 to C7
R6 to R7, C6 to C8
R6 to R7, C6 to C9
R5 to R7, C6 to C7
R5 to R7, C6 to C8
R5 to R7, C6 to C9
R4 to R7, C6 to C7
R4 to R7, C6 to C8
R4 to R7, C6 to C9
…
R0 to R7, C0 to C9
Number of GPIOs
0
0
1
1
1
2
3
2
3
4
3
4
5
2
3
4
3
4
5
4
5
6
4
5
6
5
6
7
6
7
8
…
18
Rev. A | Page 13 of 28
Photosensor Inputs
Photosensor
Number of
Input Pin(s)
Photosensor Inputs
None
0
C8, C9
2
C9
1
C8
1
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
C8, C9
2
C9
1
None
0
…
…
None
0
ADP5588
I2C PROGRAMMING AND DIGITAL CONTROL
Figure 15 shows a typical read sequence for reading back an
internal register. The cycle begins with a start condition
followed by the chip write address (0x68). The ADP5588
acknowledges the chip write address byte by pulling the data
line low. The address of the register from which data is to be
read is sent next. The ADP5588 acknowledges the register
address byte by pulling the data line low. The cycle continues
with a repeat start followed by the chip read address (0x69). The
ADP5588 acknowledges the chip read address byte by pulling
the data line low. The ADP5588 places the contents of the
previously addressed register on the bus for readback. There is
no acknowledge following the readback data byte, and the cycle
is completed with a stop condition.
The ADP5588 provides full software programmability to
facilitate its adoption in various product architectures. All
register programming is done via the I2C bus at Address 0x69
(01101001) for a read and Address 0x68 (01101000) for a write.
All communication to the ADP5588 is done via its I2C-compatible
serial interface. Figure 14 shows a typical write sequence for
programming an internal register. The cycle begins with a start
condition followed by the chip write address (0x68). The
ADP5588 acknowledges the chip write address byte by pulling
the data line low. The address of the register to which data is to
be written is sent next. The ADP5588 acknowledges the register
address byte by pulling the data line low. The data byte to be
written is sent next. The ADP5588 acknowledges the data byte
by pulling the data line low. A stop condition completes the
sequence.
0 = WRITE
0
0
0
0
0
0
0
CHIP ADDRESS
0 SP
SUBADDRESS
ADP5588 RECEIVES DATA
07673-019
1
ADP5588 ACK
1
ADP5588 ACK
0
ADP5588 ACK
ST
Figure 14. I2C Write Sequence
0
0
0
0
0
0
0
0
CHIP ADDRESS
0
0
0
0
1
1
0
ST
0
1
1
SUBADDRESS
0
0
0
CHIP ADDRESS
0
1
0
1 SP
ADP5588 SENDS DATA
07673-020
1
ADP5588 NO ACK
1
ADP5588 ACK
0
ADP5588 ACK
ST
1 = READ
ADP5588 ACK
0 = WRITE
Figure 15. I2C Read and Write Sequences
0
0
1 = READ
0
0
0
0
0
0
1
READ START ADDR
1
0 ST 0
1
1
0
1
0
0
1
CHIP ADDRESS
0 ...
0
ADP5588 SENDS DATA 1
Figure 16. I2C Read Autoincrement
Rev. A | Page 14 of 28
1 ST
ADP5588 SENDS DATA N
07673-021
CHIP ADDRESS
0
STOP
0
ADP5588 NO ACK
1
ADP5588 ACK
0
ADP5588 ACK
1
ADP5588 ACK
START
1
ADP5588 ACK
0 = WRITE
ST 0
ADP5588
REGISTERS
The general behavior of registers is as follows:
•
•
•
•
All registers are 0 on reset.
All registers are read/write unless otherwise specified.
Unused bits are read as 0.
Interrupt bits are cleared by writing 1 to the flag; writing 0
or reading the flag has no effect, with the exception of the
key press, key release, and GPIO interrupt status registers,
which are cleared on a read.
Table 17.
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
Register Name
DEV_ID
CFG
INT_STAT
KEY_LCK_EC_STAT
KEY_EVENTA
KEY_EVENTB
KEY_EVENTC
KEY_EVENTD
KEY_EVENTE
KEY_EVENTF
KEY_EVENTG
KEY_EVENTH
KEY_EVENTI
KEY_EVENTJ
KP_LCK_TMR
UNLOCK1
UNLOCK2
GPIO_INT_STAT1
GPIO_INT_STAT2
GPIO_INT_STAT3
GPIO_DAT_STAT1
GPIO_DAT_STAT2
GPIO_DAT_STAT3
GPIO_DAT_OUT1
GPIO_DAT_OUT2
GPIO_DAT_OUT3
GPIO_INT_EN1
GPIO_INT_EN2
GPIO_INT_EN3
KP_GPIO1
KP_GPIO2
KP_GPIO3
GPI_EM_REG1
GPI_EM_REG2
GPI_EM_REG3
GPIO_DIR1
GPIO_DIR2
GPIO_DIR3
GPIO_INT_LVL1
GPIO_INT_LVL2
GPIO_INT_LVL3
DEBOUNCE_DIS1
DEBOUNCE_DIS2
DEBOUNCE_DIS3
GPIO_PULL1
GPIO_PULL2
Description
Device ID
Configuration Register 1
Interrupt status register
Keylock and event counter register
Key Event Register A
Key Event Register B
Key Event Register C
Key Event Register D
Key Event Register E
Key Event Register F
Key Event Register G
Key Event Register H
Key Event Register I
Key Event Register J
Keypad Unlock 1 to Keypad Unlock 2 timer
Unlock Key 1
Unlock Key 2
GPIO interrupt status
GPIO interrupt status
GPIO interrupt status
GPIO data status, read twice to clear
GPIO data status, read twice to clear
GPIO data status, read twice to clear
GPIO data out
GPIO data out
GPIO data out
GPIO interrupt enable
GPIO interrupt enable
GPIO interrupt enable
Keypad or GPIO selection
Keypad or GPIO selection
Keypad or GPIO selection
GPI Event Mode 1
GPI Event Mode 2
GPI Event Mode 3
GPIO data direction
GPIO data direction
GPIO data direction
GPIO edge/level detect
GPIO edge/level detect
GPIO edge/level detect
Debounce disable
Debounce disable
Debounce disable
GPIO pull disable
GPIO pull disable
Rev. A | Page 15 of 28
ADP5588
Address
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
Register Name
GPIO_PULL3
Not used
CMP_CFG_STAT
CMP_CONFG_SENS1
CMP_CONFG_SENS2
CMP1_LVL2_TRIP
CMP1_LVL2_HYS
CMP1_LVL3_TRIP
CMP1_LVL3_HYS
CMP2_LVL2_TRIP
CMP2_LVL2_HYS
CMP2_LVL3_TRIP
CMP2_LVL3_HYS
CMP1_ADC_DAT_R1
CMP1_ADC_DAT_R2
CMP2_ADC_DAT_R1
CMP2_ADC_DAT_R2
Description
GPIO pull disable
Not used
Comparator configuration and status register
Sensor 1 comparator configuration register
Sensor 2 comparator configuration register
L2 light sensor reference level (output falling for Sensor 1)
L2 light sensor hysteresis (active when output rising) for Sensor 1
L3 light sensor reference level (output falling for Sensor 1)
L3 light sensor hysteresis (active when output rising) for Sensor 1
L2 light sensor reference level (output falling for Sensor 2)
L2 light sensor hysteresis (active when output rising) for Sensor 2
L3 light sensor reference level (output falling for Sensor 2)
L3 light sensor hysteresis (active when output rising) for Sensor 2
Comparator 1 ADC Data Register 1
Comparator 1 ADC Data Register 2
Comparator 2 ADC Data Register 1
Comparator 2 ADC Data Register 2
REGISTER DESCRIPTIONS
Table 18. DEV_ID—Register 0x00 (Device ID)
Register Name
DEV_ID
Register Description
Device ID[3:0], MFG ID[7:4]
Bit 7
MFID3
Bit 6
MFID2
Bit 5
MFID1
Bit 4
MFID0
Bit 3
DID3
Bit 2
DID2
Bit 1
DID1
Bit 0
DID0
Table 19. CFG—Register 0x01 (Configuration Register 1)
Field
AUTO_INC
Bit
7
GPIEM_CFG
6
OVR_FLOW_M
5
INT_CFG
4
OVR_FLOW_IEN
3
K_LCK_IM
2
GPI_IEN
1
KE_IEN
0
Description
I2C autoincrement. Burst read is supported; burst write is not supported.
1: I2C autoincrement is on.
0: I2C autoincrement is off.
GPI event mode configuration.
1: GPI events are not tracked when the keypad is locked.
0: GPI events are tracked when the keypad is locked.
Overflow mode.
1: Overflow mode is on; register overflow data shifts in, starting at the last event and losing first event data.
0: Overflow mode is off; register overflow data is lost.
Interrupt configuration.
1: Processor interrupt deasserts for 50 μs and reasserts with pending key events.
0: Processor interrupt remains asserted when host tries to clear interrupt while there is a pending key event.
Overflow interrupt enable.
1: Overflow interrupt is enabled.
0: Overflow interrupt is disabled.
Keypad lock interrupt mask.
1: Keypad lock interrupt is enabled.
0: Keypad lock interrupt is disabled.
GPI interrupt enable.
1: GPI interrupt is enabled.
0: GPI interrupt is disabled.
Key events interrupt enable.
1: Key events interrupt is enabled.
0: Key events interrupt is disabled.
Rev. A | Page 16 of 28
ADP5588
Table 20. INT_STAT—Register 0x02 (Interrupt Status Register)
Field
CMP2_INT
Bit
5
CMP1_INT
4
OVR_FLOW_INT 1
3
K_LCK_INT 2
2
GPI_INT1, 3
1
KE_INT1, 3
0
Description
Comparator interrupt status. When set, write 1 to clear.
1: Comparator 2 interrupt is detected.
0: Comparator 2 interrupt is not detected.
Comparator interrupt status. When set, write 1 to clear.
1: Comparator 1 interrupt is detected.
0: Comparator 1 interrupt is not detected.
Overflow interrupt status. When set, write 1 to clear.
1: Overflow interrupt is detected.
0: Overflow interrupt is not detected.
Keylock interrupt status. When set, write 1 to clear.
1: Keylock interrupt is detected.
0: Keylock interrupt is not detected.
GPI interrupt status. When set, write 1 to clear.
1: GPI interrupt is detected.
0: GPI interrupt is not detected.
Key events interrupt status. When set, write 1 to clear.
1: Key events interrupt is detected.
0: Key events interrupt is not detected.
1
The KE_INT, GPI_INT, and OVR_FLOW_INT bits reflect the status of the interrupts when the interrupt types are enabled even if the processor interrupt is masked.
The K_LCK_INT bit is the interrupt to the processor when the keypad lock sequence is triggered.
3
If there is a pending key event or GPI interrupt in their respective registers, KE_INT does not clear until the FIFO is empty, and the GPI_INT bit does not clear until the
cause of the interrupt is resolved. The host must write a 1 to the INT bits to clear.
2
Table 21. KEY_LCK_EC_STAT—Register 0x03 (Keylock and Event Counter Register)
Field
K_LCK_EN
Bit
[6]
LCK2, LCK1
KEC 1
[5:4]
[3:0]
1
Description
0: Lock feature is disabled.
1: Lock feature is enabled.
Keypad lock status[1:0] (00 = unlocked; 11 = locked; read only bits).
Key event count of key event register.
The KEC bit indicates the key event count of key event registers that have values in the bit (KEC(0000) = 0 events, KEC(0001) = 1 event, KEC(1010) = 10 events. As the
key events are read and cleared, the state machine automatically reduces the event count on KEC.
Table 22. KEY_EVENTx—Register 0x04 to Register 0x0D (Key Event Register A to Key Event Register J) 1
Register Name
Register Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
KEY_EVENTA
(Register 0x04)
Key Event Register A status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7 ]= 0: released, 1: pressed (cleared on read)
Key Event Register C status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7]= 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KA7
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KB7
KB6
KB5
KB4
KB3
KB2
KB1
KB0
KC7
KC6
KC5
KC4
KC3
KC2
KC1
KC0
KD7
KD6
KD5
KD4
KD3
KD2
Kd1
KD0
KE7
KE6
KE5
KE4
KE3
KE2
KE1
KE0
KF7
KF6
KF5
KF4
KF3
KF2
KF1
KF0
KG7
KG6
KG5
KG4
KG3
KG2
KG1
KG0
KH7
KH6
KH5
KH4
KH3
KH2
KH1
KH0
KEY_EVENTB
(Register 0x05)
KEY_EVENTC
(Register 0x06)
KEY_EVENTD
(Register 0x07)
KEY_EVENTE 2
(Register 0x08)
KEY_EVENTF
(Register 0x09)
KEY_EVENTG
(Register 0x0A)
KEY_EVENTH
(Register 0x0B)
Rev. A | Page 17 of 28
ADP5588
Register Name
Register Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
KEY_EVENTI
(Register 0x0C)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KI7
KI6
KI5
KI4
KI3
KI2
KI1
KI0
KJ7
KJ6
KJ5
KJ4
KJ3
KJ2
KJ1
KJ0
KEY_EVENTJ
(Register 0x0D)
1
Data in key events is provided as a FIFO, where data is sequentially provided on each read, regardless of an event register read. The user can read register Event A only
for an event count or can read registers sequentially.
2
KE[6:0] reflects the value 1 to 80 for key press events and the value 97 to 114 for GPI events. For KE[7:0], 0 = key released event, 1 = key pressed event. For GPIEM_CFG,
0 reflects a change in the GPI from GPI_INT_LVL = true to GPI_INT_LVL = false; 1 reflects a change in the GPI in which the GPI_INT_LVL condition becomes true.
Table 23. KP_LCK_TMR—Register 0x0E (Keypad Unlock 1 to Keypad Unlock 2 Timer)
Register Name
Register Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
KP_LCK_TMR
(Register 0x0E)
Keypad UnLock 1 to Keypad UnLock 2 timer[2:0]
(0: disabled, 1 sec to 7 sec)
Keypad Lock Interrupt Mask Timer[7:3]
(0: disabled, 0 sec to 31 sec) 1 , 2
KIMT7
KIMT6
KIMT5
KIMT4
KIMT3
KLLT2
KLLT1
KLLT0
1
When the keypad lock interrupt mask timer is enabled, the user must press two specific keys before a keylock interrupt is generated or keypad events are recorded.
After the keypad is locked, the first time that the user presses any key, a key event interrupt is generated. No additional interrupt is generated unless both unlock key
sequences are correct; then a keylock interrupt is generated. When the interrupt mask timer is disabled (0), an interrupt is generated only when the correct full unlock
sequence is completed.
2
The Unlock 1 and Unlock 2 timer keys can be either a key sequence or GPIEM_CFG sequence. The unlock timer keys can be programmed with any value of the keys in
the keypad matrix or any GPI values that are part of the key event table. The keylock enable bit (Bit 6, Register 0x03) must be set to lock the keypad.
Table 24. UNLOCK1—Register 0x0F (Unlock Key 1)
Register Name
UNLOCK1
(Register 0x0F)
Register Description
Unlock Key 1[6:0] (contains key number
for Unlock Key 1; 0: disabled)
Bit 7
N/A
Bit 6
ULK6
Bit 5
ULK5
Bit 4
ULK4
Bit 3
ULK3
Bit 2
ULK2
Bit 1
ULK1
Bit 0
ULK0
Bit 7
N/A
Bit 6
ULK6
Bit 5
ULK5
Bit 4
ULK4
Bit 3
ULK3
Bit 2
ULK2
Bit 1
ULK1
Bit 0
ULK0
Table 25. UNLOCK2—Register 0x10 (Unlock Key 2)
Register Name
UNLOCK2
(Register 0x10)
Register Description
Unlock Key 2[6:0] (contains key number
for Unlock Key 2; 0: disabled)
Table 26. GPIO_INT_STATx—Register 0x11 to Register 0x13 (GPIO Interrupt Status)
Register Name
GPIO_INT_STAT1
(Register 0x11)
GPIO_INT_STAT2
(Register 0x12)
GPIO_INT_STAT3
(Register 0x13)
Register Description
GPIO interrupt status (used to check
GPIO interrupt status, cleared on read)
GPIO interrupt status (used to check
GPIO interrupt status, cleared on read)
GPIO interrupt status (used to check
GPIO interrupt status, cleared on read)
Bit 7
R7IS
Bit 6
R6IS
Bit 5
R5IS
Bit 4
R4IS
Bit 3
R3IS
Bit 2
R2IS
Bit 1
R1IS
Bit 0
R0IS
C7IS
C6IS
C5IS
C4IS
C3IS
C2IS
C1IS
C0IS
N/A
N/A
N/A
N/A
N/A
N/A
C9IS
C8IS
Table 27. GPIO_DAT_STATx—Register 0x14 to Register 0x16 (GPIO Data Status)
Register Name
GPIO_DAT_STAT1
(Register 0x14)
GPIO_DAT_STAT2
(Register 0x15)
GPIO_DAT_STAT3
(Register 0x16)
Register Description
GPIO data status (shows GPIO state
when read for inputs and outputs)
GPIO data status (shows GPIO state
when read for inputs and outputs)
GPIO data status (shows GPIO state
when read for inputs and outputs)
Bit 7
R7DS
Bit 6
R6DS
Bit 5
R5DS
Bit 4
R4DS
Bit 3
R3DS
Bit 2
R2DS
Bit 1
R1DS
Bit 0
R0DS
C7DS
C6DS
C5DS
C4DS
C3DS
C2DS
C1DS
C0DS
N/A
N/A
N/A
N/A
N/A
N/A
C9DS
C8DS
Rev. A | Page 18 of 28
ADP5588
Table 28. GPIO_DAT_OUTx—Register 0x17 to Register 0x19 (GPIO Data Out)
Register Name
GPIO_DAT_OUT1
(Register 0x17)
GPIO_DAT_OUT2
(Register 0x18)
GPIO_DAT_OUT3
(Register 0x19)
Register Description
GPIO data out (GPIO data to be written to
GPIO out driver, inputs are not affected). This is
needed so that the value can be written prior
to being set as an output.
GPIO data out (GPIO data to be written to
GPIO out driver, inputs are not affected). This is
needed so that the value can be written prior
to being set as an output.
GPIO data out (GPIO data to be written to
GPIO out driver, inputs are not affected). This is
needed so that the value can be written prior
to being set as an output.
Bit 7
R7DO
Bit 6
R6DO
Bit 5
R5DO
Bit 4
R4DO
Bit 3
R3DO
Bit 2
R2DO
Bit 1
R1DO
Bit 0
R0DO
C7DO
C6DO
C5DO
C4DO
C3DO
C2DO
C1DO
C0DO
N/A
N/A
N/A
N/A
N/A
N/A
C9DO
C8DO
Table 29. GPIO_INT_ENx—Register 0x1A to Register 0x1C (GPIO Interrupt Enable)
Register Name
GPIO_INT_EN1
(Register 0x1A)
GPIO_INT_EN2
(Register 0x1B)
GPIO_INT_EN3
(Register 0x1C)
Register Description
GPIO interrupt enable (enables interrupts for
GP inputs only)
GPIO interrupt enable (enables interrupts for
GP inputs only)
GPIO interrupt enable (enables interrupts for
GP inputs only)
Bit 7
R7IE
Bit 6
R6IE
Bit 5
R5IE
Bit 4
R4IE
Bit 3
R3IE
Bit 2
R2IE
Bit 1
R1IE
Bit 0
R0IE
C7IE
C6IE
C5IE
C4IE
C3IE
C2IE
C1IE
C0IE
N/A
N/A
N/A
N/A
N/A
N/A
C9IE
C8IE
Table 30. KP_GPIOx—Register 0x1D to Register 0x1F (Keypad or GPIO Selection)
Register Name
KP_GPIO1
(Register 0x1D)
KP_GPIO2
(Register 0x1E)
KP_GPIO3
(Register 0x1F)
Register Description
Keypad or GPIO selection
0: GPIO
1: KP matrix
Keypad or GPIO selection
0: GPIO
1: KP matrix
Keypad or GPIO selection
0: GPIO
1: KP matrix
Bit 7
R7
Bit 6
R6
Bit 5
R5
Bit 4
R4
Bit 3
R3
Bit 2
R2
Bit 1
R1
Bit 0
R0
C7
C6
C5
C4
C3
C2
C1
C0
N/A
N/A
N/A
N/A
N/A
N/A
C9
C8
Table 31. GPI_EM_REGx—Register 0x20 to Register 0x22 (GPI Event Mode 1 to GPI Event Mode 3)
Register Name
GPI_EM_REG1
(Register 0x20)
GPI_EM_REG2
(Register 0x21)
GPI_EM_REG3
(Register 0x22)
Register Description
GPI Event Mode Register 1
0: GPI not part of event FIFO
1: GPI part of event FIFO (R0 to R7)
GPI Event Mode Register 2
0: GPI not part of event FIFO
1: GPI part of event FIFO (C0 to C7)
GPI Event Mode Register 3
0: GPI not part of event FIFO
1: GPI part of event FIFO (C8 to C9)
Bit 7
R7_EM
Bit 6
R6_EM
Bit
R5_EM
Bit 4
R4_EM
Bit 3
R3_EM
Bit 2
R2_EM
Bit 1
R1_EM
Bit 0
R0_EM
C7_EM
C6_EM
C5_EM
C4_EM
C3_EM
C2_EM
C1_EM
C0_EM
NA
NA
NA
NA
NA
NA
C9_EM
C8_EM
Rev. A | Page 19 of 28
ADP5588
Table 32. GPIO_DIRx—Register 0x23 to Register 0x25 (GPIO Data Direction)
Register Name
GPIO_DIR1
(Register 0x23)
Register Description
GPIO data direction
0: GPIO
1: Output
GPIO data direction
0: GPIO
1: Output
GPIO data direction
0: GPIO
1: Output
GPIO_DIR2
(Register 0x24)
GPIO_DIR3
(Register 0x25)
Bit 7
R7D
Bit 6
R6D
Bit 5
R5D
Bit 4
R4D
Bit 3
R3D
Bit 2
R2D
Bit 1
R1D
Bit 0
R0D
C7D
C6D
C5D
C4D
C3D
C2D
C1D
C0D
N/A
N/A
N/A
N/A
N/A
N/A
C9D
C8D
Table 33. GPIO_INT_LVLx—Register 0x26 to Register 0x28 (GPIO Edge/Level Detect)
Register Name
GPIO_INT_LVL1
(Register 0x26)
Register Description
GPIO INT level detect
0: Low
1: High
GPIO INT level detect
0: Low
1: High
GPIO INT level detect
0: Low
1: High
GPIO_INT_LVL2
(Register 0x27)
GPIO_INT_LVL3
(Register 0x28)
Bit 7
R7IL
Bit 6
R6IL
Bit 5
R5IL
Bit 4
R4IL
Bit 3
R3IL
Bit 2
R2IL
Bit 1
R1IL
Bit 0
R0IL
C7IL
C6IL
C5IL
C4IL
C3IL
C2IL
C1IL
C0IL
N/A
N/A
N/A
N/A
N/A
N/A
C9IL
C8IL
Table 34. DEBOUNCE_DISx—Register 0x29 to Register 0x2B (Debounce Disable)
Register Name
DEBOUNCE_DIS1
(Register 0x29)
Register Description
Debounce disable (inputs)
0: Enabled
1: Disabled
Debounce disable (inputs)
0: Enabled
1: Disabled
Debounce disable (inputs)
0: Enabled
1: Disabled
DEBOUNCE_DIS2
(Register 0x2A)
DEBOUNCE_DIS3
(Register 0x2B)
Bit 7
R7DD
Bit 6
R6DD
Bit 5
R5DD
Bit 4
R4DD
Bit 3
R3DD
Bit 2
R2DD
Bit 1
R1DD
Bit 0
R0DD
C7DD
C6DD
C5DD
C4DD
C3DD
C2DD
C1DD
C0DD
N/A
N/A
N/A
N/A
N/A
N/A
C9DD
C8DD
Table 35. GPIO_PULLx—Register 0x2C to Register 0x2E (GPIO Pull Disable)
Register Name
GPIO_PULL1
(Register 0x2C)
GPIO_PULL2
(Register 0x2D)
GPIO_PULL3
(Register 0x2E)
Register Description
GPIO pull disable (remove pull-ups from inputs)
0: Pull enabled
1: Pull disabled
GPIO pull disable (remove pull-ups from inputs)
0: Pull enabled
1: Pull disabled
GPIO pull disable (remove pull-ups from inputs)
0: Pull enabled
1: Pull disabled
Bit 7
R7PD
Bit 6
R6PD
Bit 5
R5PD
Bit 4
R4PD
Bit 3
R3PD
Bit 2
R2PD
Bit 1
R1PD
Bit 0
R0PD
C7PD
C6PD
C5PD
C4PD
C3PD
C2PD
C1PD
C0PD
N/A
N/A
N/A
N/A
N/A
N/A
C9PD
C8PD
Table 36. Register 0x2F
Field
Not Used
Bit
N/A
Description
Not used
Rev. A | Page 20 of 28
ADP5588
COMPARATOR REGISTER DESCRIPTIONS
Table 37. CMP_CFG_STAT—Register 0x30 (Comparator Configuration and Status Register)
Field
CMP2_L3_OUT
Bit
7
CMP2_L2_OUT
6
CMP1_L3_OUT
5
CMP1_L2_OUT
4
CMP2_IEN
3
CMP1_IEN
2
CMP2_EN
1
CMP1_EN
0
Description
Sensor 2 Comparator L3 output.
0: Ambient light is greater than Level 3 (dark).
1: L3_CMP has detected a change in ambient light from Level 2 (office) to L3 (dark).
Sensor 2 Comparator L2 output.
0: Ambient light is greater than Level 2 (office).
1: L2_CMP has detected a change in ambient light from Level 1 (outdoor) to L2 (office).
Sensor 1 Comparator L3 output.
0: Ambient light is greater than Level 3 (dark).
1: L3_CMP has detected a change in ambient light from Level 2 (office) to L3 (dark).
Sensor 1 Comparator L2 output.
0: Ambient light is greater than Level 2 (office).
1: L2_CMP has detected a change in ambient light from Level 1 (outdoor) to L2 (office).
Sensor 2 comparator interrupt.
0: Interrupt disabled.
1: Interrupt enabled.
Sensor 1 comparator interrupt.
0: Interrupt disabled.
1: Interrupt enabled.
Sensor 2 comparator input.
0: Input disabled.
1: Input enabled.
Sensor 1 comparator input.
0: Input disabled.
1: Input enabled.
Table 38. CMP_CONFG_SENS1—Register 0x31 (Sensor 1 Comparator Configuration Register)
Field
FILT (2-0)
Bit
[7:6]
[5:3]
FORCE_RD
2
L3_EN
1
L2_EN
0
1
Description
Not used.
Programs the number of consecutive measurements required to transition the L2 and L3 levels.
FILT
Number Required
ApproximateTime (sec)
000
1
0.08
001
2
0.16
010
4
0.32
011
8
0.64
100
16
1.28
101
32
2.56
110
64
5.12
111
128
10.24
1: Forces a read of the light sensor; reset by the internal state machine after conversion is complete and
L2_OUT and L3_OUT are valid. 1
1: Enables the L3 comparator for Sensor 1 input.
0: Disables the L3 comparator for Sensor 1 input.
1: Enables the L2 comparator for Sensor 1 input.
0: Disables the L2 comparator for Sensor 1 input.
Note that the L3 comparator has priority over the L2 comparator.
When the software forces a conversion, the state machine clears the forced bit after the conversion is done and the proper registers have been updated.
Rev. A | Page 21 of 28
ADP5588
Table 39. CMP_CONFG_SENS2—Register 0x32 (Sensor 2 Comparator Configuration Register)
Field
FILT (2-0)
Bit
[7:6]
[5:3]
FORCE_RD
2
L3_EN
1
L2_EN
0
1
Description
Not used.
Programs the number of consecutive measurements required to transition the L2 and L3 levels.
FILT
Number Required
Approximate Time (sec)
000
1
0.08
001
2
0.16
010
4
0.32
011
8
0.64
100
16
1.28
101
32
2.56
110
64
5.12
111
128
10.24
1: Forces a read of the light sensor; reset by the internal state machine after conversion is complete and
L2_OUT and L3_OUT are valid. 1
1: Enables the L3 comparator for Sensor 2 input.
0: Disables the L3 comparator for Sensor 2 input.
1: Enables the L3 comparator for Sensor 2 input.
0: Disables the L3 comparator for Sensor 2 input.
Note that the L3 comparator has priority over the L2 comparator.
When the software forces a conversion, the state machine clears the forced bit after the conversion is complete and the proper registers have been updated.
Table 40. CMP1_LVL2_TRIP—Register 0x33 (L2 Light Sensor Reference Level (Output Falling for Sensor 1)
Field
L2_T7 to L2_T0
Bit
[7:0]
Description
Sensor 1 comparator Level 2 (Office) reference. If the comparator input is below this trip point, the
comparator trips and enters Level 2 (office) mode and L2_OUT is set. The programmable range is from 0 μA
to 1000 μA (0 lux to 2550 lux) in steps of 4 μA.
Table 41. CMP1_LVL2_HYS—Register 0x34 (L2 Light Sensor Hysteresis (Active When Output Rising) for Sensor 1)
Field
L2_H7 to L2_H0
Bit
[7:0]
Description
Sensor 1 comparator Level 2 (Office) hysteresis. If the comparator input is above L2_TRP + L2_HYS, the
comparator trips and enters Level 1 (outdoor) mode and L2_OUT is cleared. The programmable range is from
0 μA to 1000 μA (0 lux to 2550 lux) in steps of 4 μA.
Table 42. CMP1_LVL3_TRIP—Register 0x35 (L3 Light Sensor Reference Level (Output Falling for Sensor 1)
Field
L3_T7 to L3_T0
Bit
[7:0]
Description
Sensor 1 comparator Level 3 (Dark) reference. If the comparator input is below L3_TRP, the comparator trips
and enters Level 3 (dark) mode and L3_OUT is set. The programmable range is from 0 μA to 127.5 μA (0 lux to
318.75 lux) in steps of 0.5 μA.
Table 43. CMP1_LVL3_HYS—Register 0x36 (L3 Light Sensor Hysteresis (Active When Output Rising) for Sensor 1)
Field
L3_H
Bit
[7:0]
Description
Sensor 1 comparator Level 3 (Dark) hysteresis. If the comparator input is above L3_TRP + L3_HYS, the
comparator trips and enters Level 2 (office) mode and L3_OUT is cleared. The programmable range is from
0 μA to 127.5 μA (0 lux to 318.75 lux) in steps of 0.5 μA.
Rev. A | Page 22 of 28
ADP5588
Table 44. CMP2_LVL2_TRIP—Register 0x37 (L2 Light Sensor Reference Level (Output Falling for Sensor 2)
Field
L2_T7 to L2_T0
Bit
[7:0]
Description
Sensor 2 comparator Level 2 (Office) reference. If the comparator input is below this trip point, the
comparator trips and enters Level 2 (office) mode and L2_OUT is set. The programmable range is from 0 μA to
1000 μA (0 lux to 2550 lux) in steps of 4 μA.
Table 45. CMP2_LVL2_HYS—Register 0x38 (L2 Light Sensor Hysteresis (Active When Output Rising) for Sensor 2)
Field
L2_H7 to L2_H0
Bit
[7:0]
Description
Sensor 2 comparator Level 2 (Office) hysteresis. If the comparator input is above L2_TRP + L2_HYS, the
comparator trips and enters Level 1 (outdoor) mode and L2_OUT is cleared. The programmable range is from
0 μA to 1000 μA (0 lux to 2550 lux) in steps of 4 μA.
Table 46. CMP2_LVL3_TRIP—Register 0x39 (L3 Light Sensor Reference Level (Output Falling for Sensor 2)
Field
L3_T7 to L3_T0
Bit
[7:0]
Description
Sensor 2 Comparator Level 3 (Dark) Reference. If the comparator input is below L3_TRP, the comparator trips
and enters Level 3 (dark) mode and L3_OUT is set. The programmable range is from 0 μA to 127.5 μA (0 lux to
318.75 lux) in steps of 0.5 μA.
Table 47. CMP2_LVL3_HYS—Register 0x3A (L3 Light Sensor Hysteresis (Active When Output Rising) for Sensor 2)
Field
L3_H
Bit
[7:0]
Description
Sensor 2 comparator Level 3 (Dark) hysteresis. If the comparator input is above L3_TRP + L3_HYS, the
comparator trips and enters Level 2 (office) mode and L3_OUT is cleared. The programmable range is from
0 μA to 127.5 μA (0 lux to 318.75 lux) in steps of -.5 μA.
Table 48. CMP1_ADC_DAT_R1—Register 0x3B (Comparator 1 ADC Data Register 1)
Register Name
CMP1_ADC_DAT
Register Description
Comparator ADC data register,
Bits[7:0]
Bit 7
NA
Bit 6
NA
Bit 5
NA
Bit 4
ADC12
Bit 3
ADC11
Bit 2
ADC10
Bit 1
ADC9
Bit 0
ADC8
Bit 3
ADC3
Bit 2
ADC2
Bit 1
ADC1
Bit 0
ADC0
Bit 3
ADC11
Bit 2
ADC10
Bit 1
ADC9
Bit 0
ADC8
Bit 3
ADC3
Bit 2
ADC2
Bit 1
ADC1
Bit 0
ADC0
Table 49. CMP1_ADC_DAT_R2—Register 0x3C (Comparator 1 ADC Data Register 2) 1
Register Name
CMP1_ADC_DAT
1
Register Description
Comparator ADC data register,
Bits[7:0]
Bit 7
ADC7
Bit 6
ADC6
Bit 5
ADC5
Bit 4
ADC4
Read-only register; contains the most current 13-bit ADC data of the comparator for Sensor 1.
Table 50. CMP2_ADC_DAT_R1—Register 0x3D (Comparator 2 ADC Data Register 1)
Register Name
CMP1_ADC_DAT
Register Description
Comparator ADC Data Register
[7:0]
Bit 7
N/A
Bit 6
N/A
Bit 5
Bit 4
ADC12
Table 51. CMP2_ADC_DAT_R2—Register 0x3E (Comparator 2 ADC Data Register 2) 1
Register Name
CMP1_ADC_DAT
1
Register Description
Comparator ADC data register,
Bits[7:0]
Bit 7
ADC7
Bit 6
ADC6
Read-only register; contains the most current 13-bit ADC data of the comparator for Sensor 2.
Rev. A | Page 23 of 28
Bit 5
ADC5
Bit 4
ADC
ADP5588
APPLICATIONS INFORMATION
GND
VCC
VCC
SCL
SDA
RST
INT
REF
VOLTAGE
19
ADP5588
VCC
21
18
23
CONTROL
REGISTERS
22
CONTROL
INTERFACE
REF
VOLTAGE
20
C9
C9
C8
C8
C9
0.1µF
C8
17
0.1µF
24
8
9
R3
R2
R1
R0
C0
10
11
12
13
14
15
16
C7
7
C6
6
C5
5
C4
4
C3
3
C2
2
C1
1
R4
INT
R5
SDA
RST
R6
HOST
PROCESSOR
R7
SCL
VCC
GPL1
VCC
GPL2
ENABLE 2 (GPO)
BACKLIGHT
ENABLE (GPO)
A7 A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
BACKLIGHT
DRIVER
C7 C6 C5 C4 C3 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
E7 E6 E5 E4 E3 E2 E1 E0
F7 F6 F5 F4 F3 F2 F1 F0
G7 G6 G5 G4 G3 G2 G1 G0
H7 H6 H5 H4 H3 H2 H1 H0
I6
I5
I4
I3
I2
I1
I0
J5 J4 J3 J2 J1 J0
07673-022
I7
J7 J6
PWM OUTPUT
Figure 17. ADP5588 Detailed Application Block Diagram
APPLICATIONS OVERVIEW
BACKLIGHT CONTROL APPLICATION
The ADP5588 is designed to complement host processors in a
variety of ways. Its versatility makes it the ideal solution for
mobile platforms that require extended keypads and GPIO
expanders. The programmable registers give the designer the
flexibility to configure any or all its GPIOs in a variety of ways.
Figure 17 shows a detailed application diagram.
Although the ADP5588 is not designed with a backlight driver,
the built-in light sensor comparator inputs, with programmable
registers and trip points, give the backlight designer all the
necessary tools to control the backlight based on lighting conditions or environment. With a few I2C commands, the designer
can program the device to monitor lighting conditions and
trigger an interrupt based on preset trip points. Once programmed, the state machine uses these trip points and hysteresis
values to alert the microprocessor of any change in lighting
conditions. In addition to the L2_OUT and L3_OUT bits, four
additional registers (Register 0x3B through Register 0x3E, two
registers per light sensor) provide detailed accounts of the
internal ADC due to light condition changes. The ADC has a
full-scale current of 1000 μA and a dynamic range of 8000,
which translates to 0.125 μA or 0.3125 lux per step. These two
corresponding registers per sensor form a 13-bit register that
can be read to provide detailed translation of the light sensor
input at any instant.
KEYPAD CURRENT
Keypad current drain varies based on how many keys and how
many rows and columns are pressed during multiple key presses.
Table 52 shows typical current drain for a single press and for
two key presses.
Table 52. Typical Current Drain
Key Presses
1
2
1
Conditions1
VCC = 1.8 V to 3.0 V
VCC = 1.8 V to 3.0 V
TA = TJ = −40°C to +85°C.
Typical
55
100
Unit
μA
μA
Rev. A | Page 24 of 28
ADP5588
KEYPAD MATRIX
VCC
LIGHT
SENSORS
A0 B0 C0 D0 E0 F0 G0 H0 I0
J0
A1 B1 C1 D1 E1 F1 G1 H1 I1
J1
A2 B2 C2 D2 E2 F2 G2 H2 I2
J2
A3 B3 C3 D3 E3 F3 G3 H3 I3
J3
A4 B4 C4 D4 E4 F4 G4 H4 I4
J4
A5 B5 C5 D5 E5 F5 G5 H5 I5
J5
A6 B6 C6 D6 E6 F6 G6 H6 I6
J6
A7 B7 C7 D7 E7 F7 G7 H7 I7
J7
I2C
INT
RST
ADP5588
BACKLIGHT
ENABLE
PWM
BACKLIGHT
DRIVER
EXPANDED
GPIOs
BACKLIGHT
Figure 18. Integration Block Diagram
Rev. A | Page 25 of 28
07673-023
HOST
PROCESSOR
ADP5588
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
TOP
VIEW
3.75
BSC SQ
0.50
BSC
1.00
0.85
0.80
12° MAX
0.30
0.23
0.18
SEATING
PLANE
24 1
19
18
2.25
2.10 SQ
1.95
EXPOSED
PAD
0.50
0.40
0.30
0.80 MAX
0.65 TYP
PIN 1
INDICATOR
(BOTTOM VIEW)
13
12
7
6
0.25 MIN
2.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
072208-A
PIN 1
INDICATOR
0.60 MAX
Figure 19. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Table 53.
Model
ADP5588ACPZ-R7 1
1
Temperature Range
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = RoHS Compliant Part.
Rev. A | Page 26 of 28
Package Option
CP-24-1
ADP5588
NOTES
Rev. A | Page 27 of 28
ADP5588
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07673-0-11/08(A)
Rev. A | Page 28 of 28