INTERSIL ISL78220

6-Phase Interleaved Boost PWM Controller with Light
Load Efficiency Enhancement
ISL78220
Features
The ISL78220 6-phase controller is targeted for applications
where high efficiency (>95%) and high power are required. The
multiphase boost converter architecture uses interleaved
timing to multiply channel ripple frequency and reduce input
and output ripple. Lower ripple results in fewer input/output
capacitors and therefore lower component cost and smaller
implementation area.
• Peak Current Mode PWM Control with Adjustable Slope
Compensation
The ISL78220 has a dedicated pin to initiate the phase
dropping scheme for higher efficiency at light load by dropping
phases based on the load current, so the switching and core
losses in the converter are reduced significantly. As the load
increases, the dropped phase(s) are added back to
accommodate heavy load transients and improve efficiency.
• Adjustable Switching Frequency or External Synchronization
from 75kHz up to 1MHz Per Phase
Input current is sensed continuously by measuring the voltage
across a dedicated current sense resistor or by inductor DCR.
This current sensing provides precision channel-current
balancing, and per-phase overcurrent protection. A separate
totalizing current limit function provides overcurrent protection
for all the phases combined. This two-stage current protection
provides maximum performance and circuit reliability.
• -40°C to +125°C Operating Temperature Range
The ISL78220 can also provide for input voltage tracking via
the VREF2 pin. The comparison reference voltage will be the
lower of the VREF2 pin or the internal 2V reference. By using a
resistor network between VIN and VREF2 pin, the output
voltage can track input voltage to limit the output power during
automotive cranking conditions.
• Precision Resistor/DCR Current Sensing
• 2-, 3-, 4- or 6-Phase Operation
• Adjustable Phase Dropping/Diode Emulation/Pulse
Skipping for High Efficiency at Light Load
• Over-Temperature/Overvoltage Protection
• 2V ±1.0% Internal Reference
• Pb-Free 44 Ld 10x10 EP-TQFP Package (RoHS Compliant)
• AEC-Q100 Qualified
• TS16949 Compliant
Applications
• Automotive Power Supplies
- Start/Stop DC/DC Converter
- Fuel Pumps
- Injection System
• Audio Amplifier Power Supplies
• Telecom and Industrial Power Supplies
The ISL78220 can output a clock signal for expanding
operation to 12 phases, which offers high system flexibility.
The threshold-sensitive enable input is available to accurately
coordinate the start-up of the ISL78220 with any other voltage
rail.
0.98
WITH PHASE DROPPING
0.97
0.96
WITHOUT PHASE DROPPING
EFFICIENCY
0.95
0.94
0.93
0.92
0.91
0.90
6V INPUT, 12V OUTPUT
SYNCHRONOUS BOOST
0.89
0.88
0
5
10
15
20
OUTPUT CURRENT (A)
25
30
FIGURE 1. EFFICIENCY vs OUTPUT CURRENT vs PHASE DROPPING MODE
December 15, 2011
FN7688.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78220
Pin Configuration
VCC
GND
MODE
IOUT
VIN_SEN
VIN_OVB
VOUT_SEN
VOUT_OVB
DMAX
EN
PGOOD
ISL78220
(44 LD 10x10 EP-TQFP)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
33
2
32
VIN
COMP
3
31
ISEN6N
FB
4
30
ISEN4P
VREF2
5
29
ISEN4N
GND
6
28
ISEN2P
SLOPE
7
27
ISEN2N
PLL_COMP
8
26
ISEN5P
SYNC
9
25
ISEN5N
CLK_OUT
10
24
ISEN3P
PWM_INV
11
23
12 13 14 15 16 17 18 19 20 21 22
ISEN3N
ISEN6P
ISEN1P
ISEN1N
NC
DRIVE_EN
PWM6
PWM4
PWM2
PWM5
PWM_TRI
SS
PWM3
1
PWM1
FS
Functional Pin Description
PIN #
SYMBOL
1
FS
A resistor placed from FS to ground will set the PWM switching frequency.
DESCRIPTION
2
SS
Use this pin to set-up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start
ramp rate and in turn determine the soft-start time.
3
COMP
4
FB
The inverting input of the transconductance amplifier. A resistor network should be placed between FB pin and
output rail to set the output voltage.
5
VREF2
External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the
internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a
resistor divider network from VCC or VIN.
6
GND
7
SLOPE
8
PLL_COMP
9
SYNC
Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to
80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input
waveform. If SYNC function is not used, tie SYNC pin to GND. A 500nA current source is connected internally to
pull down the SYNC pin if it is left open.
10
CLKOUT
This pin provides a clock signal to synchronize with another ISL78220. This provides scalability and flexibility. The
rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal.
11
PWM_INV
This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation.
Pulling this pin to VCC will invert the PWM signal. This function provides the flexibility for the ISL78220 to work
with different drivers.
The output of the transconductance amplifier. Place the compensation network between COMP and GND for
compensation loop design.
Bias and reference ground for the IC.
This pin programs the slope of the internal slope compensation. A resistor should be connected from SLOPE pin
to GND. Please refer to “Adjustable Slope Compensation” on page 18 for how to choose the resistor value.
This pin serves as the compensation node for the PLL. A second order passive loop filter connected between
PLL_COMP pin and GND compensates the PLL feedback loop.
2
FN7688.0
December 15, 2011
ISL78220
Functional Pin Description (Continued)
PIN #
SYMBOL
DESCRIPTION
12
PWM_TRI
This pin enables the tri-level of the PWM output signal. Pulling this pin to GND forces the PWM output to be
traditional two level logic. Pulling the PWM_TRI pin to VCC will enable tri level PWM signals, then PWM output can
be at the 2.5V tri level condition.
13, 14, 15,
16, 17, 18
PWM1, PWM3, PWM5,
PWM2, PWM4, PWM6
Pulse width modulation outputs. Connect these pins to the PWM input pins of the external driver ICs. The number
of active channels is determined by the state of PWM3, PWM4, PWM5 and PWM6. For 2-phase operation, connect
PWM3 to VCC; similarly, connect PWM4 to VCC for 3-phase, connect PWM5 or PWM6 to VCC for 4-phase
operation.
19
DRIVE_EN
20
NC
21, 22, 23,
24, 25, 26,
27, 28, 29,
30, 31, 32
ISEN1N, ISEN1P, ISEN3N,
ISEN3P, ISEN5N, ISEN5P,
ISEN2N, ISEN2P, ISEN4N,
ISEN4P, ISEN6N, ISEN6P
The ISENxP and ISENxN pins are current sense inputs to individual differential amplifiers. The sensed current is
used as a reference for current mode control and overcurrent protection. Inactive channels should have their
respective ISENxP pins connected to VIN and ISENxN pins left open. The ISL78220 utilizes external sense resistor
current sensing method or Inductor DCR sensing method.
33
VIN
Connect input rail to this pin. This pin is connected to the internal linear regulator, generating the power necessary
to operate the chip. It is recommended the DC voltage applied to the VIN pin does not exceed 40V.
34
VCC
This pin is the output of the internal linear regulator that supplies the bias and gate voltage for the IC. A minimum
4.7µF decoupling ceramic capacitor should be connected from VCC to GND. The controller starts to operate when
the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below
the falling POR threshold. This pin can be connected directly to a +5V supply if VIN falls below 5.6V.
35
GND
Bias and reference ground for the IC.
36
MODE
37
IOUT
IOUT is the current monitor pin with an additional OCP adjustment function. An RC network needs to be placed
between IOUT and GND to ensure the proper operation. The voltage at the IOUT pin will be proportional to the input
current. If the voltage on the IOUT pin is higher than 2V, ISL78220 will go into overcurrent protection mode and
the chip will latch off until the EN pin is toggled.
38
VIN_SEN
The VIN_SEN pin is used for sensing the VIN voltage. A resistor divider network is connected between this pin and
boost power stage input voltage rail. When the voltage on VIN_SEN is greater than 2.4V, the VIN_OVB pin will be
pulled low to indicate an input overvoltage condition. The threshold voltage can be programmed by changing the
divider ratios.
39
VIN_OVB
The VIN_OVB pin is an open drain indicator of an overvoltage condition at the input. When the voltage on the
VIN_SEN pin is greater than the 2.4V threshold, the VIN_OVB pin will be pulled low.
40
VOUT_SEN
The VOUT_SEN pin is used for sensing the output voltage, a resistor divider network is connected between this pin
and output voltage rail. When the voltage on VOUT_SEN pin is greater than 2.4V, VOUT_OVB pin will be pulled low,
indicating an output overvoltage condition.
41
VOUT_OVB
The VOUT_OVB pin is an open drain indicator of an overvoltage condition at the output. When the voltage on the
VOUT_SEN pin is greater than the 2.4V threshold, the VOUT_OVB pin will be pulled low and latched, toggling VIN
or EN will reset the latch.
42
DMAX
43
EN
This pin is a threshold-sensitive enable input for the controller. Connecting the power supply input to EN pin
through an appropriate resistor divider provides a means to synchronize power-up of the controller and the
MOSFET driver ICs. When EN pin is driven above 1.2V, the ISL78220 is active depending on status of the internal
POR, and pending fault states. Driving EN pin below 1.1V will clear all fault states and the ISL78220 will soft-start
when re-enabled.
44
PGOOD
This pin is used as an indication of the end of soft-start and output regulation. It is an open-drain logic output that
is low impedance until the soft-start is completed. It will be pulled low again once the UV/OV/OC/OT conditions
are detected.
Driver enable output pin. This pin is connected to the enable pin of MOSFET drivers.
Not Connected – This pin is not electrically connected internally.
Mode selection pin. Pull this pin to logic HIGH for forced PWM mode; phase dropping/adding is inactive during
forced PWM mode. Connecting a resistor from MODE pin to GND will initialize phase dropping mode (PDM). In
PDM, a 5µA fixed reference current will flowing out of MODE pin, and the phase dropping threshold can be
programmed by adjusting the resistor value.
DMAX pin sets the maximum duty cycle of the PWM modulator. If the DMAX pin is connected to GND, the
maximum duty cycle will be set to 91.7%. Floating this pin will limit the duty cycle to 75% and connecting the
DMAX pin to VCC will limit the duty cycle to 83.3%.
Exposed Pad
It is recommended to solder the Exposed Pad to the ground plane.
3
FN7688.0
December 15, 2011
ISL78220
Ordering Information
PART NUMBER
(Notes 2, 3)
TEMP RANGE
(°C)
PART MARKING
ISL78220ANEZ-T (Note 1)
ISL78220 ANEZ
-40 to +125
ISL78220ENG1-EVZ
Evaluation Board
ISL78220EVAL1Z
Evaluation Board
PACKAGE
(Pb-free)
PKG.
DWG. #
44 Ld EP-TQFP
Q44.10x10A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78220. For more information on MSL please see tech brief TB363.
ISL78220 Block Diagram
VIN_OVB
OV_IN
VIN_SEN
VOUT_SEN
2.4V
2.4V
PGOOD
VOUT_OVB
SYNC
OV_OUT
OV_IN
UV
OC
OT
OC_ALL
OC_PH
SYNC
DETECT
REF
VIN
FAULT CONTROL
CIRCUITS
2V
5V LDO
VCC
S
Q
POR
2.4V
1.2V
CLK_OUT
DMAX
R
EN
OVER
TEMP
PLL_COMP
VCO
OV_OUT
DMAX
FB
FS
OT
UV
0.8Vref
SLOPE
COMPENSATION
5µA
SLOPE
SS
SOFT- START LOGIC
DRIVE_EN
OC_PH
R1
Gm
R2
DMAX
OT
OC
OV_OUT
FB
PH3
COMP
PH4
PH5
IOUT1
160µA
S
VREF2
CSA
ISEN1N
DUPLICATE FOR EACH
CHANNEL
2V
ISEN1P
ISEN1
20k
ZCD
Q
(FOR PH1 &
PH2 ONLY)
PWM CONTROL
PWM1
PWM_TRI
PH6
PWM_INV
PHASE DROP CONTROL
IOUT1
MODE
ADDER
MODE
IOUT6
IOUT
OC_ALL
2V
GND
4
FN7688.0
December 15, 2011
Typical Application 1: 6-Phase Synchronous Boost Converter with Sense Resistor Current
Sensing
VIN
+
EN
VCC
UGATE
5
PHASE
DRIVER
PWM
PWM1
VOUT_SEN
LGATE
VCC
GND
MODE
IOUT
VIN_SEN
VIN_OVB
PHASE 1
VIN
COMP
ISEN6N
FB
ISEN4P
VREF2
ISEN4N
ISL78220
GND
ISEN2N
ISEN1N
NC
DRIVE_EN
PWM6
ISEN4P
ISEN4N
ISEN2P
ISEN3N
ISEN2N
ISEN5P
ISEN5N
ISEN3P
ISEN3N
ISEN1P
PHASE 2
PHASE 3
FN7688.0
December 15, 2011
Note: Please see ISL78420 for an Automotive Qualified 100V synchronous boost driver.
LOAD
EN
ISEN4P
ISEN4N
PWM4
EN
ISEN5P
ISEN5N
PWM5
PHASE 4
PHASE 5
+
ISEN6P
ISEN6N
PWM6
ISEN1P
ISEN1N
VOUT
EN
ISEN3P
ISEN3N
PWM3
EN
PWM6
PWM4
PWM2
PWM5
PWM3
PWM1
PWM4
ISEN3P
PWM2
CLK_OUT
PWM5
ISEN5N
PWM3
ISEN5P
SYNC
PWM1
PLL_COMP
PWM_TRI
ISEN6N
ISEN2P
SLOPE
PWM_INV
ISEN6P
ISEN6P
EN
ISEN2P
ISEN2N
PWM2
PHASE 6
ISL78220
VCC
VOUT_SEN
SS
VOUT_OVB
EN
PGOOD
FS
DMAX
VOUT_SEN
Typical Application 2: 6-Phase Standard Boost Converter with DCR Current Sensing
L
DCR
VIN
C
R
+
VCC
VOUT_SEN
6
EN
PWM1
VCC
GND
IOUT
MODE
VIN_SEN
VIN_OVB
VIN
FB
ISEN4P
VREF2
ISEN4N
ISL78220
ISEN1N
NC
ISEN3N
ISEN1P
PWM6
PWM4
PWM2
PWM5
PWM3
PWM6
ISEN3P
DRIVE_EN
CLK_OUT
PWM4
ISEN5N
PWM2
SYNC
PWM5
ISEN5P
PWM3
PLL_COMP
PWM1
ISEN2N
PWM1
ISEN6N
ISEN4P
ISEN4N
ISEN2P
ISEN2P
SLOPE
PWM_TRI
ISEN6P
ISEN6P
ISEN6N
PWM_INV
LGATE
PHASE 1
COMP
GND
DRIVER
ISEN2N
ISEN5P
ISEN5N
ISEN3P
ISEN3N
EN
ISEN2P
ISEN2N
PWM2
EN
ISEN3P
ISEN3N
PWM3
EN
ISEN4P
ISEN4N
PWM4
EN
ISEN5P
ISEN5N
PWM5
PHASE 3
VOUT
LOAD
PHASE 4
PHASE 5
+
EN
ISEN6P
ISEN6N
PWM6
ISEN1P
ISEN1N
PHASE 2
PHASE 6
ISL78220
VCC
VOUT_SEN
SS
VOUT_OVB
EN
PGOOD
FS
DMAX
VOUT_SEN
PWM
FN7688.0
December 15, 2011
ISL78220
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to +45V
All ISEN_ Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 5V to VIN + 0.3V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
44 Ld EP-TQFP Package (Notes 4, 5) . . . . . .
28
2.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Voltage at VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +40V
All ISEN_ Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 5V to VIN + 0.3V
Voltage at VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature (Auto) . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VIN = 12V, TA = -40°C to +125°C, unless otherwise specified. Typical specifications
are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
5.6
12
40
V
8
12
mA
10
µA
5.25
V
SUPPLY INPUT
Input Voltage Range
Input Supply Current (Normal Mode)
VIN = 12V, RFS = 158kΩ (For fS = 250kHz), EN = 5V
Input Supply Current (Shutdown Mode)
VIN = 12V, RFS = 158kΩ (For fS = 250kHz), EN = 0V
INTERNAL LINEAR REGULATOR
LDO Output Voltage (VCC Pin)
VIN > 5.6V, CL = 4.7µF from VCC to GND, IVCC < 50mA
LDO Current Limit (VCC pin)
VCC = 3V, CL = 4.7µF from VCC to GND
4.75
5
200
(Note 7)
mA
POWER-ON RESET (POR) AND ENABLE
POR Threshold
EN Threshold
VCC Rising
4.4
4.5
4.6
V
VCC Falling
4.1
4.2
4.3
V
Rising
1.1
1.2
1.3
V
Hysteresis
70
mV
OSCILLATOR
Accuracy of Switching Frequency Setting
RFS = 158kΩ from FS to GND
Adjustment Range of Switching Frequency
225
250
75
FS pin voltage
275
kHz
1000
kHz
1
V
SOFT-START
Soft-Start Current
CSS = 2.2nF from SS to GND
Soft-Start Pre-Bias Voltage Range
Soft-Start Pre-Bias Voltage Accuracy
VFB = 500mV
4
6
µA
0
2
V
-25
25
mV
Soft-Start Clamp Voltage
5
3.4
V
REFERENCE VOLTAGE
System Accuracy
-40°C to +125°C, measure at FB pin, VREF2 > 2.5V
7
1.98
2
2.02
V
FN7688.0
December 15, 2011
ISL78220
Electrical Specifications
Operating Conditions: VIN = 12V, TA = -40°C to +125°C, unless otherwise specified. Typical specifications
are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
FB Pin Input Bias Current
VFB = 2V, VREF2 > 2.5V
-1
1
µA
VREF2 Pin Input Bias Current
VREF2 = 1.6V
-1
1
µA
VREF2 External Reference Voltage Range
VREF2 External Reference Voltage Accuracy
0.7
1.8
V
-40°C to +125°C, measure at FB pin, VREF2 = 1.8V
-1
1
%
-40°C to +125°C, measure at FB pin, VREF2 = 0.7V
-1.5
1.5
%
ERROR AMPLIFIER
Transconductance Gain
2
mS
Output Impedance
5
MΩ
Unity Gain Bandwidth
CCOMP = 100pF from COMP pin to GND
11
MHz
Slew Rate
CCOMP = 100pF from COMP pin to GND
2.5
V/µs
±300
µA
Output Current Capability
Maximum Output Voltage
3.5
V
Minimum Output Voltage
0.5
V
6
%
PWM CORE
Duty Cycle Matching
IISENxP = 60µA, RSLOPE = 30.1k, fS = 250kHz,
VCOMP = 2V, 6-phase, TA = +25°C
Zero Crossing Detection (ZCD) Threshold for
PWM1/PWM2
RSEN1, 2 = 750Ω
Leading Edge Blanking (Audio Mode)
VMODE = VCC, VPWM_TRI = VCC, VCOMP = 0.5V
Leading Edge Blanking (Other Mode)
VMODE<4V or VPWM_TRI = GND, VCOMP = 0.5V
SLOPE pin Voltage
-6
VISENxN = VISENxP, from VIN - 1V to VIN
ISENxN, ISENxP Common Mode Voltage Range
VIN > 12V
mV
Ts/12
(Note 8)
ns
130
385
ISENxN Bias Current
3
515
ns
650
0.3
VIN-5
mV
µA
VIN
V
0.5
V
PWMx OUTPUT
PWMx Output Voltage LOW
IPWMx = -500µA
PWMx Output Voltage HIGH
IPWMx = +500µA
4.5
PWMx Tri-State Output Voltage
IPWMx = ±100µA
2.3
PWMx Pull Down Current
During Phase Detection Time (t3 on Figure 14), VPWM = 1V
PWM3 - PWM6 Disable Threshold
During Phase Detection Time (t3 on Figure 14)
3.5
MODE Pull-up Current
VMODE = 2.4V
4.2
5.1
6
µA
V
2.5
2.7
50
V
µA
V
PHASE ADDING/DROPPING
VIOUT Threshold, 6-phase, Drop Phase 5/6
VMODE = 2.4V
1.575
1.6
1.625
V
VIOUT Threshold, 6-phase, Drop Phase 4
VMODE = 2.4V
1.175
1.2
1.225
V
VIOUT Threshold, 6-phase, Drop Phase 3
VMODE = 2.4V
0.775
0.8
0.825
V
VIOUT Threshold, 4-phase, Drop Phase 4
VMODE = 1.6V
1.175
1.2
1.225
V
VIOUT Threshold, 4-phase, Drop Phase 3
VMODE = 1.6V
0.775
0.8
0.825
V
VIOUT Threshold, 3-phase, Drop Phase 3
VMODE = 1.8V
1.175
1.2
1.225
VIOUT Threshold Hysteresis
Phase Drop Disable Threshold at MODE pin
3.5
V
40
mV
4
V
160
µA
CURRENT SENSE AND OVERCURRENT PROTECTION
Peak Current Limit for Individual Channel
IOUT Current Tolerance
IISENxP = 60µA, 6-phase
8
260
280
300
µA
FN7688.0
December 15, 2011
ISL78220
Electrical Specifications
Operating Conditions: VIN = 12V, TA = -40°C to +125°C, unless otherwise specified. Typical specifications
are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
Maximum Voltage Limit at IOUT Pin
TYP
MAX
(Note 6) UNITS
2.0
V
DMAX PIN
DMAX Threshold, High
3
V
DMAX Threshold, Low
2
DMAX Floating Voltage
V
During Phase Detection Time (t3 on Figure 14)
2.5
Max Duty Cycle, DMAX = GND
VCOMP = 3.5V
91.7
%
Max Duty Cycle, DMAX = FLOAT
VCOMP = 3.5V
75
%
Max Duty Cycle, DMAX = VCC
VCOMP = 3.5V
83.3
%
DMAX Source/Sink Current
During t3 on Figure 14
50
µA
DMAX Source/Sink Current
After t3 on Figure 14
-1
1
µA
Input Leakage Current
EN < 1V
-1
1
µA
Input Pull Down Current
EN > 2V, Pin Voltage = 2.1V
1.5
µA
0.8
V
V
PWM_TRI, PWM_INV, SYNC PIN DIGITAL LOGIC
0.4
Logic Input Low
Logic Input High
2
V
DRIVE_EN, CLK_OUT PIN
Output High Voltage
IDRIVE_EN = 500µA
Output Low Voltage
IDRIVE_EN = -500µA
4.5
V
0.5
V
VOUT SENSE PIN
Input Leakage Current
-1
Threshold Voltage
2.325
1
µA
2.4
2.475
V
1
µA
2.4
2.475
V
VIN SENSE PIN
Input Leakage Current
-1
Threshold Voltage
2.325
Hysteresis
110
mV
VOUT_OVB, VIN_OVB PIN
Leakage Current
VPIN= HIGH
Low Voltage
IPIN = 0.5mA
1
µA
0.2
V
1
µA
0.2
V
POWER-GOOD MONITOR PIN
PGOOD Leakage Current
PGOOD = HIGH
PGOOD Low Voltage
IPGOOD = 0.5mA
Overvoltage Rising Trip Point
VFB/VREF, VREF2 > 2.5V
Overvoltage Rising Hysteresis
VFB/VREF, VREF2 > 2.5V
Undervoltage Rising Trip Point
VFB/VREF, VREF2 > 2.5V
Undervoltage Rising Hysteresis
VFB/VREF, VREF2 > 2.5V
117
120
123
5
77
80
5
%
%
83
%
%
OVER-TEMPERATURE PROTECTION
Over-Temperature Trip Point
160
°C
Over-Temperature Recovery Threshold
145
°C
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise noted. Compliance to datasheet limits is assured by one or
more methods: production test, characterization and/or design.
7. Please refer to LDO current derating curve in “Internal 5V LDO Output Current Limit Derating Curves” on page 20 for IMAX vs VIN.
8. Ts = switching period = 1/(switching frequency).
9
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ISL78220
Typical Performance Curves
0.98
0.99
WITH PHASE DROPPING
0.97
0.98
0.96
0.96
EFFICIENCY
EFFICIENCY
0.95
0.94
0.93
0.92
0.91
0.94
0.93
0.91
6V INPUT, 12V OUTPUT
SYNCHRONOUS BOOST
0.89
11V INPUT, 12V OUTPUT
SYNCHRONOUS BOOST
0.90
0.89
0.88
0
5
10
15
20
OUTPUT CURRENT (A)
25
0
30
FIGURE 2. 6V INPUT EFFICIENCY vs OUTPUT CURRENT vs PHASE
DROPPING MODE
12.5
12.5
12.4
12.4
12.3
12.3
12.2
12.1
12.0
11.9
11.8
5
10
15
20
OUTPUT CURRENT (A)
25
30
FIGURE 3. 11V INPUT EFFICIENCY vs OUTPUT CURRENT vs
PHASE DROPPING MODE
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
WITHOUT PHASE DROPPING
0.95
0.92
0.90
12.2
12.1
12.0
11.9
11.8
11.7
11.7
11.6
11.5
WITH PHASE DROPPING
0.97
WITHOUT PHASE DROPPING
11.6
6V INPUT
30A OUTPUT
11.5
0
5
10
15
20
OUTPUT CURRENT (A)
25
6
30
7
8
9
INPUT VOLTAGE (V)
10
11
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
FIGURE 4. OUTPUT VOLTAGE vs OUTPUT CURRENT
5V
PHASE 1
100mV
50mV
VOUT
(AC-COUPLED)
VOUT
(AC-COUPLED)
6V INPUT, 30A OUTPUT
1µs/DIV
FIGURE 6. FULL LOAD OUTPUT RIPPLE
10
6V INPUT, 0 TO 30A TO 0 STEP LOAD
2ms/DIV
FIGURE 7. FULL STEP LOAD TRANSIENT
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ISL78220
Typical Performance Curves (Continued)
PWM1
PWM1
5V
5V
5V
5V
PWM3
PWM3
5V
5V
PWM5
PWM5
5V
5V
CLK_OUT
CLK_OUT
1µs/DIV
1µs/DIV
FIGURE 9. WAVEFORMS WITH PWM_INV = VCC
FIGURE 8. WAVEFORMS WITH PWM_INV = GND
PWM1
6V INPUT, 1A OUTPUT
5V
2V
EN
5V
5V
PWM4
VCC
5V
5V
PWM6
5A
PGOOD
5V
IL1
VOUT
PWM_INV = GND, 8V INPUT, 30A OUTPUT
1µs/DIV
5ms/DIV
FIGURE 11. ENABLE/DISABLE WAVEFORMS
FIGURE 10. FULL LOAD WAVEFORMS
6V INPUT, 30A OUTPUT
VREF2
1V
5V
VOUT
5ms/DIV
FIGURE 12. MODULATING VREF2 INPUT
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ISL78220
Operation Description
Multiphase Power Conversion
The technical challenges associated with producing a singlephase converter, which is both cost-effective and thermally viable
for high power applications have forced a change to the
cost-saving approach of multiphase solution. The ISL78220
controller helps reduce the complexity of implementation by
integrating vital functions and requiring minimal output
components.
IL1 + IL2 + IL3
IL3
PWM3
IL2
PWM2
Interleaving
The switching of each channel in a multiphase converter is timed
to be symmetrically out-of-phase with each of the other channels.
Take a 3-phase converter for example, each channel switches
1/3 cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has a
combined ripple frequency three times greater than the ripple
frequency of any one phase. In addition, the peak-to-peak
amplitude of the combined inductor current is reduced in
proportion to the number of phases (Equations 1 and 2). The
increased ripple frequency and the lower ripple amplitude mean
that the designer can use less per-channel inductance and lower
total input and output capacitance for any performance
specification.
Figure 13 illustrates the multiplicative effect on input ripple
current. The three channel currents (IL1, IL2, and IL3) combine to
form the AC ripple current and the DC input current. The ripple
component has three times the ripple frequency of each
individual channel current. Each PWM pulse is triggered 1/3 of a
cycle after the start of the PWM pulse of the previous phase.
To understand the reduction of the ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
In Equation 1, VIN and VOUT are the input and the output voltages
respectively, L is the single-channel inductor value, and fS is the
switching frequency.
( V OUT – V IN ) V IN
I P-P = -------------------------------------------L fS V
(EQ. 1)
OUT
The input capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the expression for
the peak-to-peak current after the summation of N symmetrically
phase-shifted inductor currents in Equation 2. Peak-to-peak
ripple current decreases by an amount proportional to the
number of channels. Reducing the inductor ripple current allows
the designer to use fewer or less costly input capacitors.
( V OUT – N V IN ) V IN
I C ( P-P ) = -------------------------------------------------L fS V
(EQ. 2)
OUT
IL1
PWM1
TIME
FIGURE 13. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR
3-PHASE CONVERTER
PWM Operations
The timing of each channel is set by the total number of active
channels. The default channel setting for the ISL78220 is 6, and
the switching cycle is defined as the time between PWM pulse
initiation signals of each channel. The cycle time of the pulse
initiation signal is the inversion of the switching frequency set by
the resistor between the FS pin and ground. The PWM signals
command the MOSFET drivers to turn on/off the channel
MOSFETs.
In the default 6-phase operation, the PWM2 pulse starts 1/6 of a
cycle after PWM1, the PWM3 pulse starts 1/6 of a cycle after
PWM2, the PWM4 pulse starts 1/6 of a cycle after PWM3, the
PWM5 pulse starts 1/6 of a cycle after PWM4, and the PWM6
pulse starts 1/6 of a cycle after PWM5.
Phase Selection
The ISL78220 can work in 2, 3, 4, or 6-phase configuration.
Connecting the PWM5 or PWM6 to VCC selects 4-phase
operation and the pulse times are spaced in 1/4 cycle
increments. Connecting the PWM4 to VCC selects 3-phase
operation and the pulse times are spaced in 1/3 cycle
increments. Connecting the PWM3 to VCC selects 2-phase
operation and the pulse times are spaced in 1/2 cycle
increments. Unused current sense inputs must be left floating.
Modes of Operations
The different mode of operations will be determined by the
voltage combinations of the MODE pin and the PWM_TRI pin.
If automatic phase adding/dropping function is not needed, the
MODE pin should be tied to VCC (Logic HIGH). If higher light load
efficiency is preferred, phase adding/dropping function could be
implemented by connecting the MODE pin through a resistor to
GND. A 5µA reference current will flow out of MODE pin to
generate corresponding VMODE. VMODE is used to compare with
VIOUT to determine the phase adding/dropping level.
When PWM_TRI is tied to GND (Logic LOW), the PWM outputs will
be 2-levels (i.e: 0V and 5V).When PWM_TRI is pulled to VCC
(Logic HIGH), apart from generating the 0V and 5V PWM signals,
12
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ISL78220
the PWM outputs can also generate 2.5V tri-level signal. The
external driver can identify this tri-level signal and turn off both
low side and high side output signals accordingly.
The truth table regarding VMODE and VPWM_TRI for different
mode of applications is summarized in Table 1.
TABLE 1. OPERATION MODE FOR DIFFERENT APPLICATIONS
CASE
MODE
A
1
B
C
D
Analog
1
Analog
EXTERNAL
DRIVER
IDENTIFY
PWM 2.5V TRI-LEVEL
SIGNAL?
_TRI
1
1
0
0
Yes
Yes
No
No
Prior to converter initialization, proper conditions must exist on the
enable inputs (EN pin) and VCC pin. When both conditions are met,
the controller begins soft-start. Once the output voltage is within
the proper window of operation, VPGOOD is asserted logic high.
Figure 14 shows the ISL78220 internal circuit functions before
the soft-start begins.
CIRCUIT INITIALIZATION BEFORE SOFT- START
APPLICATIONS
Synchronous boost for audio
amplifier power supply. No
phase dropping.
Applications that need
improving light load efficiency
(automatic phase dropping +
cycle-by-cycle diode emulation
+ pulse skipping).
Applications that the external
driver cannot identify tri-level
signal, no phase dropping.
Applications that the external
driver cannot identify tri-level
signal, with improved light load
efficiency (e.g., 6-phase
non-synchronous boost with
phase dropping).
Considerations for Audio
Amplifier Power Supply
Application
For multiphase boost converters used in audio amplifier
applications, it is preferred to have the following features:
1. Automatic phase dropping function is NOT needed because
the load is fast changing.
2. In car audio amplifier applications, the switching frequency is
preferred to be fixed, such that it will not interfere with
FM/AM band.
3. For synchronous boost, diode emulation is needed during
start-up in order to prevent negative current dumping to the
input side.
4. For synchronous boost, a maximum duty cycle limitation on
the synchronous FET is preferred.
Based on the above mentioned “preferred features”, For audio
amplifier applications, it does not need phase dropping/adding,
but it needs a tri-state PWM signal if synchronous boost structure
is used. Also in order to limit the maximum duty cycle of the
synchronous FET, the minimal turn on time of the active FET
(Low-side FET for boost structure) will be changed from fixed
130ns to variable time, which is 1/12 of the switching periods.
13
Operation Initialization Before
Soft-Start
EN
t
0
VCC
POR
t
0
t1
t2
t3
t4
THEN SOFT- START BEGINS
t5
PWM_DETECTION
t
0
PWM
0
t
FIGURE 14. CIRCUIT INITIALIZATION BEFORE SOFT-START
As shown on Figure 14, there are 5 time intervals before the
soft-start is initialized, they are specified as t1, t2, t3, t4 and t5,
respectively. The descriptions for each time interval are as
follows:
Time t1: The enable comparator holds the ISL78220 in shutdown
until the VEN rises above 1.2V at the beginning of t1 time period.
During t1, VVCC will gradually increase until it reaches the internal
power-on reset (POR) rising threshold. Then the system enters t2.
Time t2: During t2 time, the device initialization occurs. The time
duration for t2 is typically from 60µs to 100µs.
Time t3: The internal PWM detection signal will be asserted and
the system enters the t3 period. During t3 the ISL78220 will
detect the voltage on each PWM pin to determine the active
phase number. If PWM1 or PWM2 is accidentally pulled to VCC,
the chip will be latched off and wait for power recycling. The time
duration for t3 is fixed to around 30µs.
Time t4: When internal PWM detection signal is released the
system enters t4 period. During t4 period the ISL78220 will wait
until the internal PLL circuits are locked to the pre-set oscillator
frequency. When PLL locking is achieved, the oscillator will
generate output at CLK_OUT pin. The time duration for t4 is
typically around 0.5ms, depending on PLL_COMP pin
configuration.
Time t5: After the PLL locks the frequency, the system enters the
t5 period. During t5 the PWM outputs are held in a
high-impedance state (If VPWM_TRI = 1) or logic low (if
VPWM_TRI = 0), and the VDRIVE_EN is logic LOW to assure the
external drivers remain off. The ISL78220 has one unique
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December 15, 2011
ISL78220
feature to pre-bias the VSS based on VFB information during this
time. The duration time for t5 is around 50µs.
After t5 the soft-start process will begin. The following section will
discuss the soft-start in detail for different applications.
Time t7: Soft-start finishes at the beginning of t7. The PWMs will
change to a 2-level 0V to 5V switching signal and the
synchronous MOSFET will be turned on.
SOFT-START WAVEFORM (CASE A)
V
Soft-Start Process for Different
Modes (Refer to Table 1)
Vfb
Case A (VMODE = VCC, VPWM_TRI = VCC)
Figure 15 shows the pre-bias start-up PWM waveform for case A
in Table 1. The VPWM_TRI = VCC so that PWM can output tri-level
signal, which the external drivers need to identify, and
VMODE = VCC to ban the automatic phase dropping function.
Time t4, t5: Same as the t4, t5 in Figure 14, soft-start has not started
yet. See “Operation Initialization Before Soft-Start” on page 13 for a
detailed description.
Time t6: At the beginning of t6 the SS pin has already been
pre-biased to a value very close to the VFB, so that the internal
reference signal will start from the voltage close to FB pin. This
scheme will eliminate the internal delay for a non pre-biased
application.
The DRIVE_EN pin, which is connected to the enable pins of the
external drivers, will be pulled high when first PWM toggles at the
beginning of t6, as a results external drivers will start working.
The PWM signals will switch between tri-level and low. The driver
will only turn on the lower MOSFET accordingly, and the duty
cycle will increase gradually from 0 to steady state. The
synchronous MOSFET (Upper FET for Boost converter) will never
turn on during this time, so diode emulation can be achieved
during the start-up and in turn prevent negative current flowing
from output to input.
0
V
5V
Vref
t4 t5
NOTE: t4, t5 PERIOD ARE FROM FIGURE 5
t6
DIODE EMULATION
t7
SYNCHRONOUS
OPERATION
LOWER FET TURN ON
(PWM_INV = 0)
2.5V
PWM
0
DIODE EMULATION
SYNCHRONOUS
OPERATION
5V
(PWM_INV = 1)
2.5V
PWM
0
5V
DRIVE_EN
0
FIGURE 15. SOFT-START WAVEFORM (CASE A)
Case B (VMODE < 4V, VPWM_TRI = VCC, Light
Load Condition)
The only difference between the case A and case B start-up
waveforms is that at light load, case B can drop phases and have
cycle-by-cycle diode emulation at PWM1 and PWM2.
For the case B applications, where good light load efficiency is
always preferred, the ISL78220 provides three light load
efficiency enhancement methods. When the load current
reduces, the ISL78220 will first assert the automatic phase
dropping function to reduce the active phase number according
to the load level. The minimum active phase number is two. If the
load current further reduces even when running at two-phase
operation, the ISL78220 will assert a second method by utilizing
cycle-by-cycle diode emulation. During this time the IC will sense
the inductor current, and when the current is approximately zero
it will turn off the synchronous MOSFET. If the load current is
further reduced to deep light load operation, pulse skipping
function will kick in to optimize the overall efficiency.
14
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ISL78220
SOFT-START WAVEFORM (CASE C)
SOFT-START WAVEFORM (CASE B, LIGHT LOAD)
V
V
Vfb
Vfb
0
V
5V
Vref
t4 t5
NOTE: t4, t5 PERIOD ARE FROM FIGURE 5
0
t7
t6
DIODE EMULATION
SYNCHRONOUS
OPERATION WITH
CYCLE-BY-CYCLE
DIODE EMULATION
Vref
t4 t5
NOTE: t4, t5 PERIOD ARE FROM FIGURE 5
t6
V
5V
LOWER FET TURN ON
(PWM_INV = 0)
LOWER FET TURN ON
(PWM_INV = 0)
PWM
PWM
2.5V
0
0
DIODE EMULATION
5V
SYNCHRONOUS
OPERATION WITH
CYCLE-BY-CYCLE
DIODE EMULATION
5V
(PWM_INV = 1)
(PWM_INV = 1)
PWM
PWM
2.5V
0
0
5V
5V
DRIVE_EN
DRIVE_EN
0
0
FIGURE 16. SOFT-START WAVEFORM (CASE B, LIGHT LOAD)
FIGURE 17. SOFT-START WAVEFORM (CASE C, LIGHT LOAD)
Case C (VPWM_TRI = 0)
For applications that the driver cannot identify a tri-state PWM signal,
the VPWM_TRI should be connected to GND (Logic LOW), such that
the PWM signal will only be 2 levels between 0V and 5V. Then
DRIVE_EN pin can be connected to the EN pin of the external drivers.
DRIVE_EN will be asserted when the PWM first toggles such that the
pre-bias start up capability can be achieved. Detailed soft start for
case C is shown in Figure 17.
Time t4, t5: Same as the t4, t5 in Figure 14, soft-start has not
started yet, see “Operation Initialization Before Soft-Start” on
page 13 for detailed description.
Time t6: At the beginning of t6, the PWM signal will start to
switch between 0V and 5V. The driver will turn on the lower and
upper MOSFETs accordingly, and the duty cycle for lower MOSFET
will increase gradually from 0 to steady state. DRIVE_EN will be
pulled high when the first PWM toggles at the beginning of t6 to
enable the external drivers.
15
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ISL78220
Soft-Start Ramp Slew Rate
Calculation
The soft-start ramp slew rate SRSS is determined by the capacitor
value CSS from SS pin to GND. CSS can be calculated based on
Equation 3:
– 12
5X10
V
SR SS = ----------------------- ⎛ ------⎞
C SS ⎝ μs⎠
(EQ. 3)
Figure 18 shows the relationship between CSS and SRSS.
SOFT-START SLEW RATE (V/ms)
5.0
4.5
4.0
3.5
The maximum frequency at each PWM output is 1MHz. If the FS
pin is accidentally shorted to GND or connected to a low
impedance node, the internal circuits will detect this fault
condition and fold back the switching frequency to the 75kHz
minimal value.
The ISL78220 contains a phase lock loop (PLL) circuit and has
frequency synchronization capability by simply connecting SYNC
pin to an external square pulse waveform (typically 20% to 80%
duty cycle). In normal operation, the external SYNC frequency
needs to be at least 20% faster than the internal oscillator
frequency setting. The ISL78220 will synchronize its switching
frequency to the fundamental frequency of the input waveform.
The frequency synchronization feature will synchronize the rising
edge of the PWM1 clock signal with the rising edge of the
external clock signal at the SYNC pin.
3.0
The PLL is compensated with a series resistor-capacitor (Rc and
Cc) from the PLL_COMP pin to GND and a capacitor (Cp) from
PLL_COMP to GND. Typical values are Rc = 6.8kΩ, Cc = 6.8nF,
Cp = 1nF. The typical lock time is around 0.5ms.
2.5
2.0
1.5
1.0
0.5
0
10
Css (nF)
1
100
FIGURE 18. SOFT- START CAPACITOR vs SLEW RATE
The CLK_OUT pin provides a square pulse waveform at the
switching frequency. The amplitude is 5V with approximately
40% positive duty cycle, and the rising edge is synchronized with
the leading edge of PWM1.
Oscillator and Synchronization
The switching frequency is determined by the selection of the
frequency-setting resistor, RFS, connected from FS pin to GND.
Equation 4 is provided to assist in selecting the correct resistor
value.
R FS = 4X10
10 ⎛ 1
–8
---------- – 5X10 ⎞
⎝f
⎠
(EQ. 4)
SW
where fSW is the switching frequency of each phase. Figure 19
shows the relationship between Rfs and switching frequency.
1000
900
800
Fs (kHz)
700
600
500
400
300
200
100
0
0
100
200
300
400
500
600
RFS (kΩ)
FIGURE 19. RFS vs SWITCHING FREQUENCY
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ISL78220
Current Sensing
Inductor DCR Sensing
The ISL78220 senses the current continuously for fast response.
It supports both sense resistor and inductor DCR current sensing
methods. The sensed current for each active channel will be used
for loop control, phase current balance, individual channel
overcurrent protection and total average current protection. The
internal circuitry, shown in Figures 20 and 21, represents a single
channel. This circuitry is repeated for each channel, but may not
be active depending on the status of the PWM3, PWM4, PWM5,
and PWM6 pin voltage.
An inductor’s winding is characteristic of a distributed resistance
as measured by the DCR (Direct Current Resistance) parameter.
Peak current mode control is implemented by feeding back the
current output of the current sense amplifier (CSA) to the
regulator control loop. Individual channel peak current limit is
implemented by comparing the CSA output current with 160µA.
When the peak current limit comparator is tripped, the PWM
on-pulse is terminated and the IC is latched off.
Sense Resistor Current Sensing
(EQ. 5)
VIN
VOUT
RSEN
L
RSET
ISEN
SENSE RESISTOR
CURRENT SENSING
ISEN
CSA
ISEN(n)P
ISEN(n)N
ISL78220 INTERNAL CIRCUITS
FIGURE 20. SENSE RESISTOR CURRENT SENSING
C
ISEN
VOUT
R
RSET
INDUCTOR DCR
CURRENT SENSING
ISEN
CSA
ISEN(n)P
ISEN(n)N
FIGURE 21. INDUCTOR DCR CURRENT SENSING
Consider the inductor DCR as a separate lumped quantity, as
shown in Figure 21. The channel current IL, flowing through the
inductor, will also pass through the DCR. Equation 6 shows the
S-domain equivalent voltage across the inductor VL.
V L = I L ⋅ ( s ⋅ L + DCR )
(EQ. 6)
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 21.
The voltage on the capacitor VC, can be shown to be proportional
to the channel current IL, see Equation 7.
L
⎛ s ⋅ ----------- + 1⎞ ⋅ ( DCR ⋅ I L )
⎝ DCR
⎠
V C = ----------------------------------------------------------------( s ⋅ RC + 1 )
(EQ. 7)
If the R-C network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor VC is equal to the
voltage drop across the DCR, i.e., proportional to the channel
current.
With the internal low-offset differential current sense amplifier,
the capacitor voltage VC is replicated across the sense resistor
RSET. Therefore the current flows into the ISENxP pin is
proportional to the inductor current. Equation 8 shows that the
ratio of the channel current to the sensed current ISEN is driven
by the value of the sense resistor and the DCR of the inductor.
DCR
I SEN = I L ⋅ ------------R
SET
17
L
ISL78220 INTERNAL CIRCUITS
A sense resistor can be placed in series with the power inductor.
As shown in Figure 20, The ISL78220 acquires the channel
current information by sensing the voltage signal across the
sense resistor. Because the voltage on both the positive input
and the negative input of CSA are forced to be equal, the voltage
across RSET is equivalent to the voltage drop across the RSEN
resistor. The resulting current into the ISENxP pin is proportional
to the channel current, IL. Equation 5 for ISEN is derived where IL
is the channel current:
R SEN
I SEN = I L ⋅ ---------------R ISET
IL
DCR
VIN
(EQ. 8)
FN7688.0
December 15, 2011
ISL78220
Light Load Efficiency
Enhancement Schemes
For switching mode power supplies, the total loss is related to
both the conduction loss and the switching loss. At heavy load
the conduction loss is dominant while the switching loss will take
charge at light load condition. So, if a multiphase converter is
running at a fixed phase number for the entire load range, we will
observe that below a certain load point the total efficiency starts
to drop heavily. The ISL78220 has automatic phase dropping,
cycle-by-cycle diode emulation and pulse skipping features to
enhance the light load efficiency. By observing the total input
current on-the-fly and dropping the active phase numbers
accordingly, the overall system can achieve optimized efficiency
over the entire load range. All the above mentioned light load
enhancement features can be disabled by simply pulling the
MODE pin to VCC.
Adjustable Automatic Phase
Dropping/Adding at Light Load Condition
If the MODE pin is connected to a resistor to GND, and the voltage
on the MODE pin is lower than its disable threshold 4V, the
adjustable automatic phase dropping/adding mode will be
enabled. When the ISL78220 controller works in this mode, it
will automatically adjust the active phase number by comparing
the VMODE and VIOUT, which represents sensed total current
information. The VMODE sets the overall phase dropping
threshold, and the VIOUT is proportional to the input current,
which is in turn proportional to the load current. The smaller the
load current, the lower the voltage observed on the IOUT pin, and
the ISL78220 will drop phases in operation. Once the MODE pin
voltage is fixed, the threshold to determine how many phases are
in operation is dependent on two factors:
1. The maximum configured phase number.
2. The voltage on the IOUT pin (VIOUT).
For example, if the converter is working in 6-phase operation and
the MODE pin is set to 1.2V, in this case the converter will
monitor the VIOUT and compared to 1.2V, such that when the
VIOUT is less than 800mV (66.6% of 1.2V), it will drop from
6-phase to 4-phase; if less than 600mV (50% of 1.2V), it will drop
to 3-phase; if less than 400mV (33% of 1.2V), it will drop to
2-phase. The detailed threshold setting is shown in the table on
page 7.
If PWM_TRI is tied to VCC, the dropped phase will provide a 2.5V
tri-level signal at its PWM output. The external driver has to
identify this tri-state signal and turn off both the lower and upper
switches accordingly. For better transient response during phase
dropping, the ISL78220 will gradually reduce the duty cycle of
the phase from steady state to zero, typically within 15 switching
cycles. This gradual dropping scheme will help smooth the
change of the PWM signal and, in turn, will help to stabilize the
system when phase dropping happens.
18
The ISL78220 also has an automatic phase adding feature
similar to phase dropping, but when doing phase adding there
will not be 15 switching cycles gradually adding. It will add
phases instantly to take care of the increased load condition. The
phase adding scheme is controlled by three factors.
1. The maximum configured phase number
2. The voltage on the IOUT pin (VIOUT).
3. Individual phase current
Factors 1 and 2 are similar to the phase dropping scheme. If the
VIOUT is higher than the phase dropping threshold plus the
hysteresis voltage, the dropped phase will be added back one by
one instantly.
The above mentioned phase-adding method can take care of the
condition that the load current increases slowly. However, if the
load is fast increasing the IC will using different phase adding
scheme. The ISL78220 monitors the individual channel current
for all active phases. During phase adding the system will bring
down the pre-set channel current limit to 2/3 of its original value
(160µA). If any of the phase’s sensed current hit the 2/3 of
pre-set channel current limit threshold (i.e: 106.7µA), all the
phases will be added back instantly. After a fixed 1.5ms delay,
the phase dropping circuit will be activated and the system will
react to drop the phase number to the correct value.
During phase adding when either phase hit the pre-set channel
current limit, there will be 200µs blanking time such that perchannel OCP will not be triggered during this blanking time.
Diode Emulation at Very Light Load Condition
When phase dropping is asserted and the minimum phase
operation is 2 phases, if the load is still reducing and
synchronous boost structure is used, the ISL78220 controller will
enter into forced cycle-by-cycle diode emulation mode. The PWM
output will be tri-stated when inductor current falls to zero, such
that the synchronous MOSFET can be turned off accordingly
cycle-by-cycle for forced diode emulation. This cycle-by-cycle
diode emulation scheme will only be asserted when two
conditions are met:
1. The PWM_TRI pin voltage is logic HIGH.
2. Only two phases are running either by phase dropping or
initial configuration.
By utilizing the cycle-by-cycle diode emulation scheme in this
way, negative current is prevented and the system can still
optimize the efficiency even at very light load condition.
Pulse Skipping at Deep Light Load Condition
If the converter enters diode emulation mode and the load is still
reducing, eventually pulse skipping will occur to increase the
deep light load efficiency.
FN7688.0
December 15, 2011
ISL78220
Adjustable Slope Compensation
For a boost converter working in current mode control, slope
compensation is needed when steady state duty cycle is larger
than 50%. When slope compensation is too low the converter
can suffer from jitter or oscillation. On the other hand, over
compensation of the slope will cause the reduction of the phase
margin. Therefore, proper design of the slope compensation is
needed.
The ISL78220 features adjustable slope compensation by
setting the resistor value RSLOPE from the SLOPE pin to GND.
This function will ease the compensation design and provide
more flexibility in choosing the external components.
For current mode control, typically we need the compensation
slope mA to be 50% of the inductor current down ramp slope mB
when the lower MOSFET is off. The equation for choosing the
suitable resistor value is as follows:
6
1.136x10 xLxR SET
R SLOPE = ---------------------------------------------------- ( Ω )
( V OUT – V IN ) ( R SEN )
(EQ. 9)
Fault Monitoring and Protection
The ISL78220 actively monitors input/output voltage and current to
detect fault conditions. Fault monitors trigger protective measures
to prevent damage to the load. Common power-good indicator pin
(PGOOD pin) and VIN_OVB, VOUT_OVB pins are provided for linking
to external system monitors.
PGOOD Signal
The PGOOD pin is an open-drain logic output to indicate that the
soft-start period is completed and the output voltage is within the
specified range. This pin is pulled low during soft-start and
releases high after a successful soft-start. PGOOD will be pulled
low when a UV/OV/OC/OT fault occurs.
Input Overvoltage Detection
The ISL78220 utilizes VIN_SEN and VIN_OVB pins to deal with a
high input voltage. The VIN_SEN pin is used for sensing the input
voltage. A resistor divider network is connected between this pin
and the boost power stage input voltage rail. When the voltage
on VIN_SEN is higher than 2.4V, the open drain output VIN_OVB
pin will be pulled low to indicate an input overvoltage condition,
The VIN overvoltage sensing threshold can be programmed by
changing the resistor values, and hysteresis voltage of the
internal comparator is fixed to be 100mV.
Output Undervoltage Detection
The undervoltage threshold is set at 80% of the internal voltage
reference. When the output voltage at FB pin is below the
undervoltage threshold minus the hysteresis, PGOOD is pulled
low. When the output voltage comes back to 80% of the
reference voltage, PGOOD will return back to high.
Output Overvoltage Detection/Protection
The ISL78220 overvoltage detection circuit monitors the FB pin
and is active after time t2 in Figure 14. The OV trip point is set to
120% of the internal reference level. Once an overvoltage
condition is detected, the PGOOD will be pulled low but the
controller will continue to operate.
19
The ISL78220 also provides the flexibility for output overvoltage
protection by utilizing the VOUT_SEN and VOUT_OVB pins. The
VOUT_SEN pin is used for sensing the output voltage. A resistor
divider network is connected between this pin and the boost
power stage output voltage rail. When the voltage on VOUT_SEN
is higher than 2.4V, the open drain output VOUT_OVB will be
pulled low, and the ISL78220 IC will be latched off to indicate an
output overvoltage condition. The VOUT overvoltage sensing
threshold can be programmed by changing the resistor values.
Overcurrent Protection
ISL78220 has two levels of overcurrent protection. Each phase is
protected from an overcurrent condition by limiting its peak
current, and the combined total current is protected on an
average basis.
For the individual channel overcurrent protection, the ISL78220
continuously compares the CSA output current of each channel
with a 160µA reference current. If any channel’s current trips the
current limit comparator, the ISL78220 will be shut down.
However, during the phase adding period, the individual channel
current protection function will be blanked for 200µs, in order to
give other phases the chance to take care of the current.
IOUT pin serves for both input current monitoring and total
average current OCP functions. The CSA output current for each
channel is scaled and summed together at this pin. An RC
network should be connected between IOUT pin and GND, such
that the ripple current signal can be filtered out and converted to
a voltage signal to represent the averaged total input current. The
relationship between total input current IIN and VIOUT can be
calculated as Equation 10: (Please refer to Figure 20 for RSEN
and RSET positions).
R SEN
V IOUT = 0.75I IN -------------- R IOUT
R
SET
(EQ. 10)
When the VIOUT is higher than 2V for a consecutive 100µs, the
ISL78220 IC will be triggered to shut down. This provides
additional safety for the voltage regulator.
Equation 11 can be used to calculate the value of the resistor RIOUT
based on the desired OCP level IAVG, OCP2.
2
R IOUT = ---------------------------I AVG, OCP2
(EQ. 11)
The total average overcurrent protection scheme will not be
asserted until the soft-start pin voltage VSS reaches its clamped
value (approximately 3.5V). During the soft-start time the system
does not latch-off if per-channel or overall OC limit is reached.
Instead the individual channel current will run at its pre-set peak
current limit level.
Thermal Protection
The ISL78220 will be disabled if the die junction temperature
reaches a nominal of +160°C. It will recover when the junction
temperature falls below a +15°C hysteresis. The +15°C
hysteresis insures that the device will not be re-enabled until the
junction temperature has dropped to below about +145°C.
FN7688.0
December 15, 2011
ISL78220
Internal 5V LDO Output Current
Limit Derating Curves
Configurations for 12-Phase
Operation
ISL78220 contains an internal 5V/200mA LDO, and the input of
LDO (VIN pin) can go as high as 40V. Based on the junction to
ambient thermal resistance RJA of the package, we need to
guarantee that the maximum junction temperature should be
below +125°C TMAX. Figure 22 shows the relationship between
maximum allowed LDO output current and input voltage. The
curve is based on +35°C/W thermal resistance RJA for the
package, different curve represents different ambient
temperature TA.
For high power applications, two ISL78220 ICs can be easily
configured to support 12-phase operation. The IC that provide the
CLK_OUT signal is called master IC, and the IC that received the
CLK_OUT signal is called slave IC. Note that the two PWM1
signals are synchronized and the net effect is 6-phase operation
with double the output current.
SYSTEM
DRIVE_EN
DRIVE_EN
DRIVE_EN
CLK_OUT
SYNC
MASTER IC
COMP
FB
SS
SLAVE IC
COMP
FB
SS
FIGURE 23. CONFIGURATIONS FOR 12-PHASE OPERATION
Figure 23 shows the step-by-step setup as follows:
1. Connect the CLK_OUT pin of the master IC to the SYNC pin of
the slave IC.
FIGURE 22. ILDO(MAX) vs VIN
Dedicated VREF2 Pin for Input
Voltage Tracking
A second reference input pin, VREF2, is added to the input of the
transconductance amplifier. The ISL78220 internal reference will
automatically change to VREF2 when it is pulled below 1.8V. The
VREF2 pin can be connected to VIN through resistor network to
implement the automatic input voltage tracking function. This
function is very useful under car battery voltage cranking
conditions (such as when the car is parked and the driver is
listening to the stereo), where the full load power is typically not
needed. In this case, the ISL78220 can limit the output power by
allowing the output voltage to track the input voltage. If VREF2 is
not used, the pin should be connected to VCC.
20
2. Set the master IC’s switching frequency as desired frequency,
set the slave IC’s switching frequency 20% below the master
IC’s.
3. Connect both IC’s COMP, SS and FB pins together.
4. Both IC’s DRIVE_EN pin should be AND together to provide
system’s driver enable signal.
5. Since PGOOD, VOUT_OVB and VIN_OVB pins are open drain
structure, both IC’s PGOOD, VOUT_OVB and VIN_OVB pins can
be tied together and use one pull-up resistor to connect to
VCC.
6. If phase dropping function is needed, tie both IC’s IOUT and
MODE pins together.
FN7688.0
December 15, 2011
ISL78220
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
12/15/11
FN7688.0
CHANGE
Initial Release.
Products
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21
FN7688.0
December 15, 2011
ISL78220
Package Outline Drawing
Q44.10x10A
44 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE WITH EXPOSED PAD (EP-TQFP)
Rev 2, 12/10
4
10.00
12.00
5
D 3
3
A
12.00
10.00
4
5
4.50±0.1
B
3
0.80
EXPOSED PAD
4X
0.20 C A-B D
4X
0.20 H A-B D
4.50±0.1
TOP VIEW
BOTTOM VIEW
1.20 MAX
11/13°
7
0.05
0.20 M C A-B D
/ / 0.10 C
WITH LEAD FINISH
0.37 +0.08/-0.07
C
SIDE VIEW
0.10
SEE DETAIL "A"
0.09/0.20
0.09/0.16
0° MIN.
0.35 ±0.05
H
BASE METAL
2
1.00 ±0.05
0.05/0.15
(10.00)
0.08
R. MIN.
0.20 MIN.
DETAIL "A"
(0.45) TYP
SCALE: NONE
0.25
GAUGE
PLANE
0.60 ±0.15
0-7°
(1.00)
NOTES:
1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.
2. Datum plane H located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting line.
3. Datums A-B and D to be determined at centerline between
leads where leads exit plastic body at datum plane H.
10.00
(4.50)
(1.50) TYP
(4.50)
TYPICAL RECOMMENDED LAND PATTERN
22
4. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254mm on D1 and E1
dimensions.
5. These dimensions to be determined at datum plane H.
6. Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
7. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm total in excess of the
b dimension at maximum material condition. Dambar cannot
be located on the lower radius or the foot.
8. Controlling dimension: millimeter.
9. This outline conforms to JEDEC publication 95 registration
MS-026, variation ACB.
10. Dimensions in ( ) are for reference only.
11. The corners of the exposed heatspreader may appear different
due to the presence of the tiebars.
FN7688.0
December 15, 2011