INTERSIL ISL6326IRZ

ISL6326
®
Data Sheet
May 5, 2008
FN9262.1
4-Phase PWM Controller with 8-Bit DAC
Code Capable of Precision DCR
Differential Current Sensing
Features
The ISL6326 controls microprocessor core voltage regulation
by driving up to 4 synchronous-rectified buck channels in
parallel. Multiphase buck converter architecture uses
interleaved timing to multiply channel ripple frequency and
reduce input and output ripple currents. Lower ripple results in
fewer components, lower component cost, reduced power
dissipation, and smaller implementation area.
• Precision Multiphase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Precision Reference-Voltage Offset
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6326 utilizes Intersil’s
proprietary Active Pulse Positioning (APP) and Adaptive
Phase Alignment (APA) modulation scheme to achieve the
extremely fast transient response with fewer output capacitors.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6326
senses the output current continuously by utilizing patented
techniques to measure the voltage across the dedicated
current sense resistor or the DCR of the output inductor.
Current sensing provides the needed signals for precision
droop, channel-current balancing, and overcurrent
protection. A programmable integrated temperature
compensation function is implemented to effectively
compensate for the temperature coefficient of the current
sense element. The current limit function provides the
overcurrent protection for the individual phase.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The thresholdsensitive enable input is available to accurately coordinate
the start up of the ISL6326 with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting.
• Proprietary Active Pulse Positioning and Adaptive Phase
Alignment Modulation Scheme
• Precision Resistor or DCR Current Sensing
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
• Microprocessor Voltage Identification Input
- Dynamic VID™ Technology
- 8-Bit VID Input with Selectable VR11 Code and
Extended VR10 Code at 6.25mV Per Bit
• Thermal Monitoring
• Integrated Programmable Temperature Compensation
• Overcurrent Protection and Channel Current Limit
• Overvoltage Protection
• 2-, 3- or 4-Phase Operation
• Adjustable Switching Frequency up to 1MHz Per Phase
• Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
•
Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
(°C)
ISL6326CRZ*
ISL6326CRZ
0 to+70
ISL6326IRZ*
ISL6326IRZ
PACKAGE
(Pb-Free)
PKG.
DWG. #
40 Ld 6x6 QFN L40.6x6
-40 to +85 40 Ld 6x6 QFN L40.6x6
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6326
Pinout
2
VID7
TM
VR_HOT
VR_FAN
VR_RDY
SS
FS
EN_VTT
EN_PWR
PWM3
ISL6326
(40 LD QFN)
TOP VIEW
40
39
38
37
36
35
34
33
32
31
VID6
1
30 ISEN3+
VID5
2
29
ISEN3-
VID4
3
28
ISEN2-
VID3
4
27 ISEN2+
VID2
5
VID1
6
25
VID0
7
24 ISEN4+
VRSEL
8
23 ISEN4-
OFS
9
22
ISEN1-
DAC
10
21
ISEN1+
26 PWM2
11
12
13
14
15
16
17
18
19
20
REF
COMP
FB
IDROOP
VDIFF
RGND
VSEN
TCOMP
VCC
PWM1
GND
PWM4
FN9262.1
May 5, 2008
ISL6326
ISL6326CR Block Diagram
VDIFF
RGND
-
VSEN
+
VR_RDY
FS
CLOCK AND
RAMP GENERATOR
-
POWER-ON
RESET (POR)
0.875
+
X1
EN_VTT
N
-
0.875
+
EN_PWR
SOFT-START
AND
FAULT LOGIC
+
OVP
-
+175mV
APP AND APA
MODULATOR
PWM1
SS
VRSEL
APP AND APA
MODULATOR
VID7
PWM2
VID6
VID5
VID4
VID3
DYNAMIC
VID
D/A
APP AND APA
MODULATOR
VID2
PWM3
VID1
VID0
DAC
OFS
APP AND APA
MODULATOR
PWM4
OFFSET
REF
+
FB
-
CHANNEL
CURRENT
BALANCE
AND PEAK
CURRENT LIMIT
E/A
COMP
CHANNEL
DETECT
N
I_TRIP
ISEN1+
OCP
+
IDROOP
ISEN1ISEN2+
1
N
Σ
TEMPERATURE
COMPENSATION
CHANNEL
CURRENT
SENSE
ISEN2ISEN3+
ISEN3ISEN4+
ISEN4-
VR_HOT
THERMAL
MONITOR
TEMPERATURE
COMPENSATION
GAIN ADJUST
TM
TCOMP
VR_FAN
3
GND
FN9262.1
May 5, 2008
ISL6326
Typical Application - 4-Phase Buck Converter with External Temperature Compensation
VIN
+12V
BOOT
PVCC
THERMISTOR
NTC
+5V
°C
VCC
UGATE
PHASE
ISL6612
DRIVER
FB
COMP VCC
GND
PWM
DAC
LGATE
REF
IDROOP
VDIFF
VSEN
PWM1
RGND
VTT
EN_VTT
VIN
+12V
BOOT
ISEN1-
PVCC
ISEN1+
VR_RDY
VCC
UGATE
VID7
PHASE
ISL6326
VID6
ISL6612
VID5
DRIVER
VID4
VID3
VID2
GND
PWM
PWM2
LGATE
ISEN2-
VID1
ISEN2+
VID0
VIN
+12V
VRSEL
BOOT
PVCC
PWM3
VR_FAN
µP
LOAD
ISEN3-
VR_HOT
VCC
ISEN3+
UGATE
VIN
PHASE
ISL6612
DRIVER
EN_PWR
LGATE
GND
PWM
GND
PWM4
ISEN4ISEN4+
TCOMP
VIN
+12V
TM
OFS
FS
BOOT
SS
PVCC
+5V
VCC
UGATE
PHASE
ISL6612
°C
DRIVER
PWM
4
LGATE
GND
FN9262.1
May 5, 2008
ISL6326
Typical Application - 4-Phase Buck Converter with Integrated Temperature Compensation
+12V
+5V
VIN
BOOT1
VCC
UGATE1
PHASE1
FB
COMP
VCC
DAC
GND
REF
IDROOP
LGATE1
VDIFF
ISL6614
VSEN
DRIVER
RGND
BOOT2
ISEN1+
VTT
PVCC
5V
TO
12V
VIN
EN_VTT
ISEN1-
VR_RDY
PWM1
VID7
PWM1
UGATE2
PHASE2
VID6
VID5
ISL6326
LGATE2
VID4
VID3
PWM3
VID2
PGND
PWM2
ISEN3-
VID1
ISEN3+
VID0
VRSEL
ISEN2+
VR_FAN
ISEN2-
VR_HOT
PWM2
+12V
VIN
µP
LOAD
BOOT1
VCC
VIN
UGATE1
EN_PWR
PHASE1
PWM4
GND
GND
ISEN4-
LGATE1
ISEN4+
ISL6614
ISL6614
PVCC
TCOMP
DRIVER
BOOT2
TM
+5V
OFS
FS
5V
To
12V
VIN
SS
+5V
PWM1
UGATE2
PHASE2
NTC
LGATE2
PWM2
5
PGND
FN9262.1
May 5, 2008
ISL6326
Absolute Maximum Ratings
Thermal Information
Supply Voltage,(VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Notes 1, 2)
θJA (°C/W)
θJC (°C/W)
40 Ld QFN Package. . . . . . . . . . . . . . .
32
3.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage, (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature
ISL6326CRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6326IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°Cto+85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply
VCC = 5VDC; EN_PWR = 5VDC; RT = 100kΩ,
ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70µA
-
18
26
mA
Shutdown Supply
VCC = 5VDC; EN_PWR = 0VDC; RT = 100kΩ
-
14
21
mA
VCC Rising
4.3
4.5
4.7
V
VCC Falling
3.7
3.9
4.2
V
0.850
0.875
0.910
V
-
130
-
mV
Falling
0.720
0.745
0.775
V
Rising
0.850
0.875
0.910
V
-
130
-
mV
0.720
0.745
0.775
V
POWER-ON RESET AND ENABLE
POR Threshold
EN_PWR Threshold
Rising
Hysteresis
EN_VTT Threshold
Hysteresis
Falling
REFERENCE VOLTAGE AND DAC
System Accuracy of ISL6326CRZ
(VID = 1V to 1.6V, TJ = 0°C to +70°C)
(Note 3)
-0.5
-
0.5
%VID
System Accuracy of ISL6326CRZ
(VID = 0.5V to 1V, TJ = 0°C to +70°C)
(Note 3)
-0.9
-
0.9
%VID
System Accuracy of ISL6326IRZ
(VID = 1V to 1.6V, TJ = -40°C to +85°C)
(Note 3)
-0.6
-
0.6
%VID
System Accuracy of ISL6326IRZ
(VID = 0.5V to 1V, TJ = -40°C to +85°C)
(Note 3)
-1
-
1
%VID
-60
-40
-20
µA
VID Input Low Level
-
-
0.4
V
VID Input High Level
0.8
-
-
V
-
-
0.4
V
VID Pull-Up
VRSEL Input Low Level
6
FN9262.1
May 5, 2008
ISL6326
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.8
-
-
V
DAC Source Current
-
4
7
mA
DAC Sink Current
-
-
300
µA
REF Source Current
45
50
55
µA
REF Sink Current
45
50
55
µA
Offset resistor connected to ground
380
400
420
mV
Voltage below VCC, offset resistor connected to VCC
1.55
1.600
1.65
V
RT = 100kΩ
225
250
275
kHz
0.08
-
1.0
MHz
-
1.563
-
mV/µs
0.625
-
6.25
mV/µs
-
1.25
-
V
VRSEL Input High Level
PIN-ADJUSTABLE OFFSET
Voltage at OFS Pin
OSCILLATORS
Accuracy of Switching Frequency Setting
Adjustment Range of Switching Frequency (Note 4)
RS = 100kΩ (Notes 5, 6)
Soft-Start Ramp Rate
Adjustment Range of Soft-Start Ramp Rate (Note 4)
PWM GENERATOR
Sawtooth Amplitude
ERROR AMPLIFIER
Open-Loop Gain
RL = 10kΩ to ground (Note 4)
-
96
-
dB
Open-Loop Bandwidth
(Note 4)
-
80
-
MHz
Slew Rate
(Note 4)
-
25
-
V/µs
Maximum Output Voltage
3.8
4.3
4.9
V
Output High Voltage @ 2mA
3.6
-
-
V
Output Low Voltage @ 2mA
-
-
1.8
V
-
20
-
MHz
REMOTE-SENSE AMPLIFIER
Bandwidth
(Note 4)
Output High Current
VSEN - RGND = 2.5V
-500
-
500
µA
Output High Current
VSEN - RGND = 0.6
-500
-
500
µA
PWM OUTPUT
PWM Output Voltage LOW Threshold
ILOAD = ±500µA
-
-
0.5
V
PWM Output Voltage HIGH Threshold
ILOAD = ±500µA
4.3
-
-
V
57
60
63
µA
Overcurrent Trip Level for Average Current
72
85
98
µA
Peak Current Limit for Individual Channel
100
120
140
µA
TM Input Voltage for VR_FAN Trip
1.55
1.65
1.75
V
TM Input Voltage for VR_FAN Reset
1.85
1.95
2.05
V
TM Input Voltage for VR_HOT Trip
1.3
1.4
1.5
V
TM Input Voltage for VR_HOT Reset
1.55
1.65
1.75
V
-
-
30
µA
CURRENT SENSE AND OVERCURRENT PROTECTION
Sensed Current Tolerance (IDROOP)
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 60µA
THERMAL MONITORING AND FAN CONTROL
Leakage Current of VR_FAN
With externally pull-up resistor connected to VCC
7
FN9262.1
May 5, 2008
ISL6326
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_FAN Low Voltage
IVR_FAN = 4mA
-
-
0.4
V
Leakage Current of VR_HOT
With externally pull-up resistor connected to VCC
-
-
30
µA
VR_HOT Low Voltage
IVR_HOT = 4mA
-
-
0.4
V
VR READY AND PROTECTION MONITORS
Leakage Current of VR_RDY
With externally pull-up resistor connected to VCC
-
-
30
µA
VR_RDY Low Voltage
IVR_RDY = 4mA
-
-
0.4
V
Undervoltage Threshold
VDIFF Falling
48
50
52
%VID
VR_RDY Reset Voltage
VDIFF Rising
58
60
62
%VID
Overvoltage Protection Threshold
Before valid VID
1.250
1.275
1.300
V
150
175
200
mV
-
100
-
mV
After valid VID, the voltage above VID
Overvoltage Protection Reset Hysteresis
NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Spec limits established by characterization and are not production tested.
5. During soft-start, VDAC rises from 0V to 1.1V first and then ramp to VID voltage after receiving valid VID.
6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
8
FN9262.1
May 5, 2008
ISL6326
Functional Pin Description
VCC
Supplies the power necessary to operate the chip. The
controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply.
GND
Bias and reference ground for the IC. The bottom metal base
of ISL6326 is the GND.
EN_PWR
This pin is a threshold-sensitive enable input for the
controller. Connecting the 12V supply to EN_PWR through
an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the
ISL6326 is active depending on status of EN_VTT, the
internal POR, and pending fault states. Driving EN_PWR
below 0.745V will clear all fault states and prime the ISL6326
to soft-start when re-enabled.
EN_VTT
This pin is another threshold-sensitive enable input for the
controller. It’s typically connected to VTT output of VTT
voltage regulator in the computer mother board. When
EN_VTT is driven above 0.875V, the ISL6326 is active
depending on status of EN_PWR, the internal POR, and
pending fault states. Driving EN_VTT below 0.745V will clear
all fault states and prime the ISL6326 to soft-start when
re-enabled.
FS
Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground will set the switching
frequency. The relationship between the value of the resistor
and the switching frequency will be described by an
approximate equation.
SS
Use this pin to set up the desired start-up oscillator
frequency. A resistor, placed from SS to ground will set up
the soft-start ramp rate. The relationship between the value
of the resistor and the soft-start ramp up time will be
described by an approximate equation.
VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0
These are the inputs to the internal DAC that generates the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active pull-up outputs. All VID pins have 40µA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level. These inputs can be
pulled up externally as high as VCC plus 0.3V.
9
VRSEL
use this pin to select internal VID code. When it is connected
to GND, the extended VR10 code is selected. When it’s
floated or pulled to high, VR11 code is selected. This input
can be pulled up as high as VCC plus 0.3V.
VDIFF, VSEN, and RGND
VSEN and RGND form the precision differential remotesense amplifier. This amplifier converts the differential
voltage of the remote output to a single-ended voltage
referenced to local ground. VDIFF is the amplifier’s output
and the input to the regulation and protection circuitry.
Connect VSEN and RGND to the sense pins of the remote
load.
FB and COMP
Inverting input and output of the error amplifier respectively.
FB can be connected to VDIFF through a resistor. A properly
chosen resistor between VDIFF and FB can set the load line
(droop), when IDROOP pin is tied to FB pin. The droop scale
factor is set by the ratio of the ISEN resistors and the
inductor DCR or the dedicated current sense resistor. COMP
is tied back to FB through an external R-C network to
compensate the regulator.
DAC and REF
The DAC pin is the output of the precision internal DAC
reference. The REF pin is the positive input of the Error
Amp. In typical applications, a 1kΩ, 1% resistor is used
between DAC and REF to generate a precision offset
voltage. This voltage is proportional to the offset current
determined by the offset resistor from OFS to ground or
VCC. A capacitor is used between REF and ground to
smooth the voltage transition during Dynamic VID™
operations.
PWM1, PWM2, PWM3, PWM4
Pulse width modulation outputs. Connect these pins to the
PWM input pins of the Intersil driver IC. The number of
active channels is determined by the state of PWM3 and
PWM4. Tie PWM3 to VCC to configure for 2-phase
operation. Tie PWM4 to VCC to configure for 3-phase
operation.
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4The ISEN+ and ISEN- pins are current sense inputs to
individual differential amplifiers. The sensed current is used
for channel current balancing, overcurrent protection, and
droop regulation. Inactive channels should have their
respective current sense inputs left open (for example, open
ISEN4+ and ISEN4- for 3-phase operation).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
FN9262.1
May 5, 2008
ISL6326
inductor current. Therefore, the sense current is proportional
to the inductor current, and scaled by the DCR of the
inductor and RISEN.
VR_HOT
To match the time delay of the internal circuit, a capacitor is
needed between each ISEN+ pin and GND, as described in
“Current Sensing” on page 12.
VR_HOT is used as an indication of high VR temperature. It
is an open-drain logic output. It will be pulled low if the
measured VR temperature is less than a certain level, and
open when the measured VR temperature reaches a certain
level. A external pull-up resistor is needed.
VR_RDY
VR_FAN
VR_RDY indicates that soft-start has completed and the
output voltage is within the regulated range around VID
setting. It is an open-drain logic output. When OCP or OVP
occurs, VR_RDY will be pulled to low. It will also be pulled
low if the output voltage is below the undervoltage threshold.
VR_FAN is an output pin with open-drain logic output. It will
be pulled low if the measured VR temperature is less than a
certain level, and open when the measured VR temperature
reaches a certain level. An external pull-up resistor is
needed.
OFS
Operation
The OFS pin can be used to program a DC offset current
which will generate a DC offset voltage between the REF
and DAC pins. The offset current is generated via an
external resistor and precision internal voltage references.
The polarity of the offset is selected by connecting the
resistor to GND or VCC. For no offset, the OFS pin should
be left unterminated.
TCOMP
Temperature compensation scaling input. The voltage
sensed on the TM pin is utilized as the temperature input to
adjust ldroop and the overcurrent protection limit to
effectively compensate for the temperature coefficient of the
current sense element. To implement the integrated
temperature compensation, a resistor divider circuit is
needed with one resistor being connected from TCOMP to
VCC of the controller and another resistor being connected
from TCOMP to GND. Changing the ratio of the resistor
values will set the gain of the integrated thermal
compensation. When integrated temperature compensation
function is not used, connect TCOMP to GND.
IDROOP
IDROOP is the output pin of the sensed average channel
current which is proportional to the load current. In the
application which does not require loadline, this pin can be
connected to GND through a resistor to generate a voltage
signal, which is proportional the load current and the resistor
value. In the application which requires load line, connect
this pin to FB so that the sensed average current will flow
through the resistor between FB and VDIFF to create a
voltage drop which is proportional to load current. Tie this pin
to GND if not used.
TM
TM is an input pin for the VR temperature measurement.
Connect this pin through an NTC thermistor to GND and a
resistor to VCC of the controller. The voltage at this pin is
reverse proportional to the VR temperature. ISL6326
monitors the VR temperature based on the voltage at the TM
pin and outputs VR_HOT and VR_FAN signals.
10
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multiphase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter which is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multiphase. The
ISL6326 controller helps reduce the complexity of
implementation by integrating vital functions and requiring
minimal output components. The block diagrams on page 3,
4, and 5 provide top level views of multiphase power
conversion using the ISL6326 controller.
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out-of-phase with each of the
other channels. In a 3-phase converter, each channel
switches 1/3 cycle after the previous channel and 1/3 cycle
before the following channel. As a result, the 3-phase
converter has a combined ripple frequency 3x greater than
the ripple frequency of any one phase. In addition, the
peak-to-peak amplitude of the combined inductor currents is
reduced in proportion to the number of phases
(Equations 1 and 2). Increased ripple frequency and lower
ripple amplitude mean that the designer can use less
per-channel inductance and lower total output capacitance
for any performance specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has 3x the ripple frequency of
each individual channel current. Each PWM pulse is
terminated 1/3 of a cycle after the PWM pulse of the previous
phase. The DC components of the inductor currents combine
to feed the load.
FN9262.1
May 5, 2008
ISL6326
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
( V IN – N V OUT ) V OUT
I C ( P-P ) = ----------------------------------------------------------L fS V
IL1 + IL2 + IL3, 7A/DIV
(EQ. 2)
IN
IL1, 7A/DIV
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
PWM1, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
( V IN – V OUT ) V OUT
I PP = ----------------------------------------------------L fS V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
INPUT-CAPACITOR CURRENT, 10A/DIV
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9ARMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 18, 19 and 20 in the section entitled “Input Capacitor
Selection” on page 28 can be used to determine the
input-capacitor RMS current based on load current, duty
cycle, and the number of channels. They are provided as
aids in determining the optimal input capacitor solution.
Figure 21 shows the single phase input-capacitor RMS
current for comparison.
PWM Modulation Scheme
CHANNEL 1
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
11
The ISL6326 adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve transient
performance. APP control is a unique dual-edge PWM
modulation scheme with both PWM leading and trailing
edges being independently moved to give the best response
to transient loads. The PWM frequency, however, is constant
and set by the external resistor between the FS pin and
GND. To further improve the transient response, the
ISL6326 also implements Intersil's proprietary Adaptive
Phase Alignment (APA) technique. APA, with sufficiently
large load step currents, can turn on all phases together.
With both APP and APA control, ISL6326 can achieve
excellent transient performance and reduce the demand on
the output capacitors.
Under steady state conditions the operation of the ISL6326
PWM modulator appears to be that of a conventional trailing
edge modulator. Conventional analysis and design methods
can therefore be used for steady state and small signal
operation.
PWM Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6326 is four.
The switching cycle is defined as the time between PWM
pulse termination signals of each channel. The cycle time of
the pulse signal is the inverse of the switching frequency set
FN9262.1
May 5, 2008
ISL6326
Connecting PWM4 to VCC selects three channel operation
and the pulse times are spaced in 1/3 cycle increments. If
PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse happens 1/2 of a cycle after
PWM pulse.
The voltage on the capacitor VC, can be shown to be
proportional to the channel current IL, see Equation 5.
L
⎛ s ⋅ ------------+ 1⎞ ⋅ ( DCR ⋅ I L )
⎝ DCR
⎠
V C = --------------------------------------------------------------------( s ⋅ RC + 1 )
(EQ. 5)
If the RC network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor VC is equal to
the voltage drop across the DCR, i.e., proportional to the
channel current.
VIN
I (s)
L
Switching Frequency
L
Switching frequency is determined by the selection of the
frequency-setting resistor, RT, which is connected from FS
pin to GND (see the figures labeled Typical Applications on
page 4 and page 5). Equation 3 is provided to assist in
selecting the correct resistor value.
ISL6605
+
INDUCTOR
VL
+
VC(s)
R
10
2.5X10
R T = -------------------------F SW
COUT
C
PWM(n)
(EQ. 3)
ISL6326 INTERNAL CIRCUIT
where FSW is the switching frequency of each phase.
Current Sensing
RISEN(n)
(PTC)
In
ISL6326 senses the current continuously for fast response.
ISL6326 supports inductor DCR sensing, or resistive
sensing techniques. The associated channel current sense
amplifier uses the ISEN inputs to reproduce a signal
proportional to the inductor current, IL. The sense current,
ISEN, is proportional to the inductor current. The sensed
current is used for current balance, load-line regulation, and
overcurrent protection.
The internal circuitry, shown in Figures 3 and 4, represents
one channel of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 and PWM4
pins, as described in the “PWM Operation” on page 11.
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed
resistance as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 3. The
channel current IL, flowing through the inductor, will also
pass through the DCR. Equation 4 shows the s-domain
equivalent voltage across the inductor VL.
V L = I L ⋅ ( s ⋅ L + DCR )
VOUT
DCR
-
For 4-channel operation, the channel firing order is 4-3-2-1:
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and
PWM1 delays another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is 3-2-1.
A simple RC network across the inductor extracts the DCR
voltage, as shown in Figure 3.
-
by the resistor between the FS pin and ground. The PWM
signals command the MOSFET driver to turn on/off the
channel MOSFETs.
(EQ. 4)
CURRENT
ISEN-(n)
SENSE
+
-
ISEN+(n)
CT
DCR
I SEN = I ------------------LR
ISEN
FIGURE 3. DCR SENSING CONFIGURATION
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
Therefore, the current out of ISEN+ pin (ISEN), is
proportional to the inductor current.
Because of the internal filter at ISEN- pin, one capacitor, CT,
is needed to match the time delay between the ISEN- and
ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT) close to 27ns.
Equation 6 shows that the ratio of the channel current to the
sensed current (ISEN) is driven by the value of the sense
resistor and the DCR of the inductor.
DCR
I SEN = I L ⋅ -----------------R
(EQ. 6)
ISEN
12
FN9262.1
May 5, 2008
ISL6326
RESISTIVE SENSING
For accurate current sense, a dedicated current-sense
resistor RSENSE in series with each output inductor can
serve as the current sense element (see Figure 4). This
technique is more accurate, but reduces overall converter
efficiency due to the additional power loss on the current
sense element RSENSE.
The same capacitor CT is needed to match the time delay
between ISEN- and ISEN+ signals. Select the proper CT to
keep the time constant of RISEN and CT (RISEN x CT) close
to 27ns.
Equation 7 shows the ratio of the channel current to the
sensed current ISEN.
R SENSE
I SEN = I L ⋅ ----------------------R
(EQ. 7)
ISEN
L
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 5 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6326 to include the combined tolerances of each of
these elements.
The output of the error amplifier (VCOMP) is compared to
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitry, which
control voltage regulation are illustrated in Figure 5.
IL
EXTERNAL CIRCUIT
R C CC
COMP
RSENSE VOUT
COUT
DAC
RREF
ISL6326 INTERNAL CIRCUIT
RISEN(n)
In
ISL6326 INTERNAL CIRCUIT
REF
CREF
+
-
FB
CURRENT
ISEN-(n)
SENSE
RFB
+
ISEN+(n)
IDROOP
+
VDROOP
VDIFF
CT
R SENSE
I
SEN = I L ------------------------R ISEN
VOUT+
FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS
The inductor DCR value will increase as the temperature
increases. Therefore the sensed current will increase as the
temperature of the current sense element increases. In order
to compensate the temperature effect on the sensed current
signal, a Positive Temperature Coefficient (PTC) resistor can
be selected for the sense resistor RISEN, or the integrated
temperature compensation function of ISL6326 should be
utilized. The integrated temperature compensation function
is described in “Temperature Compensation” on page 22.
Channel-Current Balance
The sensed current In from each active channel is summed
together and divided by the number of active channels. The
resulting average current (IAVG) provides a measure of the
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
13
IAVG
VCOMP
ERROR AMPLIFIER
VOUT-
VSEN
+
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The ISL6326 incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input (VSEN) and inverting input
(RGND) of the remote-sense amplifier. The remote-sense
output (VDIFF) is connected to the inverting input of the error
amplifier through an external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the eight 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 45µA pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
FN9262.1
May 5, 2008
ISL6326
diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
can augment the pull-up current sources if case leakage into
the driving device is greater than 45µA.
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID6 VOLTAGE
VID4 VID3 VID2 VID1 VID0 VID5
(V)
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID6 VOLTAGE
VID4 VID3 VID2 VID1 VID0 VID5
(V)
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
1
0
0
1
1
1
1
1.37500
1
0
0
1
1
1
0
1.36875
1
0
1
0
0
0
1
1.36250
0
1
0
1
0
1
1
1.60000
1
0
1
0
0
0
0
1.35625
0
1
0
1
0
1
0
1.59375
1
0
1
0
0
1
1
1.35000
0
1
0
1
1
0
1
1.58750
1
0
1
0
0
1
0
1.34375
0
1
0
1
1
0
0
1.58125
1
0
1
0
1
0
1
1.33750
0
1
0
1
1
1
1
1.57500
1
0
1
0
1
0
0
1.33125
0
1
0
1
1
1
0
1.56875
1
0
1
0
1
1
1
1.32500
0
1
1
0
0
0
1
1.56250
1
0
1
0
1
1
0
1.31875
0
1
1
0
0
0
0
1.55625
1
0
1
1
0
0
1
1.31250
0
1
1
0
0
1
1
1.55000
1
0
1
1
0
0
0
1.30625
0
1
1
0
0
1
0
1.54375
1
0
1
1
0
1
1
1.30000
0
1
1
0
1
0
1
1.53750
1
0
1
1
0
1
0
1.29375
0
1
1
0
1
0
0
1.53125
1
0
1
1
1
0
1
1.28750
0
1
1
0
1
1
1
1.52500
1
0
1
1
1
0
0
1.28125
0
1
1
0
1
1
0
1.51875
1
0
1
1
1
1
1
1.27500
0
1
1
1
0
0
1
1.51250
1
0
1
1
1
1
0
1.26875
0
1
1
1
0
0
0
1.50625
1
1
0
0
0
0
1
1.26250
0
1
1
1
0
1
1
1.50000
1
1
0
0
0
0
0
1.25625
0
1
1
1
0
1
0
1.49375
1
1
0
0
0
1
1
1.25000
0
1
1
1
1
0
1
1.4875
1
1
0
0
0
1
0
1.24375
0
1
1
1
1
0
0
1.48125
1
1
0
0
1
0
1
1.23750
0
1
1
1
1
1
1
1.47500
1
1
0
0
1
0
0
1.23125
0
1
1
1
1
1
0
1.46875
1
1
0
0
1
1
1
1.22500
1
0
0
0
0
0
1
1.46250
1
1
0
0
1
1
0
1.21875
1
0
0
0
0
0
0
1.45625
1
1
0
1
0
0
1
1.21250
1
0
0
0
0
1
1
1.45000
1
1
0
1
0
0
0
1.20625
1
0
0
0
0
1
0
1.44375
1
1
0
1
0
1
1
1.20000
1
0
0
0
1
0
1
1.43750
1
1
0
1
0
1
0
1.19375
1
0
0
0
1
0
0
1.43125
1
1
0
1
1
0
1
1.18750
1
0
0
0
1
1
1
1.42500
1
1
0
1
1
0
0
1.18125
1
0
0
0
1
1
0
1.41875
1
1
0
1
1
1
1
1.17500
1
0
0
1
0
0
1
1.41250
1
1
0
1
1
1
0
1.16875
1
0
0
1
0
0
0
1.40625
1
1
1
0
0
0
1
1.16250
1
0
0
1
0
1
1
1.40000
1
1
1
0
0
0
0
1.15625
1
0
0
1
0
1
0
1.39375
1
1
1
0
0
1
1
1.15000
1
0
0
1
1
0
1
1.38750
1
1
1
0
0
1
0
1.14375
1
0
0
1
1
0
0
1.38125
1
1
1
0
1
0
1
1.13750
14
FN9262.1
May 5, 2008
ISL6326
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID6 VOLTAGE
VID4 VID3 VID2 VID1 VID0 VID5
(V)
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID4 VID3 VID2 VID1 VID0 VID5
VID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
(V)
1
1
1
0
1
0
0
1.13125
0
0
1
1
1
0
1
0.91250
1
1
1
0
1
1
1
1.12500
0
0
1
1
1
0
0
0.90625
1
1
1
0
1
1
0
1.11875
0
0
1
1
1
1
1
0.90000
1
1
1
1
0
0
1
1.11250
0
0
1
1
1
1
0
0.89375
1
1
1
1
0
0
0
1.10625
0
1
0
0
0
0
1
0.88750
1
1
1
1
0
1
1
1.10000
0
1
0
0
0
0
0
0.88125
1
1
1
1
0
1
0
1.09375
0
1
0
0
0
1
1
0.87500
1
1
1
1
1
0
1
OFF
0
1
0
0
0
1
0
0.86875
1
1
1
1
1
0
0
OFF
0
1
0
0
1
0
1
0.86250
1
1
1
1
1
1
1
OFF
0
1
0
0
1
0
0
0.85625
1
1
1
1
1
1
0
OFF
0
1
0
0
1
1
1
0.85000
0
0
0
0
0
0
1
1.08750
0
1
0
0
1
1
0
0.84375
0
0
0
0
0
0
0
1.08125
0
1
0
1
0
0
1
0.83750
0
0
0
0
0
1
1
1.07500
0
1
0
1
0
0
0
0.83125
0
0
0
0
0
1
0
1.06875
0
0
0
0
1
0
1
1.06250
0
0
0
0
1
0
0
1.05625
0
0
0
0
1
1
1
1.05000
0
0
0
0
1
1
0
1.04375
0
0
0
1
0
0
1
1.03750
0
0
0
1
0
0
0
1.03125
0
0
0
1
0
1
1
1.02500
0
0
0
1
0
1
0
1.01875
0
0
0
1
1
0
1
1.01250
0
0
0
1
1
0
0
1.00625
0
0
0
1
1
1
1
1.00000
0
0
0
1
1
1
0
0.99375
0
0
1
0
0
0
1
0.9875
0
0
1
0
0
0
0
0.98125
0
0
1
0
0
1
1
0.97500
0
0
1
0
0
1
0
0.96875
0
0
1
0
1
0
1
0.9625
0
0
1
0
1
0
0
0.95625
0
0
1
0
1
1
1
0.95000
0
0
1
0
1
1
0
0.94375
0
0
1
1
0
0
1
0.93750
0
0
1
1
0
0
0
0.93125
0
0
1
1
0
1
1
0.92500
0
0
1
1
0
1
0
0.91875
15
TABLE 2. VR11 VID 8-BIT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0
0
0
0
1
1
1
1
1.51875
0
0
0
1
0
0
0
0
1.51250
0
0
0
1
0
0
0
1
1.50625
0
0
0
1
0
0
1
0
1.50000
0
0
0
1
0
0
1
1
1.49375
0
0
0
1
0
1
0
0
1.48750
0
0
0
1
0
1
0
1
1.48125
0
0
0
1
0
1
1
0
1.47500
FN9262.1
May 5, 2008
ISL6326
TABLE 2. VR11 VID 8-BIT (Continued)
TABLE 2. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
1
1
1
1.21875
0
0
0
1
1
0
0
0
1.46250
0
1
0
0
0
0
0
0
1.21250
0
0
0
1
1
0
0
1
1.45625
0
1
0
0
0
0
0
1
1.20625
0
0
0
1
1
0
1
0
1.45000
0
1
0
0
0
0
1
0
1.20000
0
0
0
1
1
0
1
1
1.44375
0
1
0
0
0
0
1
1
1.19375
0
0
0
1
1
1
0
0
1.43750
0
1
0
0
0
1
0
0
1.18750
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
1
0
1
1.18125
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
1
1
0
1.17500
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
1
1
1
1.16875
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
1
0
0
0
1.16250
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
1
0
0
1
1.15625
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
1
0
1
0
1.15000
0
0
1
0
0
0
1
1
1.39375
0
1
0
0
1
0
1
1
1.14375
0
0
1
0
0
1
0
0
1.38750
0
1
0
0
1
1
0
0
1.13750
0
0
1
0
0
1
0
1
1.38125
0
1
0
0
1
1
0
1
1.13125
0
0
1
0
0
1
1
0
1.37500
0
1
0
0
1
1
1
0
1.12500
0
0
1
0
0
1
1
1
1.36875
0
1
0
0
1
1
1
1
1.11875
0
0
1
0
1
0
0
0
1.36250
0
1
0
1
0
0
0
0
1.11250
0
0
1
0
1
0
0
1
1.35625
0
1
0
1
0
0
0
1
1.10625
0
0
1
0
1
0
1
0
1.35000
0
1
0
1
0
0
1
0
1.10000
0
0
1
0
1
0
1
1
1.34375
0
1
0
1
0
0
1
1
1.09375
0
0
1
0
1
1
0
0
1.33750
0
1
0
1
0
1
0
0
1.08750
0
0
1
0
1
1
0
1
1.33125
0
1
0
1
0
1
0
1
1.08125
0
0
1
0
1
1
1
0
1.32500
0
1
0
1
0
1
1
0
1.07500
0
0
1
0
1
1
1
1
1.31875
0
1
0
1
0
1
1
1
1.06875
0
0
1
1
0
0
0
0
1.31250
0
1
0
1
1
0
0
0
1.06250
0
0
1
1
0
0
0
1
1.30625
0
1
0
1
1
0
0
1
1.05625
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
0
1.26250
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
0
1.22500
0
1
1
0
0
1
1
0
0.97500
16
FN9262.1
May 5, 2008
ISL6326
TABLE 2. VR11 VID 8-BIT (Continued)
TABLE 2. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0
1
1
0
0
1
1
1
0.96875
1
0
0
0
1
1
1
1
0.71875
0
1
1
0
1
0
0
0
0.96250
1
0
0
1
0
0
0
0
0.71250
0
1
1
0
1
0
0
1
0.95625
1
0
0
1
0
0
0
1
0.70625
0
1
1
0
1
0
1
0
0.95000
1
0
0
1
0
0
1
0
0.70000
0
1
1
0
1
0
1
1
0.94375
1
0
0
1
0
0
1
1
0.69375
0
1
1
0
1
1
0
0
0.93750
1
0
0
1
0
1
0
0
0.68750
0
1
1
0
1
1
0
1
0.93125
1
0
0
1
0
1
0
1
0.68125
0
1
1
0
1
1
1
0
0.92500
1
0
0
1
0
1
1
0
0.67500
0
1
1
0
1
1
1
1
0.91875
1
0
0
1
0
1
1
1
0.66875
0
1
1
1
0
0
0
0
0.91250
1
0
0
1
1
0
0
0
0.66250
0
1
1
1
0
0
0
1
0.90625
1
0
0
1
1
0
0
1
0.65625
0
1
1
1
0
0
1
0
0.90000
1
0
0
1
1
0
1
0
0.65000
0
1
1
1
0
0
1
1
0.89375
1
0
0
1
1
0
1
1
0.64375
0
1
1
1
0
1
0
0
0.88750
1
0
0
1
1
1
0
0
0.63750
0
1
1
1
0
1
0
1
0.88125
1
0
0
1
1
1
0
1
0.63125
0
1
1
1
0
1
1
0
0.87500
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
0
1
1
1
0.86875
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
1
0
0
0
0.86250
1
0
1
0
0
0
0
0
0.61250
0
1
1
1
1
0
0
1
0.85625
1
0
1
0
0
0
0
1
0.60625
0
1
1
1
1
0
1
0
0.85000
1
0
1
0
0
0
1
0
0.60000
0
1
1
1
1
0
1
1
0.84375
1
0
1
0
0
0
1
1
0.59375
0
1
1
1
1
1
0
0
0.83750
1
0
1
0
0
1
0
0
0.58750
0
1
1
1
1
1
0
1
0.83125
1
0
1
0
0
1
0
1
0.58125
0
1
1
1
1
1
1
0
0.82500
1
0
1
0
0
1
1
0
0.57500
0
1
1
1
1
1
1
1
0.81875
1
0
1
0
0
1
1
1
0.56875
1
0
0
0
0
0
0
0
0.81250
1
0
1
0
1
0
0
0
0.56250
1
0
0
0
0
0
0
1
0.80625
1
0
1
0
1
0
0
1
0.55625
1
0
0
0
0
0
1
0
0.80000
1
0
1
0
1
0
1
0
0.55000
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
1
0
0.77500
1
0
1
0
1
1
1
0
0.52500
1
0
0
0
0
1
1
1
0.76875
1
0
1
0
1
1
1
1
0.51875
1
0
0
0
1
0
0
0
0.76250
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
1
0
0.75000
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
0
1
1
0.74375
1
1
1
1
1
1
1
0
OFF
1
0
0
0
1
1
0
0
0.73750
1
1
1
1
1
1
1
1
OFF
1
0
0
0
1
1
0
1
0.73125
1
0
0
0
1
1
1
0
0.72500
17
FN9262.1
May 5, 2008
ISL6326
Load-Line Regulation
Output Voltage Offset Programming
Some microprocessor manufacturers require a
precisely-controlled output resistance. This dependence of
output voltage on load current is often termed “droop” or
“load line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
The ISL6326 allows the designer to accurately adjust the
offset voltage. When a resistor, ROFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into OFS. If
ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of OFS. A resistor
between DAC and REF, RREF, is selected so that the
product (IOFS x ROFS) is equal to the desired offset voltage.
These functions are shown in Figure 6.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to set ROFS:
For Positive Offset (connect ROFS to VCC):
1.6 × R REF
R OFS = -----------------------------V OFFSET
(EQ. 11)
For Negative Offset (connect ROFS to GND):
0.4 × R REF
R OFS = -----------------------------V OFFSET
(EQ. 12)
As shown in Figure 5, a current proportional to the average
current of all active channels (IAVG) flows from FB through a
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as Equation 8:
V DROOP = I AVG R FB
FB
DYNAMIC
VID D/A
(EQ. 8)
DAC
RREF
E/A
⎛ I OUT R X
⎞
- ------------------ R FB⎟
V OUT = V REF – V OFS – ⎜ -----------⎝ N R ISEN
⎠
REF
+
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed in Equation 9.
CREF
+
VCC
OR
GND
(EQ. 9)
-
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the sense resistor connected to
the ISEN+ pin, and RFB is the feedback resistor, N is the
active channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
R FB R X
R LL = ----------------------------N R ISEN
-
+
1.6V
+
0.4V
VCC
ROFS
+
-
OFS
ISL6326B
GND
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
(EQ. 10)
18
FN9262.1
May 5, 2008
ISL6326
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core voltage
regulator.
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
ISL6326 INTERNAL CIRCUIT
POR
CIRCUIT
ENABLE
COMPARATOR
+
10kΩ
EN_PWR
910Ω
0.875V
+
EN_VTT
-
Assuming the microprocessor controls the VID change at
1-bit every tVID, the relationship between the time constant
of RREF and CREF network and tVID is given by Equation 13:
(EQ. 13)
+12V
VCC
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of RREF and CREF, as shown in Figure 6, can be
used. The selection of RREF is based on the desired offset
voltage as detailed above in “Output Voltage Offset
Programming” on page 18. The selection of CREF is based
on the time duration for 1-bit VID change and the allowable
delay time.
C REF R REF = T VID
EXTERNAL CIRCUIT
0.875V
SOFT-START
AND
FAULT LOGIC
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6326 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6326 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6326 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The ISL6326 features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6326 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6326 becomes enabled. The schematic in Figure 7
demonstrates sequencing the ISL6326 with the ISL66xx
19
FIGURE 7. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
When all conditions are satisfied, ISL6326 begins the
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6326 reads the VID
code at VID input pins. If the VID code is valid, ISL6326 will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6326 will shutdown, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6326 based VR has 4 periods during soft-start as shown
in Figure 8. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, The controller will have fixed delay
period td1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period td3. At the end of td3 period,
ISL6326 reads the VID signals. If the VID code is valid,
ISL6326 will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods, as shown in
Equation 14:
t SS = t d1 + t d2 + t d3 + t d4
(EQ. 14)
FN9262.1
May 5, 2008
ISL6326
td1 is a fixed delay with the typical value as 1.36ms. td3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum td3 is about 86µs.
During td2 and td4, ISL6326 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor RSS from SS pin to GND. The
second soft-start ramp time td2 and td4 can be calculated
based on Equations 15 and 16:
1.1xR SS
t d2 = ------------------------ ( μs )
6.25x25
(EQ. 15)
( V VID – 1.1 )xR SS
t d4 = ------------------------------------------------ ( μs )
6.25x25
(EQ. 16)
For example, when VID is set to 1.5V and the RSS is set at
100kΩ, the first soft-start ramp time td2 will be 704µs and the
second soft-start ramp time td4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay td5. The
typical value for td5 is 85µs.
VOUT, 500mV/DIV
td1
td2
td3
td4
td5
EN_VTT
VR_RDY
when an undervoltage or overvoltage condition is detected,
or the controller is disabled by a reset from EN_PWR,
EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during
the soft-start intervals td1, td2 and td3, the OVP threshold is
1.275V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC + 175mV.
Two actions are taken by the ISL6326 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (>20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC + 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both
upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326 will again command the lower
MOSFETs to turn on. The ISL6326 will continue to protect
the load in this fashion as long as the overvoltage condition
occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6326 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller..
500µs/DIV
VR_RDY
FIGURE 8. SOFT-START WAVEFORMS
Fault Monitoring and Protection
+
-
UV
The ISL6326 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
50%
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
-
85µA
OC
+
IAVG
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful
soft-start and a fixed delay td5. VR_RDY will be pulled low
20
+
VDIFF
OV
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
FN9262.1
May 5, 2008
ISL6326
Overcurrent Protection
Thermal Monitoring (VR_HOT/VR_FAN)
ISL6326 has two levels of overcurrent protection. Each
phase is protected from a sustained overcurrent condition by
limiting its peak current, while the combined phase currents
are protected on an instantaneous basis.
There are two thermal signals to indicate the temperature
status of the voltage regulator: VR_HOT and VR_FAN. Both
VR_FAN and VR_HOT pins are open-drain outputs, and
external pull-up resistors are required. Those signals are
valid only after the controller is enabled.
In instantaneous protection mode, the ISL6326 utilizes the
sensed average current IAVG to detect an overcurrent
condition. See the “Channel-Current Balance” on page 13
for more detail on how the average current is measured. The
average current is continually compared with a constant
85µA reference current, as shown in Figure 9. Once the
average current exceeds the reference current, a
comparator triggers the converter to shutdown.
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance state within
20ns, commanding the Intersil MOSFET driver ICs to turn off
both upper and lower MOSFETs. The system remains in this
state a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a
soft-start. If the fault remains, the trip-retry cycles will
continue indefinitely (as shown in Figure 10) until either
controller is disabled or the fault is cleared. Note that the
energy delivered during trip-retry cycling is much less than
during full-load operation, so there is no thermal hazard
during this kind of operation.
OUTPUT CURRENT
0A
The VR_FAN signal indicates that the temperature of the
voltage regulator is high and more cooling airflow is needed.
The VR_HOT signal can be used to inform the system that
the temperature of the voltage regulator is too high and the
CPU should reduce its power consumption. The VR_HOT
signal may be tied to the CPU’s PROC_HOT signal.
The diagram of thermal monitoring function block is shown in
Figure 11. One NTC resistor should be placed close to the
power stage of the voltage regulator to sense the operational
temperature, and one pull-up resistor is needed to form the
voltage divider for the TM pin. As the temperature of the
power stage increases, the resistance of the NTC will
reduce, resulting in the reduced voltage at the TM pin.
Figure 12 shows the TM voltage over the temperature for a
typical design with a recommended 6.8kΩ NTC (P/N:
NTHS0805N02N6801 from Vishay) and 1kΩ resistor RTM1.
We recommend using those resistors for the accurate
temperature compensation.
There are two comparators with hysteresis to compare the
TM pin voltage to the fixed thresholds for VR_FAN and
VR_HOT signals respectively. The VR_FAN signal is set to
high when the TM voltage is lower than 33% of VCC voltage,
and is pulled to GND when the TM voltage increases to
above 39% of VCC voltage. The VR_FAN signal is set to
high when the TM voltage goes below 28% of VCC voltage,
and is pulled to GND when the TM voltage goes back to
above 33% of VCC voltage. Figure 13 shows the operation
of those signals.
OUTPUT VOLTAGE
0V
VCC
2ms/DIV
VR_FAN
FIGURE 10. OVERCURRENT BEHAVIOR IN HICCUP MODE.
FSW = 500kHz
For the individual channel overcurrent protection, the
ISL6326 continuously compares the sensed current signal of
each channel with the 120µA reference current. If one
channel current exceeds the reference current, ISL6326 will
pull PWM signal of this channel to low for the rest of the
switching cycle. This PWM signal can be turned on next
cycle if the sensed channel current is less than the 120µA
reference current. The peak current limit of individual
channel will not trigger the converter to shutdown.
21
R TM1
0.33VCC
VR_HOT
TM
°C
R NTC
0.28VCC
FIGURE 11. BLOCK DIAGRAM OF THERMAL MONITORING
FUNCTION
FN9262.1
May 5, 2008
ISL6326
temperature coefficient, which is about +0.38%/°C. Since the
voltage across inductor is sensed for the output current
information, the sensed current has the same positive
temperature coefficient as the inductor DCR.
VTM/VCC vs TEMPERATURE
100
90
In order to obtain the correct current information, there
should be a way to correct the temperature impact on the
current sense component. ISL6326 provides two methods:
VTM/VCC (%)
80
70
60
1. Integrated temperature compensation
50
2. External temperature compensation
40
Integrated Temperature Compensation
30
When the TCOMP voltage is equal or greater than VCC/15,
ISL6326 will utilize the voltage at TM and TCOMP pins to
compensate the temperature impact on the sensed current.
The block diagram of this function is shown in Figure 14.
20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 12. THE RATIO OF TM VOLTAGE TO NTC
TEMPERATURE WITH RECOMMENDED PARTS
VCC
ISEN4
TM
RTM1
0.39*VCC
TM
0.33*VCC
0.28*VCC
°C
T1
T2
D/A
I2
I1
ki
RTC1
TCOMP
T3
ISEN1
I3
RNTC
VCC
TEMPERATURE
ISEN2
NON-LINEAR
A/D
I4
VR_FAN
VR_HOT
ISEN3
CHANNEL CURRENT
SENSE
FIGURE 13. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE
4-BIT
A/D
DROOP AND
OVERCURRENT PROTECTION
RTC2
Based on the NTC temperature characteristics and the
desired threshold of the VR_HOT signal, the pull-up resistor
RTM1 of TM pin is given by Equation 17:
R TM1 = 2.75xR NTC ( T3 )
(EQ. 17)
RNTC(T3) is the NTC resistance at the VR_HOT threshold
temperature T3.
The NTC resistance at the set point T2 and release point T1
of VR_FAN signal can be calculated in Equations 18 and 19:
R NTC ( T2 ) = 1.267xR NTC ( T3 )
(EQ. 18)
R NTC ( T1 ) = 1.644xR NTC ( T3 )
(EQ. 19)
With the NTC resistance value obtained from Equations 17
and 18, the temperature value T2 and T1 can be found from
the NTC datasheet.
Temperature Compensation
ISL6326 supports inductor DCR sensing, or resistive
sensing techniques. The inductor DCR has a positive
22
FIGURE 14. BLOCK DIAGRAM OF INTEGRATED
TEMPERATURE COMPENSATION
When the TM NTC is placed close to the current sense
component (inductor), the temperature of the NTC will track
the temperature of the current sense component. Therefore
the TM voltage can be utilized to obtain the temperature of
the current sense component.
Based on VCC voltage, ISL6326 converts the TM pin voltage
to a 6-bit TM digital signal for temperature compensation.
With the non-linear A/D converter of ISL6326, the TM digital
signal is linearly proportional to the NTC temperature. For
accurate temperature compensation, the ratio of the TM
voltage to the NTC temperature of the practical design
should be similar to that in Figure 12.
Depending on the location of the NTC and the airflow, the
NTC may be cooler or hotter than the current sense
component. The TCOMP pin voltage can be utilized to
correct the temperature difference between NTC and the
current sense component. When a different NTC type or
different voltage divider is used for the TM function, the
FN9262.1
May 5, 2008
ISL6326
TCOMP voltage can also be used to compensate for the
difference between the recommended TM voltage curve in
Figure 13 and that of the actual design. According to the
VCC voltage, ISL6326 converts the TCOMP pin voltage to a
4-bit TCOMP digital signal as TCOMP factor N.
The TCOMP factor N is an integer between 0 and 15. The
integrated temperature compensation function is disabled for
N = 0. For N = 4, the NTC temperature is equal to the
temperature of the current sense component. For N < 4, the
NTC is hotter than the current sense component. The NTC is
cooler than the current sense component for N > 4. When
N > 4, the larger TCOMP factor N, the larger the difference
between the NTC temperature and the temperature of the
current sense component.
ISL6326 multiplexes the TCOMP factor N with the TM digital
signal to obtain the adjustment gain to compensate the
temperature impact on the sensed channel current. The
compensated channel current signal is used for droop and
overcurrent protection functions.
Design Procedure
External Temperature Compensation
By pulling the TCOMP pin to GND, the integrated
temperature compensation function is disabled. And one
external temperature compensation network (shown in
Figure 15) can be used to cancel the temperature impact on
the droop (i.e. load line).
COMP
ISL6326
INTERNAL
CIRCUIT
IDROOP
°C
FB
VDIFF
1. Properly choose the voltage divider for the TM pin to
match the TM voltage vs temperature curve with the
recommended curve in Figure 12.
2. Run the actual board under the full load and the desired
cooling condition.
3. After the board reaches the thermal steady state, record
the temperature (TCSC) of the current sense component
(inductor or MOSFET) and the voltage at TM and VCC
pins.
4. Use Equation 20 to calculate the resistance of the TM
NTC, and find out the corresponding NTC temperature
TNTC from the NTC datasheet.
R NTC ( T
11. If the output voltage increases over 2mV as the
temperature increases, i.e. V2 - V1 > 2mV, reduce N and
redesign RTC2; if the output voltage decreases over 2mV
as the temperature increases, i.e. V1 - V2 > 2mV,
increase N and redesign RTC2.
V TM xR
TM1
= ------------------------------)
V CC – V
NTC
TM
(EQ. 20)
5. Use Equation 21 to calculate the TCOMP factor N:
209x ( T CSC – T
)
NTC
N = -------------------------------------------------------- + 4
3xT NTC + 400
(EQ. 21)
6. Choose an integral number close to the above result for
the TCOMP factor. If this factor is higher than 15, use
N = 15. If it is less than 1, use N = 1.
7. Choose the pull-up resistor RTC1 (typical 10kΩ).
8. If N = 15, do not need the pull-down resistor RTC2,
otherwise obtain RTC2 by using Equation 22:
NxR TC1
R TC2 = ----------------------15 – N
(EQ. 22)
9. Run the actual board under full load again with the proper
resistors connected to the TCOMP pin.
10. Record the output voltage as V1 immediately after the
output voltage is stable with the full load. Record the
output voltage as V2 after the VR reaches the thermal
steady state.
23
FIGURE 15. EXTERNAL TEMPERATURE COMPENSATION
The sensed current will flow out of the IDROOP pin and
develop a droop voltage across the resistor equivalent (RFB)
between the FB and VDIFF pins. If RFB resistance reduces
as the temperature increases, the temperature impact on the
droop can be compensated. An NTC resistor can be placed
close to the power stage and used to form RFB. Due to the
non-linear temperature characteristics of the NTC, a resistor
network is needed to make the equivalent resistance
between the FB and VDIFF pins reverse proportional to the
temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it
has no impact to the sensed current inside ISL6326.
Therefore, this network cannot compensate for the
temperature impact on the overcurrent protection function.
Current Sense Output
The current from the IDROOP pin is the sensed average
current inside the ISL6326. In typical application, the
IDROOP pin is connected to the FB pin for the application
where load line is required.
When load line function is not needed, the IDROOP pin can
be used to obtain the load current information: with one
resistor from the IDROOP pin to GND, the voltage at the
IDROOP pin will be proportional to the load current in
Equation 23:
R IDROOP R X
- ------------------ I LOAD
V IDROOP = --------------------------N
R ISEN
(EQ. 23)
FN9262.1
May 5, 2008
ISL6326
where VIDROOP is the voltage at the IDROOP pin, RIDROOP
is the resistor between the IDROOP pin and GND, ILOAD is
the total output current of the converter, RISEN is the sense
resistor connected to the ISEN+ pin, N is the active channel
number, and RX is the resistance of the current sense
element, either the DCR of the inductor or RSENSE
depending on the sensing method.
The resistor from the IDROOP pin to GND should be chosen
to ensure that the voltage at the IDROOP pin is less than 2V
under the maximum load current.
If the IDROOP pin is not used, tie it to GND.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following sections. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts for all common
microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis, which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15A and 20A.
All surface-mount designs will tend toward the lower end of
this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In
cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (rDS(ON)). In Equation 24, IM is the maximum
continuous output current; IP-P is the peak-to-peak inductor
24
current (see Equation 1); d is the duty cycle (VOUT/VIN); and
L is the per-channel inductance.
I L(P-P) ( 1 – d ) 2
⎛ I M⎞ 2
P LOW, 1 = r DS ( ON ) ⎜ -----⎟ ( 1 – d ) + ----------------------------------12
⎝ N⎠
(EQ. 24)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON) the switching frequency,
fS and the length of dead times, td1 and td2, at the beginning
and the end of the lower-MOSFET conduction interval
respectively as shown in Equation 25:
⎛I
⎞
IM I ⎞
M I P-P
P-P- t
P LOW, 2 = V D ( ON ) f S ⎛ ----d1 + ⎜ ------ – ----------⎟ t d2
⎝ N- + --------⎠
2 ⎠
2
⎝N
(EQ. 25)
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of PLOW,1 and
PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted
across the input voltage (VIN) during switching. Since a
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times the lower-MOSFET body-diode
reverse-recovery charge (Qrr) and the upper MOSFET
rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I P-P⎞ ⎛ t 1 ⎞
P UP,1 ≈ V IN ⎛ ----- ⎜ ---- ⎟ f
⎝ N- + --------2 ⎠ ⎝ 2⎠ S
(EQ. 26)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 27, the
approximate power loss is PUP,2.
⎛ I M I P-P⎞ ⎛ t 2 ⎞
P UP, 2 ≈ V IN ⎜ ----- – ----------⎟ ⎜ ---- ⎟ f S
2 ⎠⎝ 2⎠
⎝N
(EQ. 27)
A third component involves the lower MOSFET’s
reverse-recovery charge (Qrr). Since the inductor current
has fully commutated to the upper MOSFET before the
lower-MOSFET’s body diode can draw all of Qrr, it is
FN9262.1
May 5, 2008
ISL6326
conducted through the upper MOSFET across VIN. The
power dissipated as a result is PUP,3 and is approximately
P UP,3 = V IN Q rr f S
(EQ. 28)
Balance” on page 13). Choose RISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase in
Equation 31:
Finally, the resistive part of the upper MOSFET’s is given in
Equation 29 as PUP,4.
ΔT
R ISEN ,2 = R ISEN ----------2
ΔT 1
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, and 28. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
Make sure that ΔT2 is the desired temperature rise above the
ambient temperature, and ΔT1 is the measured temperature
rise above the ambient temperature. While a single
adjustment according to Equation 31 is usually sufficient, it
may occasionally be necessary to adjust RISEN two or more
times to achieve optimal thermal balance between all
channels.
2
I PP2
⎛ I M⎞
P UP,4 ≈ r DS ( ON ) ⎜ -----⎟ d + ---------- d
12
⎝ N⎠
Load-Line Regulation Resistor
(EQ. 29)
The load-line regulation resistor is labelled RFB in Figure 5.
Its value depends on the desired loadline requirement of the
application.
Current Sensing Resistor
The resistors connected to the ISEN+ pins determine the
gains in the load-line regulation loop and the channel-current
balance loop as well as setting the overcurrent trip point.
Select values for these resistors by using Equation 30:
RX
I OCP
R ISEN = ---------------------- ------------–6 N
85 ×10
(EQ. 31)
The desired loadline can be calculated by using
Equation 32:
V DROOP
R LL = -----------------------I FL
(EQ. 32)
(EQ. 30)
where RISEN is the sense resistor connected to the
ISEN+ pin, N is the active channel number, RX is the
resistance of the current sense element, either the DCR of
the inductor or RSENSE depending on the sensing method,
and IOCP is the desired overcurrent trip point. Typically, IOCP
can be chosen to be 1.3x the maximum load current of the
specific application.
With integrated temperature compensation, the sensed
current signal is independent on the operational temperature
of the power stage, i.e. the temperature effect on the current
sense element RX is cancelled by the integrated
temperature compensation function. RX in Equation 30
should be the resistance of the current sense element at the
room temperature.
When the integrated temperature compensation function is
disabled by pulling the TCOMP pin to GND, the sensed
current will be dependent on the operational temperature of
the power stage, since the DC resistance of the current
sense element may be changed according to the operational
temperature. RX in Equation 30 should be the maximum DC
resistance of the current sense element at the all-operational
temperature.
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled “Channel-Current
25
where IFL is the full load current of the specific application,
and VRDROOP is the desired voltage droop under the full
load condition.
Based on the desired loadline RLL, the loadline regulation
resistor can be calculated by using Equation 33:
NR
R
ISEN LL
R FB = --------------------------------RX
(EQ. 33)
where N is the active channel number, RISEN is the sense
resistor connected to the ISEN+ pin, and RX is the
resistance of the current sense element, either the DCR of
the inductor or RSENSE depending on the sensing method.
If one or more of the current sense resistors are adjusted for
thermal balance, as in Equation 31, the load-line regulation
resistor should be selected based on the average value of
the current sensing resistors, as given in Equation 34:
R LL
R FB = ---------RX
∑ RISEN ( n )
(EQ. 34)
n
where RISEN(n) is the current sensing resistor connected to
the nth ISEN+ pin.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in “Load-Line Regulation” on page 18, there are
two distinct methods for achieving these goals.
FN9262.1
May 5, 2008
ISL6326
COMPENSATING LOAD-LINE REGULATED
CONVERTER
Case 1:
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
CC
COMP
IDROOP
ISL6326
+
VDROOP
IN
0.75V IN
C C = ----------------------------------2πV PP R FB f 0
Case 2:
1
1
------------------- ≤ f 0 < ----------------------------2πC ( ESR )
2π LC
V PP ( 2π ) 2 f 02 LC
R C = R FB -------------------------------------------0.75 V
(EQ. 35)
IN
0.75V IN
C C = -----------------------------------------------------------2
( 2π ) f 02 V PP R FB LC
Case 3:
1
f 0 > -----------------------------2πC ( ESR )
0.75V IN ( ESR ) C
C C = -----------------------------------------------2πV PP R FB f 0 L
FB
RFB
2πf 0 V pp LC
R C = R FB ----------------------------------0.75V
2π f 0 V pp L
R C = R FB ----------------------------------------0.75 V IN ( ESR )
C2 (OPTIONAL)
RC
1
------------------- > f 0
2π LC
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VP-P is the sawtooth
amplitude described in Electrical Specifications on page 7.
VDIFF
FIGURE 16. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6326 CIRCUIT
The feedback resistor, RFB, has already been chosen as
outlined in “Load-Line Regulation Resistor” on page 25.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
26
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 16). Keep
a position available for C2, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 35
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 35 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 17, provides the
necessary compensation.
FN9262.1
May 5, 2008
ISL6326
Output Filter Design
C2
RC
CC
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
COMP
IDROOP
RFB
R1
ISL6326
FB
C1
VDIFF
FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, fHF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose fHF = 10f0, but it can be
higher if desired. Choosing fHF to be lower than 10f0 can
cause problems with too much phase shift below the system
bandwidth.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI; the load-current slew rate, di/dt; and the
maximum allowable output voltage deviation under transient
loading, ΔVMAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 36, RFB is selected arbitrarily. The remaining
compensation components are then selected.
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
in Equation 37:
C ( ESR )
R 1 = R FB ----------------------------------------LC – C ( ESR )
di
ΔV ≈ ( ESL ) ----- + ( ESR ) ΔI
dt
LC – C ( ESR )
C 1 = ----------------------------------------R FB
(EQ. 37)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
0.75V IN
C 2 = ------------------------------------------------------------------2
( 2π ) f 0 f HF LCR FB V P-P
(EQ. 36)
2
V PP ⎛ 2π⎞ f 0 f HF LCR FB
⎝ ⎠
R C = -------------------------------------------------------------------⎛2πf
⎞
LC
–
1
0.75 V
⎝ HF
⎠
IN
⎞
0.75V IN ⎛2πf
⎝ HF LC – 1⎠
C C = -------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V P-P
In Equation 36, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VP-P is the sawtooth
signal amplitude as described in “Electrical Specifications”
on page 7.
27
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to IC(P-P)(ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, VP-P(MAX), determines the lower limit on the
inductance.
FN9262.1
May 5, 2008
ISL6326
.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔVMAX. This places an upper limit on inductance.
Equation 39 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output voltage deviation than the leading edge. Equation 40
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2NCVO
L ≤ -------------------- ΔV MAX – ΔI ( ESR )
( ΔI ) 2
( 1.25 ) NC
L ≤ -------------------------- ΔV MAX – ΔI ( ESR ) ⎛ V IN – V O⎞
⎝
⎠
( ΔI ) 2
(EQ. 39)
(EQ. 40)
Switching Frequency Selection
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 24 and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output voltage ripple as outlined in “Output Filter
Design” on page 27. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
28
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
(EQ. 38)
0.2
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
⎛V – N V
⎞
OUT⎠ V OUT
⎝ IN
L ≥ ( ESR ) -----------------------------------------------------------f S V IN V P-P( MAX )
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
For a two-phase design, use Figure 18 to determine the
input-capacitor RMS current requirement given the duty
cycle, maximum sustained output current (IO), and the ratio
of the per-phase peak-to-peak inductor current (IL(P-P)) to
IO. Select a bulk capacitor with a ripple current rating which
will minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage.
FN9262.1
May 5, 2008
ISL6326
IL(P-P) = 0
IL(P-P) = 0.25 IO
0.6
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
INPUT-CAPACITOR CURRENT (IRMS/IO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
Figures 19 and 20 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described previously.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew rates produced by the upper MOSFETs turn on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
MULTIPHASE RMS IMPROVEMENT
Figure 21 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a two-phase
converter vs that of a single phase. Assume both converters
have a duty cycle of 0.25, maximum sustained output current
of 40A, and a ratio of IL(P-P) to IO of 0.5. The single phase
converter would require 17.3ARMS current capacity while the
two-phase converter would only require 10.9ARMS. The
advantages become even more pronounced when output
current is increased and additional phases are added to
keep the component cost down relative to the single phase
approach.
0.4
0.2
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same placement
of these components for each phase.
Next, place the input and output capacitors. Position one highfrequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to the
upper MOSFET drains as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductors and the load, while keeping
them in close proximity to the microprocessor socket.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
29
FN9262.1
May 5, 2008
ISL6326
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00
36X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
31
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
30
FN9262.1
May 5, 2008