OPA OPA692 69 2 OPA6 92 SBOS236E – MARCH 2002 – REVISED DECEMBER 2008 www.ti.com Wideband, Fixed Gain Video BUFFER AMPLIFIER With Disable FEATURES DESCRIPTION ● FLEXIBLE SUPPLY RANGE: +5V to +12V Single Supply ±2.5V to ±6V Dual Supplies ● INTERNALLY FIXED GAIN: +2 or ±1 ● HIGH BANDWIDTH (G = +2): 225MHz ● LOW SUPPLY CURRENT: 5.1mA ● LOW DISABLED CURRENT: 150µA ● HIGH OUTPUT CURRENT: 190mA ● OUTPUT VOLTAGE SWING: ±4.0V ● SOT23-6 AVAILABLE The OPA692 provides an easy to use, broadband fixed gain video buffer amplifier. Depending on the external connections, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of +1 or –1 voltage buffer. Operating on a very low 5.1mA supply current, the OPA692 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers high output current with minimal headroom and crossover distortion. This gives exceptional single-supply operation. Using a single +5V supply, the OPA692 can deliver a 1V to 4V output swing with over 120mA drive current and > 200MHz bandwidth. This combination of features makes the OPA692 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. APPLICATIONS ● ● ● ● ● BROADBAND VIDEO LINE DRIVERS MULTIPLE LINE VIDEO DA PORTABLE INSTRUMENTS ADC BUFFERS ACTIVE FILTERS The low 5.1mA supply current for the OPA692 is precisely trimmed at +25°C. This trim, along with low drift over temperature, ensures a lower maximum supply current than competing products that report only a room temperature nominal supply current. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, gives normal operation. If pulled LOW, the OPA692 supply current drops to less than 150µA while the I/O pins go into a high-impedance state. OPA692 RELATED PRODUCTS Voltage-Feedback SINGLES DUALS TRIPLES OPA690 OPA2690 OPA3690 Current-Feedback OPA691 OPA2691 OPA3691 Fixed Gain OPA682 OPA2682 OPA3692 75Ω Video Out OPA692 RG-59 75Ω 1 8 2 7 3 6 4 5 DIS 75Ω Video In +5V RG-59 75Ω 75Ω 75Ω –5V RG-59 75Ω SO-8 G = +2 75Ω RG-59 75Ω 225MHz, 4-Output Component Video DA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation(2) ............................ See Thermal Information Differential Input Voltage(3) ............................................................... ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: D, DVB ........................... –65°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C ESD Resistance: HBM ........................................................................ 2kV MM ........................................................................ 200V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Packages must be derated based on specified θJA. Maximum TJ must be observed. (3) Noninverting input to internal inverting node. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA692ID SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA692ID OPA692IDR OPA692IDBVT OPA692IDBVR Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 SO-8 Surface-Mount D –40°C to +85°C OPA692 " " " " " OPA692IDBV SOT23-6 DBV –40°C to +85°C OAGI " " " " " NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN CONFIGURATION Top View SO Top View SOT Output 1 6 +VS 5 DIS 4 –IN RF 402Ω NC 1 RG 402Ω RF 402Ω 8 –VS 2 +IN 3 DIS –IN 2 7 +VS +IN 3 6 Output 6 –VS 4 5 RG 402Ω 5 4 NC OAGI NC: No Connection 1 2 3 Pin Orientation/Package Marking 2 OPA692 www.ti.com SBOS236E ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP PARAMETER CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C UNITS MHz typ 185 180 170 MHz min B MHz typ C MIN/ TEST MAX LEVEL(2 ) AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth (VO < 0.5VPP) Bandwidth for 0.1dB Gain Flatness G = +1 280 G = +2 225 G = –1 220 C G = +2, VO < 0.5VPP 120 40 35 30 MHz min B Peaking at a Gain of +1 VO < 0.5VPP 0.2 1 1.5 2 dB max B Large-Signal Bandwidth G = +2, VO = 5VPP 220 MHz typ C G = +2, 4V Step 2000 1400 1375 1350 V/µs min B G = +2, VO = 0.5V Step 1.6 ns typ C G = +2, VO = 5V Step 1.9 ns typ C G = +2, VO = 2V Step 12 ns typ C G = +2, VO = 2V Step 8 ns typ C B Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic G = +2, f = 5MHz, VO = 2VPP RL = 100Ω –69 –62 –59 –57 dBc max RL ≥ 500Ω –79 –70 –67 –65 dBc max B RL = 100Ω –76 –72 –70 –68 dBc max B RL ≥ 500Ω –94 –87 –82 –78 dBc max B Input Voltage Noise f > 1MHz 1.7 2.5 2.9 3.1 nV/√Hz max B Noninverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B Inverting Input Current Noise f > 1MHz 15 17 18 19 pA/√Hz max B NTSC, RL = 150Ω 0.07 % typ C NTSC, RL = 37.5Ω 0.17 % typ C NTSC, RL = 150Ω 0.02 deg typ C NTSC, RL = 37.5Ω 0.07 deg typ C G = +1 ±0.2 % typ C G = +2 ±0.3 ±1.5 ±1.6 ±1.7 % max A G = –1 ±0.2 ±1.5 ±1.6 ±1.7 % max B Maximum 402 457 462 464 Ω max A Minimum 402 347 342 340 Ω min A 0.13 0.13 0.13 %/C° max B ±2.5 ±3.2 ±3.9 mV max A ±12 ±20 µV/°C max B Differential Gain Differential Phase DC PERFORMANCE(3) Gain Error Internal RF and RG Average Drift Input Offset Voltage VCM = 0V Average Offset Voltage Drift VCM = 0V Noninverting Input Bias Current VCM = 0V Average Noninverting Input Bias Current Drift VCM = 0V Inverting Input Bias Current VCM = 0V Average Inverting Input Bias Current Drift VCM = 0V ±0.5 +15 ±5 +35 ±25 +43 +45 µA max A –300 –300 nA/°C max B ±30 ±40 µA max A ±90 ±200 nA°C max B ±3.3 ±3.2 INPUT ±3.5 Common-Mode Input Range Noninverting Input Impedance ±3.4 100 || 2 V min B kΩ || pF typ C OUTPUT Voltage Output Swing No Load ±4.0 ±3.6 V min A ±3.9 ±3.8 ±3.7 ±3.7 100Ω Load ±3.6 ±3.3 V min A +190 +160 +140 +100 mA min A –190 –160 –140 –100 mA min A Current Output, Sourcing Sinking Short-Circuit Current Closed-Loop Output Impedance VO = 0 ±250 mA typ C G = +2, f = 100kHz 0.12 Ω typ C NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. OPA692 SBOS236E www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.) Boldface limits are tested at +25°C. G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP PARAMETER CONDITIONS MIN/MAX OVER TEMPERATURE +25°C +25°C(1) 0°C to 70°C –40°C to +85°C UNITS –300 –350 –400 µA max A µs typ C MIN/ TEST MAX LEVEL(2 ) DISABLE/POWER DOWN (DIS Pin) Power-Down Supply Current (+VS) VDIS = 0 –150 VIN = +1VDC 1 Enable Time VIN = +1VDC 25 ns typ C Off Isolation G = +2, 5MHz 70 dB typ C 4 pF typ C Turn-On Glitch G = +2, RL = 150Ω ±50 mV typ C Turn-Off Glitch G = +2, RL= 150Ω ±20 C Disable Time Output Capacitance in Disable mV typ Enable Voltage 3.3 3.5 3.6 3.7 V min A Disable Voltage 1.8 1.7 1.6 1.5 V max A 75 130 150 160 µA max A V typ C ±6 ±6 ±6 V max A Control Pin Input Bias Current VDIS = 0 POWER SUPPLY ±5 Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current VS = ±5V 5.1 5.3 5.5 5.8 mA max A Minimum Quiescent Current VS = ±5V 5.1 4.9 4.5 4.25 mA min A Input Referred 58 52 50 49 dB min A –40 to +85 °C typ C Power-Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 125 °C/W typ C DBV SOT23-6 150 °C/W typ C NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. 4 OPA692 www.ti.com SBOS236E ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (see Figure 2 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP PARAMETER CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C UNITS MHz typ 168 160 140 MHz min B MHz typ C MIN/ TEST MAX LEVEL(2 ) AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth (VO < 0.5VPP) Bandwidth for 0.1dB Gain Flatness G = +1 240 G = +2 190 G = –1 195 C G = +2, VO < 0.5VPP 90 40 30 25 MHz min B Peaking at a Gain of +1 VO < 0.5VPP 0.2 1 2.5 3 dB max B Large-Signal Bandwidth G = +2, VO = 2VPP 210 MHz typ C G = +2, 2V Step 830 600 575 550 V/µs min B G = +2, VO = 0.5V Step 2.0 ns typ C G = +2, VO = 2V Step 2.3 ns typ C G = +2, VO = 2V Step 14 ns typ C G = +2, VO = 2V Step 10 ns typ C Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic G = +2, f = 5MHz, VO = 2VPP RL = 100Ω to VS /2 –66 –58 –57 –56 dBc max B RL ≥ 500Ω to VS /2 –73 –65 –63 –62 dBc max B RL = 100Ω to VS /2 –72 –68 –67 –65 dBc max B RL ≥ 500Ω to VS /2 –77 –72 –70 –69 dBc max B Input Voltage Noise f > 1MHz 1.7 2.5 2.9 3.1 nV/√Hz max B Noninverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B Inverting Input Current Noise f > 1MHz 15 17 18 19 pA/√Hz max B G = +1 ±0.2 % typ C G = +2 ±0.3 ±1.5 ±1.6 ±1.7 % max A G = –1 ±0.2 ±1.5 ±1.6 ±1.7 % max B Maximum 402 457 462 464 Ω max B Minimum 402 347 342 340 Ω min B 0.13 0.13 0.13 %/C° max B ±3 ±3.6 ±4.3 mV max A ±12 ±20 µV/°C max B DC PERFORMANCE(3) Gain Error Internal RF and RG Average Drift Input Offset Voltage VCM = 2.5V Average Offset Voltage Drift VCM = 2.5V Noninverting Input Bias Current VCM = 2.5V Average Noninverting Input Bias Current Drift VCM = 2.5V Inverting Input Bias Current VCM = 2.5V Average Inverting Input Bias Current Drift VCM = 2.5V ±0.5 +20 ±5 +40 ±25 +46 +56 µA max A –250 –250 nA/°C max B ±30 ±40 µA max A ±112 ±200 nA°C max B INPUT Least Positive Input Voltage 1.5 1.6 1.7 1.8 V max B Most Positive Input Voltage 3.5 3.4 3.3 3.2 V min B kΩ || pF typ C Noninverting Input Impedance 100 || 2 OUTPUT Most Positive Output Voltage Least Positive Output Voltage No Load 4.0 3.8 3.7 3.5 V min A RL = 100Ω 3.9 3.7 3.6 3.4 V min A No Load 1.0 1.2 1.3 1.5 V max A RL = 100Ω 1.1 1.3 1.4 1.6 V max A Current Output, Sourcing +160 +120 +100 +80 mA min A Sinking –160 –120 –100 –80 mA min A Short-Circuit Current Output Impedance VO = VS/2 ±250 mA typ C G = +2, f = 100kHz 0.12 Ω typ C NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. OPA692 SBOS236E www.ti.com 5 ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.) Boldface limits are tested at +25°C. G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (see Figure 2 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP PARAMETER MIN/MAX OVER TEMPERATURE CONDITIONS +25°C(1) +25°C 0°C to 70°C –40°C to +85°C –300 –350 –400 UNITS MIN/ TEST MAX LEVEL(2 ) DISABLE/POWER DOWN (DIS Pin) Power-Down Supply Current (+VS) µA typ C dB typ C pF typ C mV typ B VDIS = 0 –150 G = +2, 5MHz 65 4 Turn-On Glitch G = +2, RL = 150Ω, VIN = 2.5V ±50 Turn-Off Glitch G = +2, RL = 150Ω, VIN = 2.5V ±20 mV typ B V min B Off Isolation Output Capacitance in Disable Enable Voltage 3.3 Disable Voltage Control Pin Input Bias Current (DIS ) VDIS = 0 3.5 3.6 3.7 1.8 1.7 1.6 1.5 V max B 75 130 150 160 µA typ C V typ C 12 12 12 V max A POWER SUPPLY Specified Single-Supply Operating Voltage 5 Maximum Single-Supply Operating Voltage Maximum Quiescent Current VS = +5V 4.5 4.8 5.0 5.2 mA max A Minimum Quiescent Current VS = +5V 4.5 4.1 3.8 3.7 mA min A Input Referred 55 dB typ C –40 to +85 °C typ C 125 °C/W typ C 150 °C/W typ C Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT23-6 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. 6 OPA692 www.ti.com SBOS236E TYPICAL CHARACTERISTICS: VS = ±5V TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 1 7 VO = 1Vp-p 6 G = +1 VO = 2Vp-p –1 G = –1 –2 5 Gain (1dB/div) Normalized Gain (1dB/div) 0 –3 –4 –5 VO = 4Vp-p 3 VO = 7Vp-p 2 G = +2 –6 4 1 –7 –8 0 0 250MHz 500MHz 0 125MHz Frequency (50MHz/div) LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 4 VO = 0.5Vp-p G = +2 300 VO = 5Vp-p G = +2 3 Output Voltage (1V/div) Output Voltage (100mV/div) 400 200 100 0 –100 –200 2 1 0 –1 –2 –3 –300 –4 –400 Time (5ns/div) Time (5ns/div) COMPOSITE VIDEO dG/dP 0.20 +5V 0.18 Video In 0.16 DIS Video Loads DISABLED FEEDTHROUGH vs FREQUENCY –50 No Pull-Down With 1.3kΩ Pull-Down 0.12 Feedthrough (5dB/div) –5V dG Optional 1.3kΩ Pull-Down dG 0.10 0.08 dP 0.06 0.04 VDIS = 0 –55 OPA692 0.14 dG/dP (%/°) 250MHz Frequency (25MHz/div) dP –60 –65 –70 –75 Reverse –80 Forward –85 –90 0.02 0 –95 1 2 3 4 0.5 10 100 Frequency (MHz) Number of 150Ω Loads OPA692 SBOS236E 1 www.ti.com 7 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE –60 –50 VO = 2Vp-p f = 5MHz VO = 2Vp-p RL = 100Ω f = 5MHz –55 –70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –65 2nd-Harmonic –75 –80 –85 3rd-Harmonic –90 –95 –100 –60 2nd-Harmonic –65 –70 –75 –80 3rd-Harmonic –85 –105 –110 –90 100 1000 2 2.5 3 Load Resistance (Ω) 4.5 5 5.5 6 –65 VO = 2Vp-p RL = 100Ω dBc = dB Below Carrier RL = 100Ω f = 5MHz –60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 4 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY (G = +2) –50 2nd-Harmonic –70 –80 3rd-Harmonic –90 –100 2nd-Harmonic –70 –75 3rd-Harmonic –80 –85 0.1 1 10 0.1 20 HARMONIC DISTORTION vs FREQUENCY (G = –1) –50 5 HARMONIC DISTORTION vs FREQUENCY (G = +1) –50 VO = 2Vp-p RL = 100Ω dBc = dB Below Carrier 1 Output Voltage Swing (Vp-p) Frequency (MHz) VO = 2Vp-p RL = 100Ω dBc = dB Below Carrier –60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 3.5 Supply Voltage (±VS) 2nd-Harmonic –70 –80 3rd-Harmonic –90 –60 –70 3rd-Harmonic –80 –90 2nd-Harmonic –100 –100 0.1 1 10 20 0.1 Frequency (MHz) 8 1 10 20 Frequency (MHz) OPA692 www.ti.com SBOS236E TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. 2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS INPUT VOLTAGE AND CURRENT NOISE DENSITY –30 3rd-Order Spurious Level (dBc) Inverting Input Current Noise (15pA/√Hz) 10 Noninverting Current Noise (12pA/√Hz) Voltage Noise (1.7nV/√Hz) 1 dBc = dB below carriers 50MHz –40 –50 –60 20MHz –70 10MHz –80 Load Power at Matched 50Ω Load –90 100 1k 10k 100k 1M 10M –8 –6 –4 Frequency (Hz) RECOMMENDED RS vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 50 RS (Ω) 40 30 20 10 0 10 2 4 6 8 10 100 9 CL = 10pF 6 3 CL = 47pF 0 CL = 22pF –3 VIN RS 402Ω –6 CL = 100pF VO OPA692 CL 1kΩ 402Ω 1kΩ is optional. –9 1k 0 125MHz Capacitive Load (pF) 250MHz Frequency (25MHz/div) PSRR vs FREQUENCY SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 65 10 250 Sourcing Output Current 60 +PSRR 55 Supply Current (2mA) Power-Supply Rejection Ratio (dB) 0 FREQUENCY RESPONSE vs CAPACITIVE LOAD 60 1 –2 Single-Tone Load Power (dBm) –PSRR 50 45 40 35 30 8 200 Sinking Output Current 6 150 4 100 Quiescent Supply Current 2 50 Output Current (50mA/div) Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) 100 25 20 0 1k 10k 100k 1M 10M 100M Frequency (Hz) –25 0 25 50 75 100 125 Ambient Temperature (°C) OPA692 SBOS236E 0 –50 www.ti.com 9 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. TYPICAL DC DRIFT OVER TEMPERATURE OUTPUT VOLTAGE AND CURRENT LIMITATIONS Output Current Limited 1W Internal Power Limit Input Offset Voltage (mV) 3 VO (V) 2 1 25Ω Load Line 0 –1 50Ω Load Line –2 100Ω Load Line –3 –4 1W Internal Power Limit Output Current Limit 40 Noninverting Input Bias Current 1.5 30 1 20 0.5 10 Inverting Input Bias Current 0 0 –0.5 –10 Input Offset Voltage –1 –20 –1.5 –30 –2 –5 –300 –250 –200 –150 –100 –50 0 50 –40 –50 100 150 200 250 300 –25 0 25 50 LARGE-SIGNAL DISABLE/ENABLE RESPONSE 0 2.0 Output Voltage (10mV/div) Output Voltage (400mV/div) 2.0 6.0 VDIS VDIS (2V/div) 4.0 VDIS 1.6 Output Voltage 0.8 0 125 DISABLE/ENABLE GLITCH 6.0 0.4 100 Ambient Temperature (°C) IO (mA) 1.2 75 VIN = +1V 4.0 2.0 0 30 20 Output Voltage (0V Input) 10 0 –10 –20 Time (200ns/div) Time (20ns/div) CLOSED-LOOP OUTPUT IMPEDANCE 10 Output Impedance (Ω) +5V 50Ω OPA692 ZO –5V 402Ω 1 402Ω 0.1 10k 100k 1M 10M 100M Frequency (Hz) 10 OPA692 www.ti.com SBOS236E VDIS (2V/div) 4 2 Input Bias Currents (µA) 5 TYPICAL CHARACTERISTICS: VS = +5V TA = +25°C, G = +2, and RL = 100Ω (see Figure 2 for AC performance only), unless otherwise noted. LARGE-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE 1 7 VO = 0.5Vp-p 6 G = +1 –1 5 –2 Gain (1dB/div) Normalized Gain (1dB/div) 0 G = –1 –3 –4 –5 3 2 –6 G = +2 1 –7 RL = 100Ω to 2.5V –8 0 0 250M 0 500M 125M SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE 2.9 4.1 G = +2 VO = 0.5Vp-p 2.8 Output Voltage (400mV/div) Output Voltage (100mV/div) 250M Frequency (Hz) Frequency (Hz) 2.7 2.6 2.5 2.4 2.3 2.2 G = +2 VO = 2Vp-p 3.7 3.3 2.9 2.5 2.1 1.7 1.3 2.1 0.9 Time (5ns/div) Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 60 6 Normalized Gain to Capacitive Load (dB) 70 50 RS (Ω) VO = 1Vp-p VO = 2Vp-p 4 40 30 20 CL = 10pF CL = 22pF 3 CL = 47pF 0 +5V –3 806Ω VIN 0.1µF RS 57.6Ω 10 –6 0 –9 806Ω OPA692 CL CL = 100pF VO 1kΩ 402Ω 402Ω (1kΩ is optional) 0.1µF 1 10 100 1k 0 Capacitive Load (pF) OPA692 SBOS236E 125MHz 250MHz Frequency (25MHz/div) www.ti.com 11 TYPICAL CHARACTERISTICS: VS = +5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 2 for AC performance only), unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE –60 –50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2Vp-p f = 5MHz –65 2nd-Harmonic –70 3rd-Harmonic –75 –80 2nd-Harmonic –70 –80 3rd-Harmonic 0.1 1k 1 Frequency (MHz) HARMONIC DISTORTION vs OUTPUT VOLTAGE 2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS –30 3rd-Order Spurious Level (dBc) RL = 100Ω to 2.5V f = 5MHz –65 2nd-Harmonic –70 –75 3rd-Harmonic 1 2 50MHz –40 –45 –50 –55 20MHz –60 –65 10MHz –70 –75 Load Power at Matched 50Ω Load –14 3 20 dBc = dB Below Carriers –35 –80 –80 0.1 10 Load Resistance (Ω) –60 Harmonic Distortion (dBc) –60 –90 100 –12 –10 –8 –6 –4 –2 0 2 Single-Tone Load Power (dBm) Output Voltage Swing (Vp-p) 12 VO = 2Vp-p RL = 100Ω to 2.5V OPA692 www.ti.com SBOS236E APPLICATIONS INFORMATION WIDEBAND BUFFER OPERATION The OPA692 gives the exceptional AC performance of a wideband current-feedback op amp with a highly linear, highpower output stage. It features internal RF and RG resistors that make it easy to select a gain of +2, +1, or –1 without any external resistors. Requiring only 5.1mA quiescent current, the OPA692 will swing to within 1V of either supply rail and deliver in excess of 160mA at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA692 will deliver greater than 200MHz bandwidth driving a 2VPP output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA692 achieves a comparable power gain with much better linearity. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. Figure 1 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω. The disable control line (DIS) is typically left open to ensure normal amplifier operation. In addition to the usual power-supply decoupling capacitors to ground, a 0.1µF capacitor can be included between the two power-supply pins. This optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 2 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA692 requires minimal input and output voltage headroom compared to other very wideband current-feedback op amps. It will deliver a 3VPP output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2VPP input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1—which puts the input DC bias voltage (2.5V) on the output as well. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 120mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA692 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd-harmonic distortion typical characteristics. +VS +5V 0.1µF 50Ω Source 0.1µF 57.6Ω 6.8µF 806Ω DIS VIN +5V + VO 806Ω OPA692 100Ω VS/2 DIS RF 402Ω + 0.1µF 6.8µF 50Ω Source VIN 50Ω 50Ω RG 402Ω 50Ω Load 0.1µF OPA692 RF 402Ω FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification and Test Circuit. RG 402Ω SINGLE-SUPPLY ADC INTERFACE 0.1µF + 6.8µF –5V FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. Most modern, high-performance ADCs (such as the Texas Instruments ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low-distortion input signal at the ADC input for signal frequencies OPA692 SBOS236E www.ti.com 13 the output, centering the output voltage swing as well. Tested performance at a 20MHz analog input frequency and a 60MSPS clock rate on the converter gives > 58dBc SFDR. exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA692 make it an ideal single-supply ADC driver. Figure 3 shows an example input interface to a very high performance 10-bit, 60MSPS CMOS converter. WIDEBAND VIDEO MULTIPLEXING The OPA692 in the circuit of Figure 3 provides 190MHz bandwidth operating at a signal gain of +2 with a 2VPP output swing. The noninverting input bias voltage is referenced to the midpoint of the ADC signal range by dividing off the top and bottom of the internal ADC reference ladder. With the gain resistor (RG) AC-coupled, this bias voltage has a gain of +1 to One common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple wired-OR video multiplexer can be easily implemented using the OPA692, as shown in Figure 4. +5V +5V RF 402Ω RG 402Ω 0.1µF ADS826 10-Bit 60MSPS Clock 50Ω Input OPA692 2Vp-p 1Vp-p 22pF Input 0.1µF CM 2kΩ DIS +3.5V REFT 0.1µF +2.5V DC Bias 2kΩ +1.5V REFB 0.1µF FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver. +5V 2kΩ |VOUT| < 2.6V VDIS +5V Video 1 DIS OPA692 75Ω 402Ω –5V 402Ω 68.1Ω 75Ω Cable VOUT 402Ω RG-59 402Ω +5V 68.1Ω OPA692 Video 2 DIS 75Ω 2kΩ –5V FIGURE 4. 2-Channel Video Multiplexer. 14 OPA692 www.ti.com SBOS236E Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The make-before-break disable characteristic of the OPA692 ensures that there is always one amplifier controlling the line when using a wired-OR circuit (see Figure 4). Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (68.1Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The matching resistors have been set to get a signal gain of +1 at the load while providing > 20dB return loss at the load. The video multiplexer connection (see Figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated ±1.2V maximum for standard video signal levels. In any case, VOUT must be < ±2.6VPP in order to not exceed the absolute maximum differential input voltage (±1.2V) on the disabled channel. The Disable Operation section shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than ±50mV. Where two outputs are switched (see Figure 4), the output line is always under the control of one amplifier or the other due to the make-beforebreak disable timing. In this case, the switching glitches for two 0V inputs drops to < 20mV. 4-CHANNEL FREQUENCY CHANNELIZER The circuit of Figure 5 is a 4-channel multiplexer. In this circuit the OPA691 provides the drive for all four channels. Each channel includes a bandpass filter and each bandpass filter is set for a different frequency band. This allows the channelizing part of this circuit. The role of the OPA692 is to provide impedance isolation. This is done through the use of four matching resistances (59Ω in this case). These matching resistors ensure that the signals will combine during the transition between channels. They have been used to get a gain of +1 at the load. This circuit may be used with a different number of channels. Its limitation comes from the drive requirement for each channel, as well as the minimum acceptable return loss. The output resistor value (RO) to keep a gain of +1 at the load, depends on the number of channels. For the OPA692, Equation 1 gives: (1) RO = [75Ω • (n – 2) + 804Ω] • 2 1+ [ 241200Ω 75Ω • (n − 2) + 804Ω ] 2 – 1 Where n = number of devices in multiplexer. +5V 75Ω DIS 1 RO 59Ω #1 OPA692 75Ω –5V +5V 75Ω DIS 2 RO 59Ω #2 OPA692 +5V 75Ω 75Ω Cable –5V OPA691 +5V 75Ω RO 59Ω #3 –5V VOUT DIS 3 RG-59 75Ω Load OPA692 75Ω –5V +5V 75Ω DIS 4 RO 59Ω #4 OPA692 75Ω –5V G = +2 Stages FIGURE 5. 4-Channel Frequency Channelizer. OPA692 SBOS236E www.ti.com 15 DELAY-EQUALIZED LOW-PASS FILTER The circuit in Figure 6 realizes a 5th-order Butterworth lowpass filter with a –3dB bandwidth of 20MHz and group delay equalization. This filter is based on the KRC active filter topology using amplifiers with a fixed positive gain ≥ 1. VIN The component values have been predistorted to compensate for the op amps parasitic effects. The low-Q pole section was placed last to minimize noise peaking in the passband, while maintaining good dynamic range performance. OPA692 +5V 200Ω The OPA692 makes a good amplifier for this type of filter. The first stage is the group delay equalizer, which is based on a gain of –1. The second stage has a high-Q pole, uses a gain of +2 for minimum component sensitivity, and also produces a real pole. The last stage has a low-Q pole, and uses a gain of +1 for minimum component sensitivity. 80.6kΩ 2.7nF 402Ω VOUT 402Ω OPA227 200Ω –5V 2.7nF FIGURE 7. Precision Wideband, Unity-Gain Buffer. PRECISION VOLTAGE BUFFER DESIGN-IN TOOLS The precision buffer in Figure 7 combines the DC precision and low 1/f noise of the OPA227 with the high-speed performance of the OPA692. The 80.6kΩ resistor makes the highfrequency and low-frequency nominal gains equal. The OPA692 takes over from the OPA227 at approximately 32kHz. DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA692 in its two package options. Both of these are offered free of 56pF 402Ω 402Ω 49.9Ω 105Ω 226Ω VIN 220pF OPA692 27pF 115Ω OPA692 402Ω 100pF 402Ω 68pF 95.3Ω 226Ω OPA692 39pF VOUT 402Ω 402Ω (Open) FIGURE 6. Butterworth LP Filter with Delay Equalization. 16 OPA692 www.ti.com SBOS236E charge as unpopulated PCBs, delivered with a user's guide. The summary information for these fixtures is shown in the table below. PRODUCT OPA692ID OPA692IDBV PACKAGE ORDERING NUMBER LITERATURE NUMBER SO-8 SOT23-6 DEM-OPA-SO-1A DEM-OPA-SOT-1A SBOU009 SBOU010 over-temperature specifications because the output stage junction temperatures are higher than the minimum specified operating ambient. DRIVING CAPACITIVE LOADS The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA692 product folder. OPERATING SUGGESTIONS GAIN SETTING Setting the gain with the OPA692 is very easy. For a gain of +2, ground the –IN pin and drive the +IN pin with the signal. For a gain of +1, leave the –IN pin open and drive the +IN pin with the signal. For a gain of –1, ground the +IN pin and drive the –IN pin with the signal. As the internal resistor values (not their ratio) change over temperature and process, external resistors should not be used to modify the gain. OUTPUT CURRENT AND VOLTAGE The OPA692 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1V to either supply rail; the tested swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is specified to deliver more than ±160mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage times current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA692 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA692 can drive ±2.5V into 25Ω, or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability (see the Electrical Characteristics). The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristics. As the output transistors deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing), and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve ADC linearity. A high-speed amplifier like the OPA692 can be very susceptible to decreased stability and frequency response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended “RS vs Capacitive Load” and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA692. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA692 output pin (see the Board Layout Guidelines section). DISTORTION PERFORMANCE The OPA692 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high-frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rdharmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network— in the noninverting configuration (see Figure 1) this is the sum of RF + RG, while in the inverting configuration, it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate while the 3rd-harmonic increases at a much lower rate than the expected 3x. Where the test power doubles, the difference between it and the 2nd-harmonic decreases less than the OPA692 SBOS236E www.ti.com 17 expected 6dB, while the difference between it and the 3rd decreases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2VPP for each tone at the load, which requires 8VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show 58dBc difference between the test-tone power and the 3rdorder intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies. NOISE PERFORMANCE The OPA692 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (15pA/√Hz) is significantly lower than earlier solutions while the input voltage noise (1.7nV√Hz) is lower than most unity-gain stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher noninverting input current noise (12pA/√Hz). As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise for the gain settings, available using the OPA692. Figure 8 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI (2) 2 2 EO = ENI2 + (IBNR S ) + 4kTRS NG2 + (IBIRF ) + 4kTRFNG Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 3. (3) 2 4kTRF 2 I R EN = ENI2 + (IBNR S ) + 4kTRS + BI F + NG NG Evaluating these two equations for the OPA692 circuit and component values (see Figure 1) will give a total output spot noise voltage of 8.2nV/√Hz and a total equivalent input spot noise voltage of 4.1nV/√Hz. This total input-referred spot noise voltage is higher than the 1.7nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. DC ACCURACY The OPA692 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Bias current cancellation techniques will not reduce the output DC offset for OPA692. As the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: ±(NG • VOS(max)) + (IBN • RS/2 • NG) ± (IBI • RF) EO OPA692 RS The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 2 shows the general form for the output noise voltage using the terms shown in Figure 8. where NG = noninverting signal gain = ±(2 • 2.5mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA) IBN = ±5mV + 1.75mV ± 10.05mV = –13.3mV → +16.80mV ERS RF √4kTRS 4kT RG RG IBI √4kTRF 4kT = 1.6E –20J at 290°K Minimizing the resistance seen by the noninverting input will give the best DC offset performance. For significantly improved DC accuracy, consider the precision buffer circuit (see Figure 7). DISABLE OPERATION FIGURE 8. Noise Model. 18 The OPA692 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left OPA692 www.ti.com SBOS236E unconnected, the OPA692 will operate normally. To disable, the control pin must be asserted LOW. Figure 9 shows a simplified internal circuit for the disable control feature. +VS Q1 110kΩ 25kΩ IS Control Due to the high output power capability of the OPA692, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL), where RL includes feedback network loading. 15kΩ VDIS THERMAL ANALYSIS –VS FIGURE 9. Simplified Disable Control Circuit. Note that it is the power in the output stage and not in the load that determines internal power dissipation. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As V DIS is pulled LOW, additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 75µA). At this point, any further current pulled out of V DIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode is only that required to operate the circuit of Figure 8. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). As a worst-case example, compute the maximum TJ using an OPA692IDBV (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5VDC: When disabled, the output and input nodes go to a highimpedance state. If the OPA692 is operating in a gain of +1, this will show a very high impedance (4pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain of +2, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured at a gain of –1, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. The Typical Characteristics show these glitches for the circuit of Figure 1 with the input signal set to 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. The transition edge rate (dV/dt) of the DIS control line will influence this glitch. Slowing this edge can be achieved by adding a simple RC filter into the V DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring an adequate logic level swing. PD = 10V • 5.8mA + 52/(4 • (20Ω || 800Ω)) = 378mW Maximum TJ = +85°C + (0.39W • 150°C/W) = 142°C Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower junction temperatures. Remember, this is a worst-case internal power dissipation—use your actual signal and load to compute PDL. The highest possible internal dissipation occurs if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The “Output Voltage and Current Limitations” plot shown in the Typical Characteristics include a boundary for 1W maximum internal power dissipation under these conditions. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA692 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. OPA692 SBOS236E www.ti.com 19 b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat further from the device and may be shared among several devices in the same area of the PC board. shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA692 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of “RS vs Capacitive Load.” This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA692. Any external resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC-board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. All external components should also be placed close to the package. e) Socketing a high-speed part like the OPA692 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA692 onto the board. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended “RS vs Capacitive Load.” Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA692 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the “Distortion vs Load” plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA692 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the 20 INPUT AND ESD PROTECTION The OPA692 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in +V CC External Pin Internal Circuitry –V CC FIGURE 10. Internal ESD Protection. Figure 10. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA692), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. OPA692 www.ti.com SBOS236E Revision History DATE REVISION PAGE 12/08 E 2 3/06 D 16-17 SECTION DESCRIPTION Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C. Design-In Tools Board part number changed. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. OPA692 SBOS236E www.ti.com 21 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) OPA692ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA 692 OPA692IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OAGI OPA692IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OAGI OPA692IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OAGI OPA692IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OAGI OPA692IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA 692 OPA692IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA 692 OPA692IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA 692 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Jan-2013 Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) OPA692IDBVR SOT-23 DBV 6 3000 180.0 OPA692IDBVT SOT-23 DBV 6 250 OPA692IDR SOIC D 8 2500 B0 (mm) K0 (mm) P1 (mm) 8.4 3.2 3.1 1.39 4.0 180.0 8.4 3.2 3.1 1.39 330.0 12.4 6.4 5.2 2.1 Pack Materials-Page 1 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA692IDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 OPA692IDBVT SOT-23 DBV 6 250 210.0 185.0 35.0 OPA692IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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