® OPA OPA2682 268 OPA 2 268 2 For most current data sheet and other product information, visit www.burr-brown.com Dual, Wideband, Fixed Gain BUFFER AMPLIFIER With Disable TM FEATURES ● ● ● ● ● ● ● APPLICATIONS INTERNALLY FIXED GAIN: +2 or ±1 HIGH BANDWIDTH (G = +2): 240MHz LOW SUPPLY CURRENT: 6mA/ch LOW DISABLED CURRENT: 320µA/ch HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V ±5V OR SINGLE +5V OPERATION ● ● ● ● ● ● DESCRIPTION The OPA2682 provides an easy to use, broadband fixed gain, dual buffer amplifier. Depending on the external connections, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of +1 or –1 voltage buffer. Operating on a very low 6mA/ch supply current, the OPA2682 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers high output current with a minimal headroom and crossover distortion. This gives exceptional single supply operation. Using a single +5V supply, the OPA2682 can deliver a 1V to 4V output swing with over 100mA drive current and 200MHz bandwidth. This combination of features makes the OPA2682 an ideal RGB line driver or single-supply ADC input driver. V1 1/2 OPA2682 400Ω 249Ω The OPA2682’s low 6mA/ch supply current is precisely trimmed at 25°C. This trim, along with low drift over temperature, guarantees lower maximum supply current than competing products that report only a room temperature nominal supply current. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it high, gives normal operation. If pulled low, the OPA2682 supply current drops to less than 320µA/ch while the output goes into a high impedance state. This feature may be used for either power savings or for video MUX applications. OPA2682 RELATED PRODUCTS SINGLES DUALS TRIPLES Voltage Feedback OPA680 OPA2680 OPA3680 Current Feedback OPA681 OPA2681 OPA3681 Fixed Gain OPA682 OPA2682 OPA3682 249Ω 400Ω OPA680 400Ω BROADBAND VIDEO LINE DRIVERS VIDEO MULTIPLEXERS MULTIPLE LINE VIDEO DA PORTABLE INSTRUMENTS ADC BUFFERS ACTIVE FILTERS VOUT = 2 • (V1 – V2) 400Ω High-Speed Instrumentation 1/2 OPA2682 499Ω 499Ω Differential Amplifier V2 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © SBOS102 1998 Burr-Brown Corporation PDS-1477B Printed in U.S.A. October, 1999 SPECIFICATIONS: VS = ±5V G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted. OPA2682U, N GUARANTEED(1) TYP PARAMETER +25°C CONDITIONS +25°C 0°C to 70°C –40°C to +85°C UNITS MHz min 220 210 190 MHz min B MHz typ C MHz min B dB max B MHz typ C V/µs min B ns typ C MIN/ TEST MAX LEVEL(2 ) AC PERFORMANCE (Figure 1) Small-Signal Bandwidth (VO < 0.5Vp-p) Bandwidth for 0.1dB Gain Flatness G = +1 330 G = +2 240 G = –1 220 G = +2, VO < 0.5Vp-p 150 50 45 Peaking at a Gain of +1 VO < 0.5Vp-p 0.8 2 4 Large-Signal Bandwidth G = +2, VO = 5Vp-p 210 Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic 1600 1600 45 1200 C G = +2, 4V Step 2100 G = +2, VO = 0.5V Step 1.7 G = +2, VO = 5V Step 2.0 ns typ C G = +2, VO = 2V Step 12 ns typ C G = +2, VO = 2V Step 8 ns typ C G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω –63 dBc typ C RL = ≥ 500Ω –81 dBc typ C RL = 100Ω –78 dBc typ C RL = ≥ 500Ω –95 dBc typ C B Input Voltage Noise f > 1MHz 2.2 3.0 3.4 3.6 nV/√Hz max Non-Inverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B Differential Gain Differential Phase Channel-to-Channel Crosstalk NTSC, RL = 150Ω 0.001 % typ C NTSC, RL = 37.5Ω 0.008 % typ C C NTSC, RL = 150Ω 0.01 deg typ NTSC, RL = 37.5Ω 0.05 deg typ C f = 5MHz –70 dBc typ C C DC PERFORMANCE(3) Gain Error G = +1 ±0.2 G = +2 ±0.3 G = –1 –1.0 –2.5, +1.5 % typ % max A % typ C Internal RF and RG Maximum 400 480 510 520 Ω max A Minimum 400 320 310 290 Ω min A Average Drift Input Offset Voltage VCM = 0V Average Offset Voltage Drift VCM = 0V Non-Inverting Input Bias Current VCM = 0V Average Non-Inverting Input Bias Current Drift VCM = 0V Inverting Input Bias Current VCM = 0V Average Inverting Input Bias Current Drift VCM = 0V 0.13 0.13 0.13 %/°C max B ±1.3 ±5 ±6.5 ±7.5 mV max A +35 +40 µV/°C max B +30 +55 ±65 ±85 µA max A –400 –400 nA/°C max B ±10 ±40 ±50 ±55 µA max A –125 –150 nA°C max B ±3.3 ±3.2 INPUT ±3.5 Common-Mode Input Range Non-Inverting Input Impedance ±3.4 100 || 2 V min B kΩ || pF typ C OUTPUT Voltage Output Swing No Load ±4.0 ±3.6 V min A ±3.9 ±3.8 ±3.7 ±3.7 100Ω Load ±3.6 ±3.3 V min A +190 +160 +140 +80 mA min A –150 –135 –130 –80 mA min A typ C Current Output, Sourcing Sinking Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA2682 2 SPECIFICATIONS: VS = ±5V (Cont.) G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted. OPA2682U, N GUARANTEED(1) TYP PARAMETER DISABLE/POWER DOWN (DIS Pin) Power Down Supply Current (+VS) +25°C CONDITIONS +25°C 0°C to 70°C –40°C to +85°C UNITS MIN/ TEST MAX LEVEL(2 ) SO-14 Only VDIS = 0, Both Channels Disable Time Enable Time –640 µA typ C 100 ns typ C 25 ns typ C G = +2, 5MHz 70 dB typ C 4 pF typ C Turn On Glitch G = +2, RL = 150Ω ±50 mV typ C Turn Off Glitch G = +2, RL= 150Ω ±20 mV typ C A Off Isolation Output Capacitance in Disable Enable Voltage 3.3 3.5 3.6 3.7 V min Disable Voltage 1.8 1.7 1.6 1.5 V max A 100 160 160 160 µA max A V typ C ±6 ±6 ±6 V max A Control Pin Input Bias Current (DIS) VDIS = 0, Each Channel POWER SUPPLY ±5 Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current VS = ±5V 6 6.4 6.5 6.6 mA/chan max A Min Quiescent Current VS = ±5V 6 5.6 5.5 5.0 mA/chan min A Input Referred 56 50 48 47 dB min A –40 to +85 °C typ C U SO-8 125 °C/W typ C N SO-14 100 °C/W typ C Power Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature +23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. ® 3 OPA2682 SPECIFICATIONS: VS = +5V G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VCM = 2.5V (Figure 2 for AC performance only), unless otherwise noted. OPA2682U, N GUARANTEED(1) TYP PARAMETER AC PERFORMANCE (Figure 2) Small-Signal Bandwidth (VO < 0.5Vp-p) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise CONDITIONS +25°C G = +1 G = +2 G = –1 G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step 290 220 200 100 0.4 210 830 1.5 2.0 14 9 +25°C 0°C to 70°C –40°C to +85°C 180 140 110 50 2 35 4 23 700 680 570 UNITS MIN/ TEST MAX LEVEL(2) MHz MHz MHz MHz dB MHz V/µs ns ns ns ns min min typ min max typ min typ typ typ typ C B C B B C B C C C C C G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS /2 –61 dBc typ RL = ≥ 500Ω to VS /2 –69 dBc typ C RL = 100Ω to VS /2 –69 dBc typ C RL = ≥ 500Ω to VS /2 f > 1MHz f > 1MHz f > 1MHz –73 2.2 12 15 dBc nV/√Hz pA/√Hz pA/√Hz typ max max max C B B B % typ C % max A % typ C B 3.0 14 18 3.4 14 18 3.6 15 19 DC PERFORMANCE(3) Gain Error G = +1 ±0.2 G = +2 ±0.3 G = –1 –1.0 –2.5, +1.5 Internal RF and RG Minimum 400 480 510 520 Ω min Maximum 400 320 310 290 Ω max B ±1 0.13 ±5 +40 +65 ±5 ±20 0.13 ±6 +15 ±75 –300 ±25 –125 0.13 ±7 +20 ±95 –350 ±35 –175 %/°C mV µV/°C µA nA/°C µA nA°C max max max max max max max B A B A B A B 1.5 3.5 100 || 2 1.6 3.4 1.7 3.3 1.8 3.2 V V kΩ || pF min max typ B B C 4.0 3.9 1.0 1.1 +150 –110 0.03 3.8 3.7 1.2 1.3 +110 –75 3.7 3.6 1.3 1.4 +110 –70 3.5 3.4 1.5 1.6 +60 –50 V V V V mA mA Ω min min min min min min typ A A A A A A C Average Drift Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V INPUT Least Positive Input Voltage Most Positive Input Voltage Non-Inverting Input Impedance OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Sinking Output Impedance No Load RL = 100Ω No Load RL = 100Ω G = +2, f = 100kHz ® OPA2682 4 SPECIFICATIONS: VS = +5V (Cont.) G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VCM = 2.5V (Figure 2 for AC performance only), unless otherwise noted. OPA2682U, N GUARANTEED(1) TYP PARAMETER DISABLE/POWER DOWN (DIS Pin) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single Supply Operating Voltage Maximum Single Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (–PSRR) +25°C CONDITIONS SO-14 Only VDIS = 0, Both Channels G = +2, 5MHz G = +2, RL = 150Ω, VIN = VCM G = +2, RL = 150Ω, VIN = VCM VDIS = 0, Each Channel +25°C 0°C to 70°C –40°C to +85°C typ typ typ typ typ typ typ min max typ C C C C C B B A A C V V mA/chan mA/chan dB typ max max min typ C A A A C –40 to +85 °C typ C 125 100 °C/W °C/W typ typ C C 4.8 4.8 48 TEMPERATURE RANGE Specification: P, U, N Thermal Resistance, θJA U SO-8 N SO-14 MIN/ TEST MAX LEVEL(2) µA ns ns dB pF mV mV V V µA –540 100 25 65 4 ±50 ±20 3.3 1.8 100 3.5 1.7 3.6 1.6 3.7 1.5 12 5.3 4.1 12 5.4 3.7 12 5.4 3.6 5 VS = ±5V VS = ±5V Input Referred UNITS NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature +23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. ® 5 OPA2682 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation(1) ............................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: ........................................ –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. NOTE:: (1) Packages must be derated based on specified θJA. Maximum TJ must be observed. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATIONS Top View SO-8 SO-14 OPA2682U Out A 400Ω 1 400Ω 8 +VS –In A 1 14 Out A 7 Out B +In A 2 13 NC 6 –In B DIS A 3 12 NC 5 +In B –VS 4 DIS B 5 10 NC +In B 6 9 NC –In B 7 8 Out B 400Ω –In A 2 400Ω +In A 400Ω 3 400Ω –VS 4 OPA2682N 400Ω 11 +VS 400Ω NC = No Connection PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPA2682U SO-8 Surface Mount 182 –40°C to +85°C OPA2682U " " " " " OPA2682N SO-14 Surface Mount 235 –40°C to +85°C OPA2682N " " " " " TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA OPA2682U OPA2682U/2K5 OPA2682N OPA2682N/2K5 Rails Tape and Reel Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA2682U/2K5” will get a single 2500-piece Tape and Reel. ® OPA2682 6 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). LARGE-SIGNAL FREQUENCY RESPONSE 8 1 7 G = +1 0 –2 G = +2 –3 –4 RL = 100Ω 6 –1 Gain (1dB/div) Normalized Gain (1dB/div) SMALL-SIGNAL FREQUENCY RESPONSE 2 G = –1 –5 5 2Vp-p 4 3 2 –6 0 –7 –1 –8 7Vp-p –2 0 250MHz 500MHz 0 Frequency (50MHz/div) SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE VO = 0.5Vp-p VO = 5Vp-p Output Voltage (1V/div) +3 200 100 0 –100 –200 +2 +1 0 –1 –2 –3 –300 –4 –400 Time (5ns/div) Time (5ns/div) CHANNEL-TO-CHANNEL CROSSTALK LARGE-SIGNAL DISABLE/ENABLE RESPONSE 4.0 VDIS 2.0 0 Output Voltage 2.0 1.6 1.2 0.8 VIN = +1V 0 –10 –20 Crosstalk (10dB/div) 6.0 VDIS (2V/div) Output Voltage (100mV/div) 250MHz +4 300 Output Voltage (400mV/div) 125MHz Frequency (25MHz/div) 400 0.4 1Vp-p 4Vp-p 1 –30 –40 –50 –60 –70 –80 (SO-14 Only) –90 0 –100 1 Time (50ns/div) 10 100 Frequency (MHz) ® 7 OPA2682 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd HARMONIC DISTORTION vs FREQUENCY –50 –50 VO = 2Vp-p Harmonic Distortion (dBc) Harmonic Distortion (dBc) f = 5MHz –60 2nd Harmonic –70 –80 3rd Harmonic –60 –70 G = +1 G = +2 –80 G = –1 –90 –90 0.1 1 5 0.1 Frequency (MHz) 3rd HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE Harmonic Distortion (dBc) VO = 2Vp-p Harmonic Distortion (dBc) 20 –50 –50 –60 –70 G = +2 G = –1 G = +1 –80 VO = 2Vp-p f0 = 5MHz –60 2nd Harmonic –70 3rd Harmonic –80 –90 –90 0.1 10 1 10 20 100 1000 Frequency (MHz) RL (Ω) INPUT VOLTAGE AND CURRENT NOISE DENSITY TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS –40 3rd-Order Spurious Level (dBc) 100 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) 10 1 Output Voltage (Vp-p) Inverting Input Current Noise 15.1pA/√Hz 10 Non-Inverting Input Current Noise 12.2pA/√Hz 2.2nV/√Hz Voltage Noise dBc = dB below carriers –45 –50 50MHz –55 –60 –65 –70 20MHz –75 –80 10MHz –85 Load Power at Matched 50Ω Load –90 1 100 1k 10k 100k 1M –8 10M ® OPA2682 –6 –4 –2 0 2 4 Single-Tone Load Power (dBm) Frequency (Hz) 8 6 8 10 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 60 Gain to Capacitive Load (3dB/div) 15 50 30 20 10 0 CL = 10pF 9 CL = 22pF 6 3 CL = 47pF 0 VIN –3 RS 1/2 OPA2682 –6 400Ω –9 CL 10 –12 100 1kΩ is optional. 0 CL = 100pF 150MHz Capacitive Load (pF) 300MHz Frequency (30MHz/div) POWER SUPPLY REJECTION RATIO vs FREQUENCY SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 70 20 65 +PSRR 60 –PSRR Supply Current (5.0mA/div) Rejection Ratio (dB) 1kΩ 400Ω –15 1 VO 55 50 45 40 35 30 200 Sourcing Output Current Sinking Output Current 15 150 10 Output Current (mA) RS (Ω) 40 12 100 Quiescent Supply Current 5 50 25 20 0 103 104 105 106 107 108 0 –40 –20 0 40 60 80 100 120 140 Ambient Temperature (°C) Frequency (Hz) COMPOSITE VIDEO dG/dP TYPICAL DC DRIFT OVER TEMPERATURE 0.05 5 Positive Video Negative Sync 50 4 Input Offset Voltage (mV) 0.04 dP dG/dP (%/°) 20 0.03 0.02 0.01 dG 0 40 Non-Inverting Input Bias Current 3 30 2 20 Inverting Input Bias Current 1 0 10 0 VIO –1 –10 –2 –20 –3 –30 –4 –40 –5 1 2 3 4 –50 –40 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Number of 150Ω Loads ® 9 OPA2682 Input Bias Currents (µA) 102 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1). OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 3 VO (Volts) 2 1 Output Current Limited +5 1W Internal Power Limit One Channel Only Output Impedance (Ω) 4 CLOSED-LOOP OUTPUT IMPEDANCE 10 25Ω Load Line 0 50Ω Load Line –1 100Ω Load Line –2 50Ω 1 ZO 400Ω 400Ω 0.1 –5 –3 –4 1/2 OPA2682 1W Internal Power Limit Output Current Limit 0.01 –5 –300 –200 –100 0 100 200 10k 300 ® OPA2682 100k 1M Frequency (Hz) IO (mA) 10 10M 100M TYPICAL PERFORMANCE CURVES: VS = +5V G = +2 and RL = 100Ω to VCM = +2.5V, unless otherwise noted (see Figure 2). LARGE-SIGNAL FREQUENCY RESPONSE 8 1 7 RL = 100Ω to 2.5V G = +2 –2 G = +1 –3 –4 –5 VO = 1Vp-p 5 4 VO = 2Vp-p 3 2 1 G = –1 –6 0 –7 –1 –2 –8 0 250MHz 0 500MHz 125 LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 4.5 2.10 4.1 VO = 0.5Vp-p Output Voltage (400mV/div) 2.9 Output Voltage (100mV/div) 250 Frequency (25MHz/div) Frequency (50MHz/div) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 VO = 2Vp-p 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 2.1 0.5 2.0 Time (5ns/div) Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 70 Gain to Capacitive Load (3dB/div) 15 60 50 RS (Ω) VO = 0.5Vp-p 6 0 –1 Gain (1dB/div) Normalized Gain (1dB/div) SMALL-SIGNAL FREQUENCY RESPONSE 2 40 30 20 10 0 CL = 10pF CL = 47pF 12 9 CL = 22pF 6 +5V 3 806Ω 0 VIN 0.1µF 1/2 –3 57.6Ω VO 806Ω OPA2682 RS C L –6 1kΩ 400Ω –9 400Ω –12 (1kΩ is optional) CL = 100pF 0.1µF –15 1 10 100 0 Capacitive Load (pF) 100MHz 200MHz Frequency (20MHz/div) ® 11 OPA2682 TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.) G = +2 and RL = 100Ω to VCM = +2.5V, unless otherwise noted (see Figure 2). HARMONIC DISTORTION vs SUPPLY VOLTAGE TWO-TONE, 3rd-ORDER SPURIOUS LEVEL –50 –40 VO = 2Vp-p f0 = 5MHz Harmonic Distortion (dBc) 3rd-Order Spurious (dBc) dBc = dB Below Carriers –50 50MHz –60 20MHz –70 10MHz –80 –60 2nd Harmonic –70 –80 3rd Harmonic Load Power at Matched 50Ω Load –90 –90 –14 –12 –10 –8 –6 –4 –2 0 5 2 ® OPA2682 6 7 8 9 10 Total Supply Voltage (V) Single-Tone Load Power (dBm) 12 11 12 Figure 2 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA2682 requires minimal input and output voltage headroom compared to other fixed-gain buffer amplifiers. It will deliver a 3Vp-p output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1, which puts the input DC bias voltage (2.5V) on the output as well. On a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 75mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA2682 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd harmonic distortion plots. APPLICATIONS INFORMATION WIDEBAND BUFFER OPERATION The OPA2682 gives the exceptional AC performance of a wideband, current-feedback op amp with a highly linear, high power output stage. It features internal RF and RG resistors which make it easy to select a gain of +2, +1, or –1 without any external resistors. Requiring only 6mA/ch quiescent current, the OPA2682 will swing to within 1V of either supply rail and deliver in excess of 135mA (guaranteed) at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA2682 will deliver greater than 200MHz bandwidth driving a 2Vp-p output into 100Ω on a single +5V supply. Previous current-boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA2682 achieves a comparable power gain with much better linearity. The primary advantage of the internal current-feedback op amp over a voltage-feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. Figure 1 shows the DC-coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 800Ω = 89Ω. The disable control line (DIS) is typically left open (SO-14 only) to guarantee normal amplifier operation. In addition to the usual power supply decoupling capacitors to ground, a 0.1µF capacitor can be included between the two power supply pins. This optional added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. +5V +VS 0.1µF 50Ω Source + 6.8µF 806Ω 0.1µF VIN 57.6Ω 1/2 OPA2682 806Ω VO 100Ω VS/2 RF 400Ω +5V +VS RG 400Ω + 0.1µF 50Ω Source 6.8µF VIN 50Ω 1/2 OPA2682 50Ω 0.1µF 50Ω Load FIGURE 2. AC-Coupled, G = +2, Single Supply Specification and Test Circuit. RF 400Ω HIGH SPEED INSTRUMENTATION AMPLIFIER RG 400Ω 0.1µF –VS + The front page shows an instrumentation amplifier based on the OPA2682. The differential gain for this circuit is 2.0. The inputs are high impedance, with only 1pF to ground at each input. The loads on the OPA2682 outputs were made equal in order to achieve the best harmonic distortion possible. 6.8µF –5V FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. ® 13 OPA2682 DIFFERENTIAL ADC DRIVER is always under control. To avoid large switching glitches, switch during the sync or retrace portions of the video signal—the two inputs should be almost equal at these times. Because the output is always under control, the switching glitches for two 0V inputs are < 20mV. This circuit also ensures that the maximum differential voltage across the inputs of the unselected channel do not exceed the ±1.2V Maximum Rating when using standard video signal levels. The circuit in Figure 3 converts a single-ended input to a differential signal which drives the ADS823 converter. The common-mode biasing uses a simple resistor divider connected to the ADC’s reference voltages. Connecting the top op amp’s RG to its non-inverting input provides a bias current path for the non-inverting input. This connection also improves distortion performance because both op amps operate with nearly equal noise gains. The two output resistors isolate the outputs from each other when switching between channels. The feedback network of the disabled amplifier forms part of the output impedance and attenuates the output signal slightly. The 68.1Ω value compensates for the attenuation, and still provides good back-matching for the cable (return loss > 20dB). MULTIPLEXED VIDEO AMPLIFIER The multiplexed video amplifier in Figure 4 “wire-ORs” the two output signals together. The “make-before-break” disable characteristic of the OPA2682N ensures that the output +5V +5V 0.10µF VIN +VS 100Ω 1/2 OPA2682 +In 50pF 400Ω 400Ω 400Ω 400Ω ADS823 10-Bit 60MSPS 100Ω –In 50pF 1/2 OPA2682 0.10µF REFT (+3.5V) GND REFB (+1.5V) 0.10µF 2kΩ 0.10µF 2kΩ 2.5V FIGURE 3. Wideband, AC-Coupled, Single-Supply A/D Driver. +5V 2kΩ VOUT < 2.6V VDIS +5V Video 1 1/2 OPA2682N 75Ω DIS 400Ω 400Ω 68.1Ω 75Ω Cable 400Ω RG-59 400Ω 68.1Ω 1/2 OPA2682N Video 2 DIS 75Ω –5V 2kΩ FIGURE 4. Two-Channel Video Multiplexer (SO-14 only). ® OPA2682 14 VOUT AC-COUPLED DIFFERENTIAL LOWPASS FILTER MACROMODELS The circuit in Figure 5 gives a single +5V supply, 3rdorder Chebyshev lowpass filter with 0.5dB of ripple in the passband and a –3dB bandwidth of 20MHz. This filter is based on the KRC active filter topology, which uses an amplifier with a fixed gain ≥ 1. The OPA2682 makes a good amplifier for this type of filter. The component values have been pre-distorted to compensate for the op amp’s parasitic effects. Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2682 is available through the Burr-Brown Internet web page (http://www.burr-brown.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion, temperature performance, or dG/dφ characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. DESIGN-IN TOOLS APPLICATIONS SUPPORT The Burr-Brown Applications Department is available for design assistance at 1-800-548-6132 (US/Canada only). The Burr-Brown internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. OPERATING SUGGESTIONS GAIN SETTING DEMONSTRATION BOARDS Setting the gain with the OPA2682 is very easy. For a gain of +2, ground the –IN pin and drive the +IN pin with the signal. For a gain of +1, leave the –IN pin open and drive the +IN pin with the signal. For a gain of –1, ground the +IN pin and drive the –IN pin with the signal. Since the internal resistor values change significantly over temperature and process, external resistors should not be used to modify the gain. Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA2682 in its two package styles. These are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. PRODUCT PACKAGE DEMO BOARD NUMBER OPA2682U OPA2682N 8-Lead SO-8 14-Lead SO-14 DEM-OPA268xU DEM-OPA268xN LITERATURE REQUEST NUMBER MKT-352 MKT-353 OUTPUT CURRENT AND VOLTAGE The OPA2682 provides output voltage and current capabilities that are unsurpassed in a low-cost, monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1V to either supply rail; the guaranteed swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is guaranteed to deliver more than ±135mA. Contact the Burr-Brown applications support line (1-800-548-6132) to request any of these boards, using the literature request number. +5V 82pF 0.10µF 51.1Ω 105Ω 205Ω +5V 1/2 OPA2682 1.10kΩ 400Ω 400Ω 400Ω 400Ω 1kΩ 0.10µF VIN 180pF 18pF VOUT 0.10µF 1kΩ 1.10kΩ 0.10µF 51.1Ω 105Ω 1/2 OPA2682 205Ω 82pF FIGURE 5. Single-Supply, 3rd-Order Differential Chebyshev Low-Pass Filter. ® 15 OPA2682 The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage x current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Performance Curves. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2682’s output drive capabilities, noting that the graph is bounded by a “Safe Operating Area” of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA2682 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit for a single channel. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability, as shown in the Typical Specifications. decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2682. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2682 output pin (see Board Layout Guidelines). The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. DISTORTION PERFORMANCE The OPA2682 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. Increasing the load impedance improves 2nd harmonic distortion directly. Remember that the total load includes the feedback network-in the non-inverting configuration (see Figure 1); this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Performance Curves show the 2nd harmonic increasing at a little less than the expected 2X rate while the 3rd harmonic increases at a little less than the expected 3X rate. Where the test power doubles, the difference between it and the 2nd harmonic decreases less than the expected 6dB while the difference between it and the 3rd decreases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Performance Curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2Vp-p for each tone at the load, which requires 8Vp-p for the overall 2-tone envelope at the output pin), the Typical Performance Curves show 62dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies. To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power supply pin (8-pin packages) will, in most cases, destroy the amplifier. If additional short-circuit protection is required, consider a small series resistor in the power supply leads. This will, under heavy output loads, reduce the available output voltage swing. A 5Ω series resistor in each power supply lead will limit the internal power dissipation to less than 1W for an output short circuit while decreasing the available output voltage swing only 0.5V for up to 100mA desired load currents. Always place the 0.1µF power supply decoupling capacitors after these supply current limiting resistors, and directly at the supply pins. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter—including additional external capacitance which may be recommended to improve A/D linearity. A high-speed amplifier like the OPA2682 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s openloop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can ® OPA2682 16 NOISE PERFORMANCE DC ACCURACY The OPA2682 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (15pA/√Hz) is significantly lower than earlier solutions while the input voltage noise (2.2nV√Hz) is lower than most unity gain stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher non-inverting input current noise (12pA/√Hz). As long as the AC source impedance looking out of the non-inverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 6 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA√Hz. The OPA2682 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Typical Specifications show an input offset voltage comparable to high speed voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Bias current cancellation techniques will not reduce the output DC offset for OPA2682. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: ±(NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF) where NG = non-inverting signal gain = ±(2 • 5.0mV) + (55µA • 25Ω • 2) ± (480Ω • 40µA) = ±10mV + 2.8mV ± 19.2mV ENI = –26.4mV → +32.0mV EO OPA2682 RS Minimizing the resistance seen by the non-inverting input will give the best DC offset performance. IBN ERS DISABLE OPERATION (SO-14 Only) RF √4kTRS IBI RG 4kT RG The OPA2682N provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA2682N will operate normally. To disable, the control pin must be asserted low. Figure 7 shows a simplified internal circuit for the disable control feature. √4kTRF 4kT = 1.6 • 10–20 FIGURE 6. Noise Model. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled low, additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 100µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approxi- The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 6. (1) EO = (E 2 NI ) + ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG 2 2 +VS Dividing this expression by the noise gain (NG = (1+RF/RG)) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in Equation 2. (2) 15kΩ E N = E NI + ( I BN R S ) 2 2 I R 2 4kTR F + 4kTR S + BI F + NG NG Q1 Evaluating these two equations for the OPA2682 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 8.7nV/√Hz and a total equivalent input spot noise voltage of 4.4nV/√Hz. This total input-referred spot noise voltage is higher than the 2.2nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. 25kΩ VDIS 110kΩ IS Control –VS FIGURE 7. Simplified Disable Control Circuit. ® 17 OPA2682 Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. mately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode is only that required to operate the circuit of Figure 7. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high impedance state. If the OPA2682N is operating in a gain of +1, this will show a very high impedance (4pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain of +2, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as at a gain of –1, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2682U (SO-8 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C with both outputs driving a grounded 100Ω load to +2.5V: One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 8 shows these glitches for the circuit of Figure 1 with the input signal set to zero volts. The glitch waveform at the output pin is plotted along with the DIS pin voltage. Output Voltage (20mV/div) 40 PD = 10V • 13.2mA + 2 [52/(4 • (20Ω || 800Ω)) = 273mW Maximum TJ = +85°C + (0.27W • 125°C/W) = 119°C This worst-case condition is still well within rated maximum TJ for this 100Ω load. Heavier loads may, however, exceed the 175°C maximum junction temperature rating. Careful attention to internal power dissipation is required, and forced air cooling may be required. Output Voltage (0V Input) 20 0 BOARD LAYOUT GUIDELINES –20 –40 Achieving optimum performance with a high frequency amplifier like the OPA2682 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: 4.8V VDIS 0.2V a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability; on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Time (20ns/div) FIGURE 8. Disable/Enable Glitch. The transition edge rate (dV/dt) of the DIS control line will influence this glitch. For the plot of Figure 8, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the VDIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring an adequate logic level swing. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. THERMAL ANALYSIS Due to the high output power capability of the OPA2682, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. ® OPA2682 18 c) Careful selection and placement of external components will preserve the high frequency performance of the OPA2682. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axiallyleaded resistors can also provide good high-frequency performance. Keep the leads and PC board trace lengths as short as possible. Never use wirewound type resistors in a high frequency application. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2682 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2682 onto the board. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA2682 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion vs Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2682 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2682 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source INPUT AND ESD PROTECTION The OPA2682 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 9. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA2682), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +V CC External Pin Internal Circuitry –V CC FIGURE 9. Internal ESD Protection. ® 19 OPA2682 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated