TOSHIBA TH58NVG5S0FTA20

TOSHIBA CONFIDENTIAL
TENTATIVE
TH58NVG5S0FTA20
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
32 GBIT (4G × 8 BIT) CMOS NAND E PROM
DESCRIPTION
The TH58NVG5S0F is a single 3.3V 32 Gbit (36,305,895,424 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 232) bytes × 64 pages × 16384 blocks.
The device has two 4328-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 4328-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 14.5 Kbytes: 4328 bytes × 64 pages).
The TH58NVG5S0F is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
x8
4328 × 256K × 8 × 4
4328 × 8
4328 bytes
(256K + 14.5K) bytes
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
•
Mode control
Serial input/output
Command control
•
Number of valid blocks
Min 16064 blocks
Max 16384 blocks
•
Power supply
VCC = 2.7V to 3.6V
•
Access time
Cell array to register
Serial Read Cycle
30 µs max
25 ns min (CL=100pF)
•
Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
3 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
200 µA max
•
•
Package
TSOP I 48-P-1220-0.50C
•
4bit ECC for each 512Byte is required.
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TH58NVG5S0FTA20
PIN ASSIGNMENT (TOP VIEW)
TH58NVG5S0FTA20
×8
NC
NC
NC
NC
NC
RY / BY 2
RY / BY 1
RE
CE 1
CE 2
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
×8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
PSL
NC
VCC
VSS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
PINNAMES
I/O1 to I/O8
I/O port
CE 1
Chip enable (Chip A,B)
CE 2
Chip enable (Chip C,D)
WE
Write enable
RE
Read enable
CLE
Command latch enable
ALE
Address latch enable
PSL
Power on select
WP
Write protect
RY/BY 1
Ready/Busy (Chip A,B)
RY/BY 2
Ready/Busy (Chip C,D)
VCC
Power supply
VSS
Ground
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TH58NVG5S0FTA20
BLOCK DIAGRAM
VCC VSS
(Chip A, B)
Status register
I/O1
to
Address register
Column buffer
I/O
Control circuit
Column decoder
I/O8
Command register
Data register
CLE
ALE
WE
RE
WP
Logic control
Control circuit
PSL
Row address decoder
CE 1
Row address buffer
decoder
Sense amp
Memory cell array
RY / BY 1
RY / BY
HV generator
Status register
Address register
Column buffer
I/O
Control circuit
Column decoder
Command register
Data register
Control circuit
Row address decoder
Logic control
Row address buffer
decoder
Sense amp
CE 2
Memory cell array
RY / BY 2
RY / BY
HV generator
(Chip C, D)
3
VCC VSS
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TH58NVG5S0FTA20
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
VCC
Power Supply Voltage
−0.6 to 4.6
V
VIN
Input Voltage
−0.6 to 4.6
V
VI/O
Input /Output Voltage
PD
Power Dissipation
0.3
W
TSOLDER
Soldering Temperature (10 s)
260
°C
TSTG
Storage Temperature
−55 to 150
°C
TOPR
Operating Temperature
0 to 70
°C
−0.6 to VCC + 0.3
(≤ 4.6 V)
V
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
MAX
UNIT
CIN
Input
VIN = 0 V
⎯
40
pF
COUT
Output
VOUT = 0 V
⎯
40
pF
*
This parameter is periodically sampled and is not tested for every device.
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TH58NVG5S0FTA20
VALID BLOCKS
SYMBOL
NVB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
UNIT
16064
⎯
16384
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
2.7
⎯
3.6
V
VCC
Power Supply Voltage
VIH
High Level input Voltage
2.7 V ≤ VCC ≤ 3.6 V
Vcc x 0.8
⎯
VCC + 0.3
V
VIL
Low Level Input Voltage
2.7 V ≤ VCC ≤ 3.6 V
−0.3*
⎯
Vcc x 0.2
V
−2 V (pulse width lower than 20 ns)
*
DC CHARACTERISTICS (Ta = 0 to 70℃, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
CONDITION
MIN
TYP.
MAX
UNIT
IIL
Input Leakage Current
VIN = 0 V to VCC
⎯
⎯
±10
µA
ILO
Output Leakage Current
VOUT = 0 V to VCC
⎯
⎯
±10
µA
PSL = GND or NU
⎯
⎯
30
PSL = VCC, FFh command input after
Power On
⎯
⎯
30
CE = VIL, IOUT = 0 mA, tcycle = 25 ns
⎯
⎯
30
mA
mA
ICCO0 *1
Power On Reset Current
ICCO1 *2
Serial Read Current
ICCO2 *2
Programming Current
⎯
⎯
⎯
30
mA
ICCO3 *2
Erasing Current
⎯
⎯
⎯
30
mA
ICCS
Standby Current
⎯
⎯
200
µA
VOH
High Level Output Voltage
IOH = −0.4 mA
2.4
⎯
⎯
V
VOL
Low Level Output Voltage
IOL = 2.1 mA
⎯
⎯
0.4
V
IOL
( RY / BY )
Output current of RY / BY
VOL = 0.4 V
pin
⎯
8
⎯
mA
CE = VCC − 0.2 V, WP = 0 V/VCC,
PSL = 0 V/VCC/NU
*1 Refer to application note (2) for detail
*2 Icco1/2/3 are the value of one chip, and an unselected chip is in Standby mode.
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TH58NVG5S0FTA20
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70℃, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
CLE Setup Time
12
⎯
ns
tCLH
CLE Hold Time
5
⎯
ns
tCS
CE Setup Time
20
⎯
ns
tCH
CE Hold Time
5
⎯
ns
tWP
Write Pulse Width
12
⎯
ns
tALS
ALE Setup Time
12
⎯
ns
tALH
ALE Hold Time
5
⎯
ns
tDS
Data Setup Time
12
⎯
ns
tDH
Data Hold Time
5
⎯
ns
tWC
Write Cycle Time
25
⎯
ns
tWH
WE High Hold Time
10
⎯
ns
tWW
WP High to WE Low
100
⎯
ns
tRR
Ready to RE Falling Edge
20
⎯
ns
tRW
Ready to WE Falling Edge
20
⎯
ns
tRP
Read Pulse Width
12
⎯
ns
tRC
Read Cycle Time
25
⎯
ns
tREA
RE Access Time
⎯
20
ns
tCEA
CE Access Time
⎯
25
ns
tCLR
CLE Low to RE Low
10
⎯
ns
tAR
ALE Low to RE Low
10
⎯
ns
tRHOH
RE High to Output Hold Time
25
⎯
ns
tRLOH
RE Low to Output Hold Time
5
⎯
ns
tRHZ
RE High to Output High Impedance
⎯
60
ns
tCHZ
CE High to Output High Impedance
⎯
20
ns
tCSD
CE High to ALE or CLE Don’t Care
0
⎯
ns
tREH
RE High Hold Time
10
⎯
ns
tIR
Output-High-impedance-to- RE Falling Edge
0
⎯
ns
tRHW
RE High to WE Low
60
⎯
ns
tWHC
WE High to CE Low
30
⎯
ns
tWHR
WE High to RE Low
60
⎯
ns
tR
Memory Cell Array to Starting Address
⎯
30
µs
tDCBSYR1
Data Cache Busy in Read Cache (following 31h and 3Fh)
⎯
30
µs
tDCBSYR2
Data Cache Busy in Page Copy (following 3Ah)
⎯
35
µs
tWB
WE High to Busy
⎯
100
ns
tRST
Device Reset Time (Ready/Read/Program/Erase)
⎯
10/10/30/500
µs
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
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TH58NVG5S0FTA20
AC TEST CONDITIONS
CONDITION
PARAMETER
VCC: 2.7 to 3.6V
Input level
0V to Vcc
Input pulse rise and fall time
3 ns
Input comparison level
Vcc / 2
Output data comparison level
Vcc / 2
CL (100 pF) + 1 TTL
Output load
Note:
Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0 to 70℃, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
tPROG
Average Programming Time
⎯
300
700
µs
tDCBSYW1
Data Cache Busy Time in Write Cache (following 11h)
⎯
0.5
1
µs
tDCBSYW2
Data Cache Busy Time in Write Cache (following 15h)
⎯
⎯
700
µs
N
Number of Partial Program Cycles in the Same Page
⎯
⎯
4
tBERASE
Block Erasing Time
⎯
3
10
NOTES
(2)
(1)
ms
(1) Refer to Application Note (12) toward the end of this document.
(2) tDCBSYW2 depends on the timing between internal programming time and data in time.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
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TH58NVG5S0FTA20
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
tDS
tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS
tCS
tCLH
tCH
CE
tWP
WE
tALS
tALH
ALE
tDS
tDH
I/O
: VIH or VIL
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TH58NVG5S0FTA20
Address Input Cycle Timing Diagram
tCLS
tCLH
CLE
tCH
tCS
tCS
tWC
tWC
tCH
CE
tWP
tWH
tWP
tWH
tWP
tWH
tWP
tWH
tWP
WE
tALS
tALH
ALE
tDS
I/O
tDH
tDS
CA0 to 7
tDH
tDS
CA8 to 12
tDH
tDS
PA0 to 7
tDH
PA8 to 15
tDS
tDH
PA16 to 18
: VIH or VIL
Data Input Cycle Timing Diagram
tCLS
tCLH
CLE
tCH
tCS
tCS
tCH
CE
tALS
tALH
tWC
ALE
tWP
tWH
tWP
tWP
WE
tDS
I/O
tDH
tDS
DIN0
tDH
DIN1
9
tDS
tDH
DIN4327*
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TH58NVG5S0FTA20
Serial Read Cycle Timing Diagram
tRC
CE
tRP
tREH
RE
tRHZ
tRHOH
tREA
tRP
tREA
tCHZ
tRP
tRHZ
tRHZ
tRHOH
tREA
tCEA
tRHOH
tCEA
I/O
tRR
RY / BY
: VIH or VIL
Status Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
CE
tWP
tCH
WE
tCEA
tCHZ
tWHC
tWHR
RE
tDS
tDH
tRHOH
tIR
tREA
I/O
tRHZ
Status
output
70h*
RY / BY
: VIH or VIL
*: 70h represents the hexadecimal number
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Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
CE
tWC
WE
tALH tALS
tALH tALS
ALE
tR
tRC
tWB
RE
tDS tDH
I/O
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
00h
CA8
to 12
PA0
to 7
PA8
to 15
tDS tDH
PA16
to 18
tCEA
tRR
tREA D
OUT
30h
N
DOUT
N+1
Data out from
Col. Add. N
Col. Add. N
RY / BY
Read Cycle Timing Diagram: When Interrupted by CE
tCLR
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
CE
tCSD
tWC
WE
tALH
tALS
tALH
tALS
ALE
tR
tWB
RE
tDS tDH
I/O
tRC
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 12
PA0
to 7
PA8
to 15
Col. Add. N
PA16
to 18
tDS tDH
30h
tRR
tCEA
tREA D
OUT
N
tCHZ
tRHZ
tRHOH
DOUT
N+1
Col. Add. N
RY / BY
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TH58NVG5S0FTA20
Read Cycle with Data Cache Timing Diagram (1/2)
tCLR
CLE
tCLS
tCS
tCLH
tCLS
tCH
tCLH
tCLS
tCH
tCS
tCLR
tCLH
tCLS
tCH
tCS
tCLH
tCH
tCS
CE
tWC
WE
tALH tALS
tRW
tALH tALS
tCEA
tCEA
ALE
tR
tWB
RE
tDS tDH
I/O
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 12
Column address
N*
PA0
to 7
PA8
to 15
PA16
to 18
tDCBSYR1
tRC
tDCBSYR1
tWB
tDS tDH
tDS tDH
30h
31h
Page address
M
tWB
tRR
tDS tDH
tREA
DOUT
0
DOUT
1
31h
DOUT
Col. Add. 0
* The column address will be reset to 0 by the 31h command input.
tREA
DOUT
0
Page address
M+1
Page address M
RY / BY
tRR
Col. Add. 0
1
Continues to 1
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TH58NVG5S0FTA20
Read Cycle with Data Cache Timing Diagram (2/2)
tCLR
CLE
tCLS
tCS
tCLR
tCLH
tCLS
tCH
tCS
tCLR
tCLH
tCLS
tCH
tCS
tCLH
tCH
CE
WE
tCEA
tCEA
tCEA
ALE
tDCBSYR1
tDCBSYR1
tRC
tWB
RE
tDS tDH
I/O DOUT
tRC
tDCBSYR1
tWB
tRR
31h
tDS tDH
tREA
DOUT
0
DOUT
1
DOUT
tRC
tWB
tRR
DOUT
0
31h
tDS tDH
tREA
DOUT
1
Page address
M+2
Page address M + 1
RY / BY
Col. Add. 0
Col. Add. 0
1
DOUT
3Fh
tRR
tREA
DOUT
0
DOUT
1
DOUT
Page address M + x
Col. Add. 0
Make sure to terminate the operation with 3Fh command.
Continues from 1
of last page
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TH58NVG5S0FTA20
Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
CLE
tCLS tCLH
tCS
tCLS tCLH
tCH
tCH
tCS
CE
tWC
tCEA
WE
tALH tALS
tALH
tALS
ALE
tRC
tR
tWB
RE
I/O
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
00h
CA0
to 7
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
30h
Page address
P
tRR
tREA
DOUT DOUT
A
A+1
DOUT
A+N
Page address
P
RY / BY
Column address
A
1
Continues from 1
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TH58NVG5S0FTA20
Column Address Change in Read Cycle Timing Diagram (2/2)
tCLR
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
CE
tRHW
tWC
tCEA
WE
tALH tALS
tALH
tALS
ALE
tWHR
tRC
RE
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tREA
tIR
DOUT
A+N
I/O
05h
CA0
to 7
CA8
to 12
Column address
B
E0h
DOUT
B
DOUT
B+1
DOUT
B + N’
Page address
P
RY / BY
Column address
B
1
Continues from 1
of last page
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Data Output Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
CE
WE
tALH
ALE
tRC
tRP
tCHZ
tREH
tRP
tRP
tRHZ
RE
tREA
tCEA
tREA
I/O
Dout
tRR
tREA
tDS tDH
tRLOH
tRLOH
Command
Dout
tRHOH
tRHOH
RY / BY
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Auto-Program Operation Timing Diagram
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tALS
tPROG
tWB
tALS
ALE
RE
I/O
tDS
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDH
tDH
CA8
to 12
PA0
to 7
PA8 PA16
to 15 to 18
DINN
DIN
N+1
DINM
10h
70h
Status
output
Column address
N
RY / BY
: Do not input data while data is being output.
: VIH or VIL
*) M: up to 4327 (byte input data for ×8 device).
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Auto-Program Operation with Data Cache Timing Diagram (1/3)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tDCBSYW2
tWB
tALS
tALS
ALE
RE
I/O
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDS
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
DINN
tDH
DIN
N+1
15h
80h
CA0
to 7
DIN4327
RY / BY
: Do not input data while data is being output.
: VIH or VIL
1
CA0 to CA12 is 0 in this diagram.
Continues to
18
1
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TH58NVG5S0FTA20
Auto-Program Operation with Data Cache Timing Diagram (2/3)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tALS
tDCBSYW2
tWB
tALS
ALE
RE
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
I/O
tDS
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
DINN
tDH
DIN
N+1
15h
80h
CA0
to 7
DIN4327
RY / BY
Repeat a max of 62 times (in order to program pages 1 to 62 of a block).
1
Continued from
1
2
of last page
: Do not input data while data is being output.
: VIH or VIL
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Auto-Program Operation with Data Cache Timing Diagram (3/3)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tPROG (*1)
tWB
tALS
tALS
ALE
RE
tDS tDH
80h
CA0
to 7
I/O
tDS
tDS
tDS tDH
tDH
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
DINN
DIN
N+1
10h
70h
Status
DIN4327
RY / BY
: Do not input data while data is being output.
: VIH or VIL
2
Continued from
2
of last page
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page − A
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
(Note)
Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by
issuing Status Read command (70h) and make sure the previous page program operation is
completed. If the page program operation is completed issue FFh reset before next operation.
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TH58NVG5S0FTA20
Multi-Page Program Operation with Data Cache Timing Diagram (1/4)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tALS
tDCBSYW1
tWB
tALS
ALE
RE
tDS tDH
I/O
80h
tDS
tDS tDH
CA0
to 7
tDS
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
DINN
tDH
DIN
N+1
Page Address M
District-0
RY / BY
11h
81h
CA0
to 7
DIN4327
: Do not input data while data is being output.
: VIH or VIL
1
Continues to
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TH58NVG5S0FTA20
Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tDCBSYW2
tWB
tALS
tALS
ALE
RE
tDS
tDS tDH
tDS tDH
81h
CA0
to 7
I/O
tDS
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
DINN
tDH
DIN
N+1
Page Address M
District-1
15h
80h
CA0
to 7
DIN4327
RY / BY
Repeat a max of 63 times (in order to program pages 0 to 62 of a block).
1
Continued from
1
2
of last page
: Do not input data while data is being output.
: VIH or VIL
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Multi-Page Program Operation with Data Cache Timing Diagram (3/4)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tALS
tDCBSYW1
tWB
tALS
ALE
RE
I/O
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDS
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 18
DINN
tDH
DIN
N+1
Page Address M+n
District-0
RY / BY
11h
81h
CA0
to 7
DIN4327
: Do not input data while data is being output.
: VIH or VIL
3
2
Continues to
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Multi-Page Program Operation with Data Cache Timing Diagram (4/4)
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tALS
tPROG (*1)
tWB
tALS
ALE
RE
tDS tDH
81h
CA0
to 7
I/O
tDS
tDS
tDS tDH
tDH
tDH
CA8
PA0
PA8 PA16
to 12
to 7
to 15 to 18
Page Address M+n
District-1
RY / BY
DINN
DIN
N+1
10h
71h
DIN4327
: Do not input data while data is being output.
: VIH or VIL
3
Continued from
3
of last page
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page − A
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
(Note)
Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status
Read command (70h) and make sure the previous page program operation is completed. If the page program
operation is completed issue FFh reset before next operation.
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Status
TOSHIBA CONFIDENTIAL
TH58NVG5S0FTA20
Auto Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
CE
WE
tALH
tALS
tWB
tBERASE
ALE
RE
tDS tDH
I/O
RY / BY
60h
Auto Block
Erase Setup
command
: VIH or VIL
PA0
to 7
PA8
to 15
PA16
to 18
D0h
Erase Start
command
Status
output
70h
Busy
Status Read
command
: Do not input data while data is being output.
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Multi Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
CE
WE
tALH
tALS
tWB
tBERASE
ALE
RE
tDS tDH
I/O1
to
60h
PA0
to 7
PA8
to 15
PA16
to 18
D0h
71h
Status
output
RY/BY
Auto Block
Erase Setup
command
Busy
Status Read
command
Repeat 2 times (District-0,1)
: VIH or VIL
: Do not input data while data is being output.
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27
R/B
I/Ox
RE
ALE
WE
CE
CLE
00h
tWC
Column Address
Row Address
Col
Col Row Row Row
35h
Add1 Add2 Add1 Add2 Add3
tWB
Copy Back Program with Random Data Input
85h
Column Address
Row Address
Col
Col Row Row Row
Add1 Add2 Add1 Add2 Add3
Copy Back Program Data
Input Command
Busy
tR
Data1
DataN
10h
tWB
70h
tWHR
I/O
I/O1=0 Successful Program
I/O1=1 Error in Program
Busy
Read Status command
tPROG
TOSHIBA CONFIDENTIAL
TH58NVG5S0FTA20
2010-12-13C
TOSHIBA CONFIDENTIAL
TH58NVG5S0FTA20
ID Read Operation Timing Diagram
tCLS
CLE
tCLS
tCS
tCS
tCH
tCEA
CE
tCH
WE
tALH
tALH
tALS
tAR
ALE
RE
tDH
tDS
I/O
tREA
tREA
tREA
90h
00h
98h
D5h
ID Read
command
Address
00
Maker code
Device code
tREA
See
Table 5
tREA
See
Table 5
See
Table 5
: VIH or VIL
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PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE (n)
Since the device contains two 8Gbit chips, control for each chip by using CE 1 and CE 2. The chip not to be
selected is disabled while CE is High.
CE (n) signal is used to select the chip, and the chip goes into a low-power Standby mode when CE goes High
during the chip is in Ready state. The CE signal is ignored when device is in Busy state ( RY / BY = L), such
as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes
High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY (n)
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
The device has RY / BY 1 and RY / BY 2 signal. RY / BY 1 indicates operating condition of the chip which
has CE 1, and RY / BY 2 indicates operating condition of the chip which has CE 2.
Power on Select: PSL
The PSL signal is used to select whether the device initialization should take place during the device power
on or during the first Reset. Please refer to the application note (2) for details.
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Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
[8Gbit ( Chip A,B)]
[8Gbit ( Chip C,D)]
I/O1
Data Cache
4096
232
Page Buffer
4096
232
I/O1
I/O8
Data Cache
4096
232
Page Buffer
4096
232
I/O8
64 Pages=1 block
524288
pages
8192
blocks
64 Pages=1 block
524288
pages
8192
blocks
8I/O
8I/O
4328
4328
A page consists of 4328 bytes in which 4096 bytes are used for main memory storage and 232 bytes are
for redundancy or for other uses.
1 page = 4328 bytes
1 block = 4328 bytes × 64 pages = (256K + 14.5K) bytes
Capacity = 4328 bytes × 64pages × 16384 blocks
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
L
L
L
CA12
CA11
CA10
CA9
CA8
Third cycle
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth cycle
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
L
L
L
L
L
PA18
PA17
PA16
First cycle
Second cycle
Fifth cycle
30
CA0 to CA12: Column address
PA0 to PA18: Page address
PA6 to PA18: Block address
PA0 to PA5: NAND address in block
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TOSHIBA CONFIDENTIAL
TH58NVG5S0FTA20
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE , WP and PSL signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
Command Input
H
L
Data Input
L
Address input
*1
*3
RE
WP
L
H
*
0V/VCC/NU
L
L
H
H
0V/VCC/NU
L
H
L
H
*
0V/VCC/NU
Serial Data Output
L
L
L
H
*
0V/VCC/NU
During Program (Busy)
*
*
*
*
*
H
0V/VCC/NU
During Erase (Busy)
*
*
*
*
*
H
0V/VCC/NU
*
*
H
*
*
*
0V/VCC/NU
*
*
L
H (*2)
H (*2)
*
0V/VCC/NU
Program, Erase Inhibit
*
*
*
*
*
L
0V/VCC/NU
Standby
*
*
H
*
*
0 V/VCC
0V/VCC/NU
During Read (Busy)
WE
PSL
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
*3: PSL must be tied to either 0V or VCC or left unconnected(NU).
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Table 3. Command table (HEX)
First Set
Second Set
Serial Data Input
80
⎯
Read
00
30
Column Address Change in Serial Data Output
05
E0
Read with Data Cache
31
⎯
Read Start for Last Page in Read Cycle with Data Cache
3F
⎯
Auto Page Program
80
10
Column Address Change in Serial Data Input
85
⎯
Auto Program with Data Cache
80
15
80
11
81
15
81
10
Read for Page Copy (2) with Data Out
00
3A
Read for Copy-Back without Data Out
00
35
Copy-Back Program without Data Out
85
10
Auto Program with Data Cache during Page Copy (2)
8C
15
Auto Program for last page during Page Copy (2)
8C
10
Auto Block Erase
60
D0
Page Program with 2KB Data
80 – 11
80 - 10
Copy-Back Program with 2KB Data
85 - 11
85 - 10
ID Read
90
⎯
Status Read
70
⎯
{
Status Read2 for Chip A or C
F1
⎯
{
Status Read2 for Chip B or D
F2
⎯
{
Status Read for Multi-Page Program or Multi Block Erase
71
⎯
{
Reset
FF
⎯
{
Multi Page Program
Acceptable while Busy
HEX data bit assignment
(Example)
Serial Data Input: 80h
1
0
0
0
0
0
0
8
7
6
5
4
3
2 I/O1
0
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8
Power
Output select
L
L
L
H
L
Data output
Active
Output Deselect
L
L
L
H
H
High impedance
Active
H: VIH, L: VIL
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DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. After initial power on sequence, “00h”
command is latched into the internal command register. Therefore read operation after power on sequence is
excuted by the setting of only five address cycles and “30h” command. Refer to the figures below for the
sequence and the block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
RY / BY
Column Address M
Busy
Page Address N
00h
I/O
tR
30h
Data Cache
m
Page Buffer
Select page
N
M+2
Page Address N
Start-address input
M
M+1
M
Cell array
I/O1 to 8: m = 4327
A data transfer operation from the cell array to the Data
Cache via Page Buffer starts on the rising edge of WE in the
30h command input cycle (after the address information has
been latched). The device will be in the Busy state during this
transfer period.
After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
Random Column Address Change in Read Cycle
CLE
CE
WE
ALE
RE
RY / BY
Busy
tR
Col. M
I/O
30h
00h
Col. M
Page N
M+1 M+2 M+3
Page N
Start from Col. M
Start-address input
M
M
E0h
05h
Col. M’
M’ M’+1 M’+2 M’+3 M’+4
Page N
Start from Col. M’
During the serial data output from the Data Cache, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
M’
Select page
N
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TH58NVG5S0FTA20
Read Operation with Read Cache
The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be
started from the beginning.
CLE
CE
WE
ALE
RE
RY / BY
tR
I/O
00h
30h
Col. M
Data Cache
Page Buffer
1
tDCBSYR1
31h
Page N
2
0
Column 0
1
tDCBSYR1
3
2
31h
4327
3
4
1
2
Page N
Page N
1
3
4327
3Fh
0
1
7
2
3
4327
Page Address N + 2
Page N + 2
Page N + 1
Page N
1
2
6
Page Address N + 1
Page Address N
Page N + 1
3
4
Cell Array
0
tDCBSYR1
5
Page N + 2
5
7
6
Page N + 1
3
Page N + 2
5
3Fh & RE clock
31h & RE clock
30h
31h & RE clock
If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tR (Data transfer from memory
cell to data register) will be reduced.
1
Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tR max.
2
After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time
period can be detected by Ready/Busy signal.
3
Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously.
4
The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max..
This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
5
Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by /RE clock simultaneously
6
The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for
tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
7
Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately
after the completion of serial data out.
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Multi Page Read Operation
The device has a Multi Page Read operation and Multi Page Read with Data Cache operation..
(1) Multi Page Read without Data Cache
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
(3 cycle)
60
Address input
(3 cycle)
60
Address input
Page Address
PA0 to PA18
(District 1)
Page Address
PA0 to PA18
(District 0)
tR
RY/BY
A
Command
input
(5 cycle)
00
Address input
Address input
E0
Column Address
CA0 to CA12
(District 0)
Data output
B
(District 0)
B
A
B
Command
input
(5 cycle)
00
Address input
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(District 1)
RY/BY
A
(2 cycle)
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(District 0)
RY/BY
A
30
Address input
E0
Column Address
CA0 to CA12
(District 1)
Data output
(District 1)
B
District 0
District 1
Reading
Selected
page
Selected
page
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously
with the RE clock from the start address designated in the address input cycle.
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(2) Multi Page Read with Data Cache
When the block address changes (increments) this sequenced has to be started from the beginning.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
60
Address input
Address input
60
Page Address
PA0 to PA18
(Page n0 ; District 1)
Page Address
PA0 to PA18
(Page m0 ; District 0)
A
30
tR
RY/BY
A
Command
input
A
RY/BY
A
31
Address input
00
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page m0 ; District 0)
tDCBSYR1
Address input
E0
Column Address
CA0 to CA12
(District 0)
Data output
B
(District 0)
B
Command
input
B
Address input
00
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page n0 ; District 1)
RY/BY
Address input
Data output
C
C
C
Return to A
Repeat a max of 63 times
3F
Address input
00
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page m63 ; District 0)
tDCBSYR1
Address input
E0
Column Address
CA0 to CA12
(District 0)
Data output
D
00
Address input
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page n63 ; District 1)
RY/BY
D
(District 0)
Command
input
D
C
(District 1)
B
Command
input
RY/BY
E0
Column Address
CA0 to CA12
(District 1)
Address input
Column Address
CA0 to CA12
(District 1)
E0
Data output
(District 1)
D
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(3) Notes
(a) Internal addressing in relation with the Districts
•
•
•
•
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
The device contains four chips of NAND EEPROM.
Each internal chip consists from 2 Districts.
Each District consists from 2048 erase blocks.
The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 4094
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 4095
(c) District 0: Block 4096, Block 4098, Block 4100, Block 4102,···, Block 8190
(d) District 1: Block 4097, Block 4099, Block 4101, Block 4103,···, Block 8191
Combination of (a) and (b) or (c) and (d) can only be selected.
(b) Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
District0 and District1 should be selected within the same chip.
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c) WP signal
Make sure WP is held to High level when Multi Page Read operation is performed
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Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
CLE
CE
WE
ALE
RE
RY/BY
Din Din Din
80h
I/O
Col. M
Page P
Din
70h
10h
Status
Out
Data
Data input
Program
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of WE
following input of the “10h” command. After programming, the
programmed data is transferred back to the Page Buffer to be
automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
Read& verification
Selected
page
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page Program
operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input. After
the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h
Din
Col. M
Din
Din
Din
85h
Din
Col. M’
Page N
Col. M
Din
Din
Din
10h
70h
Status
Busy
Col. M’
Data input
Program
Reading & verification
Selected
page
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Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto
Page Program. The sequence of command, address and data input is shown bellow. (Refer to the detailed timing
chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program
operation completes. Status bit of I/O 1 is set to “1” when any of the pages fails. Limitation in addressing with
Multi Page Program is shown below.
Multi Page Program
tPROG
tDCBSYW1
R/ B
I/O0~7
”0”
80h
Address & Data Input
CA0~CA12
PA0~PA5
PA6
PA7~PA18
11h
81h
Note
: Valid
: Valid’
: District0’
: Valid’
Address & Data Input
CA0~CA12
PA0~PA5
PA6
PA7~PA18
10h
: Valid
: Valid
: District1
: Valid
70h
I/O1
Pass
”1”
Fail
NOTE: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
80h
11h
81h
10h
Data
Input
Plane 0
(2048 Block)
Plane 1
(2048 Block)
Block 0
Block 1
Block 2
Block 3
Block 4092
Block 4093
Block 4094
Block 4095
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Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
sequenced has to be started from the beginning.
CLE
CE
WE
ALE
RE
RY / BY
tDCBSYW2
I/O
80h
Add Add Add Add Add
Din Din
Page N
Data for Page N
Data Cache
Page Buffer
Cell Array
1
Din
1
15h
70h
Add Add Add Add Add
80h
2
Data for Page N
Din Din
Page N + 1
Status Output
2
tPROG (NOTE)
tDCBSYW2
3
Din
15h
3
70h
4
80h
4
Page N + P
Status Output
5
Data for Page N + 1
Add Add Add Add Add
Din Din
Din
5
10h
70h
6
Status Output
Data for Page N + P
Data for Page N + 1
3
Page N
5
6
Page N + 1
Page N + P − 1
Page N + P
Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache
1
Data for Page N is input to Data Cache.
2
Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (tDCBSYW2).
3
Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.
4
By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 15h command
until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N + 1 (tDCBSYW2).
5
Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.
6
The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page N + P is completed.
NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following;
tPROG = tPROG for the last page + tPROG of the previous page − ( command input cycle + address input cycle + data input cycle time of the previous page)
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Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation.
z
I/O1 : Pass/fail of the current page program operation.
z
I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
z
Status on I/O1: Page Buffer Ready/Busy is Ready State.
The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 10h command
z
Status on I/O2: Data Cache Read/Busy is Ready State.
The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 15h command.
Example)
I/O2
I/O1
80h…15h
=>
=>
Invalid
Invalid
70h
Status
Out
Page 1
Page 1
Invalid
80h…15h
70h
Status
Out
Page N − 2
Invalid
Page 1
Page 2
70h
Status
Out
80h…15h
70h
Status
Out
Page N − 1
Page 2
Page N − 1
Page N
invalid
invalid
80h…10h
70h
Status
Out
70h
Status
Out
Page N
RY/BY pin
Data Cache Busy
Page Buffer Busy
Page 1
Page 2
Page N − 1
Page N
If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during
this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2
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Multi Page Program with Data Cache
The device has a Multi Page Program with Data Cache operation, which enables even higher speed program
operation compared to Auto Page Program with Data Cache as shown below. When the block address changes
(increments) this sequenced has to be started from the beginning.
The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
Data input
command
Dummy
for
multi-page
Program
program
command
Data input
command
80
11
Address Data input
0 to 4327
input
(District 0)
Program with
Data Cache
command
81
15
Address Data input
0 to 4327
input
(District 1)
Data input
command
80
Dummy
Program
command
11
Address Data input
0 to 4327
input
(District 0)
Data input
command
for multi-page
program
Auto Page
Program
command
81
10
Address Data input
0 to 4327
input
(District1)
RY/BY
After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details
of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”.
District 0
Program
District 1
Reading & verification
Selected
page
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of
/WE following input of the “15h” or “10h” command. After programming, the programmed data is
transferred back to the register to be automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
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Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation
total 64 times with incrementing the page address in the blocks, and then input the last page data of the
blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command
sequence.
In this full sequence, the command sequence is following.
80
11
81
15
80
11
81
15
63th
80
11
81
15
64th
80
11
81
10
1st
After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read
command.
10 or15
71
Pass
I/O
Status Read
command
Fail
RY/BY
The 71h command Status description is as below.
STATUS
OUTPUT
I/O1
Chip Status1 : Pass/Fail
Pass: 0
Fail: 1
I/O2
District 0 Chip Status1 : Pass/Fail
Pass: 0
Fail: 1
I/O3
District 1 Chip Status1 : Pass/Fail
Pass: 0
Fail: 1
I/O4
District 0 Chip Status2 : Pass/Fail
Pass: 0
Fail: 1
I/O5
District 1 Chip Status2 : Pass/Fail
Pass: 0
Fail: 1
I/O6
Ready/Busy
Ready: 1
Busy: 0
I/O7
Data Cache Ready/Busy
Ready: 1
Busy: 0
I/O8
Write Protect
Protect: 0
I/O1 describes Pass/Fail condition of
district 0 and 1(OR data of I/O2 and I/O3).
If one of the districts fails during multi
page program operation, it shows “Fail”.
I/O2 to 5 shows the Pass/Fail condition of
each district. For details on “Chip Status1”
and “Chip Status2”, refer to section
“Status Read”.
Not Protect: 1
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Internal addressing in relation with the Districts
To use Multi Page Program operation, the internal addressing should be considered in relation with the
District.
•
The device contains four chips of NAND EEPROM.
•
Each internal chip consists from 2 Districts.
•
Each District consists from 2048 erase blocks.
•
The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 4094
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 4095
(c) District 0: Block 4096, Block 4098, Block 4100, Block 4102,···, Block 8190
(d) District 1: Block 4097, Block 4099, Block 4101, Block 4103,···, Block 8191
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Page Program with Data Cache operation
There are following restrictions in using Multi Page Program with Data Cache;
(Restriction)
District0 and District1 should be selected within the same chip.
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (15 or 10)
(80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (15 or 10)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(80) [District 0] (11) (81) [District 1] (15 or 10)
(80) [District 1] (11) (81) [District 0] (15 or 10)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Program with Data Cache operation
(Restriction)
The operation has to be terminated with “10h” command.
Once the operation is started, no commands other than the commands shown in the timing diagram is allowed
to be input except for Status Read command and reset command.
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Page Copy (2)
By using Page Copy (2), data in a page can be copied to another page after the data has been read out.
When the block address changes (increments) this sequenced has to be started from the beginning.
Command
input
00
2
Address input
30
Address
CA0 to CA12, PA0 to PA18
(Page N)
RY/BY
Data output
3
8C
Col = 0 start
1
Address input
Data input
Address
CA0 to CA12, PA0 to PA18
(Page M)
15
00
When changing data,
changed data is input.
4
Data for Page N
3A
Address
CA0 to CA12, PA0 to PA18
(Page N+P1)
tDCBSYW2
tR
1
Address input
2
Data for Page N
3
Data for Page M
Data output
Col = 0 start
5
tDCBSYR2
4
5
A
A
Data for Page N + P1
Data Cache
Page Buffer
Cell Array
Page M
Page N + P1
Page N
Page Copy (2) operation is as following.
1 Data for Page N is transferred to the Data Cache.
2 Data for Page N is read out.
3 Copy Page address M is input and if the data needs to be changed, changed data is input.
4 Data Cache for Page M is transferred to the Page Buffer.
5 After the Ready state, Data for Page N + P1 is output from the Data Cache while the data of Page M is being programmed.
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Command
input
A
6
Address input
8C
Address
CA0 to CA12, PA0 to PA18
(Page M+R1)
RY / BY
TH58NVG5S0FTA20
Data input
15
Address input
00
When changing data,
changed data is input.
7
3A
Address
CA0 to CA12, PA0 to PA18
(Page N+P2)
Data output
00
Address input
8
Data output
3A
Address
CA0 to CA12, PA0 to PA18
(Page N+Pn)
Col = 0 start
B
Col = 0 start
9
A
B
tDCBSYW2
6
Data for Page M + R1
7
Data for Page M + R1
tDCBSYR2
8
tDCBSYR2
9
Data for Page N + P2
Data for Page N + Pn
Data Cache
Page Buffer
Cell Array
Page M + Rn − 1
Page M + R1
Page M + Rn − 1
Page M
Page N + Pn
Page N + P1
6
7
8
9
Page N + P2
Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.
By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.
The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.
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Command
input
B
10
Address input
8C
Data input
Address
CA0 to CA12, PA0 to PA18
(Page M+Rn)
RY / BY
TH58NVG5S0FTA20
10
70
Status output
11
B
tPROG (*1)
10
Data Cache
Page Buffer
Data for Page M + Rn
11
Data for Page M + Rn
Page N + Pn
Page M + Rn − 1
Cell Array
10
11
Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following,
tPROG = tPROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle time of the last page)
NOTE) This operation needs to be executed within District-0 or District-1.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
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Multi Page Copy (2)
By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out.
When the each block address changes (increments) this sequenced has to be started from the beginning.
Same page address (PA0 to PA5) within two districts has to be selected.
Command
input
Address input
60
Address input
60
30
RY/BY
00
Address input
05
A
Data output
Address
CA0 to CA12
(Col = 0)
Address input
E0
Data output
Address input
8C
Data input
B
tDCBSYW1
8C
Address input
Data input
15
60
Address
CA0 to CA12, PA0 to PA18
(Page N0 ; District 1)
Address input
60
Address
PA0 to PA18
(Page m1 ; District 0)
B
C
B
11
Address
CA0 to CA12, PA0 to PA18
(Page M0 ; District 0)
A
B
Address input
00
Address input
05
Address input
E0
C
3A
Address
PA0 to PA18
(Page n1 ; District 1)
C
tDCBSYR2
tDCBSYW2
Address
CA0 to CA12, PA0 to PA18
(Page m1)
RY/BY
E0
A
Address
CA0 to CA12
(Col = 0)
Address
CA0 to CA12, PA0 to PA18
(Page n0)
RY/BY
Address input
tR
A
RY/BY
05
Address
CA0 to CA12, PA0 to PA18
(Page m0)
Address
PA0 to PA18
(Page n0 ; District 1)
Address
PA0 to PA18
(Page m0 ; District 0)
Address input
00
Data output
00
Address
CA0 to CA12
(Col = 0)
Address input
Address
CA0 to CA12, PA0 to PA18
(Page n1)
C
48
05
Address input
Address
CA0 to CA12
(Col = 0)
E0
Data output
D
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D
8C
Address input
Data input
11
8C
Address
CA0 to CA12, PA0 to PA18
(Page M1 ; District 0)
RY/BY
Address input
Address input
60
3A
F
Address input
00
Address
PA0 to PA18
(Page n63 ; District 1)
E0
Data output
00
Address input
05
Address input
E0
Data output
8C
Address
CA0 to CA12
(Col = 0)
Address
CA0 to CA12
(Col = 0)
Address input
Data input
G
11
Address
CA0 to CA12, PA0 to PA18
(Page M63 ; District 0)
F
tDCBSYW1
8C
Address input
Data input
F
F
G
10
Note)
This operation needs to be executed within each District.
Address
CA0 to CA12, PA0 to PA18
(Page N63 ; District 1)
RY/BY
Address input
tDCBSYR2
Address
CA0 to CA12, PA0 to PA18
(Page n63)
G
05
Address
CA0 to CA12, PA0 to PA18
(Page m63)
E
E
tDCBSYW2
tDCBSYW1
60
E
15
Address
CA0 to CA12, PA0 to PA18
(Page N1 ; District 1)
Address
PA0 to PA18
(Page m63 ; District 0)
RY/BY
Data input
D
E
RY/BY
Address input
TH58NVG5S0FTA20
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after
the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
G
tPROG (*1)
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG* during cache programming is given by the following equation.
Make sure WP is held to High level when Multi Page Copy (2) operation is performed.
Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence
tPROG = tPROG of the last page + tPROG of the previous page-A
A = (command input cycle + address input cycle + data output/input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
60
D0
Block Address
input: 3 cycles
70
I/O
Status Read
command
Erase Start
command
RY / BY
Pass
Fail
Busy
Multi Block Erase
The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by
checking the status by 71h status read command. For details on 71h status read command, refer to section
“Multi Page Program with Data Cache”.
60
Block Address
input: 3 cycles
District 0
60
D0
71
Status Read
command
Block Address Erase Start
input: 3 cycles command
District 1
RY / BY
I/O
Pass
Fail
Busy
Internal addressing in relation with the Districts
•
•
•
•
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
The device contains four chips of NAND EEPROM.
Each internal chip consists from 2 Districts.
Each District consists from 2048 erase blocks.
The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 4094
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 4095
(c) District 0: Block 4096, Block 4098, Block 4100, Block 4102,···, Block 8190
(d) District 1: Block 4097, Block 4099, Block 4101, Block 4103,···, Block 8191
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase
(Restriction)
District0 and District1 should be selected within the same chip.
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.
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READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE
Copy-Back operation is a sequence execution of Read for Copy-Back and of copy-back program with the
destination page address. A read operation with “35h” command and the address of source page moves the
whole 4328byte data into the internal data buffer. Bit errors are checked by sequential reading the data. In the
case where there is no bit error, the data don’t need to be reloaded. Therefore Copy-Back program operation is
initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Acutual programming
operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read
Status Register command (70h) may be enterd to read the status register. The system contoller can detect the
completion of a program cycle by monitoring the RY / BY output, or the Status Bit (I/O7) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit (I/O1) may be checked. The command register
remains in Read Status command mode until another valid command is written to the command register.
During copy-Back program, data modification is possible using randam data input command (85h) as shown
below.
Page Copy-Back Program Operation
tPROG
tR
R/ B
I/Ox
”0”
00h
Add.(5Cycles)
35h
Data Output
Col. Add.1,2 & Page Add.1,2,3
Source Address
85h
Add.(5Cycles)
10h
70h
Col. Add.1,2 & Page Add.1,2,3
Destination Address
I/O1
Pass
”1”
Fail
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
Page Copy-Back Program Operation with Random Data Input
tR
tPROG
R/ B
I/Ox
00h Add.(5Cycles)
35h
Col. Add.1,2 & Page Add.1,2,3
Source Address
Data Output
85h Add.(5Cycles)
Data
Col. Add.1,2 & Page Add.1,2,3
Destination Address
85h Add.(2Cycles)
Data
10h
70h
Col. Add.1,2
There is no limitation for the number of repetition
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Two-Plane Copy-Back Program Operation
Multi Page Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4328byte data
registers. Since the device is equipped with two memory planes, activating the two sets of 4328 byte data
registers enable a simultaneous programming of two pages. Same page address (PA0 to PA5) within two
districts has to be selected.
tR
R/ B
I/Ox
60h
Address(3Cycle)
60h
Address(3Cycle)
35h
Row Add.1,2,3
Row Add.1,2,3
PA0~PA5 : Valid
PA6
: Fixed ‘Low’
PA7~PA18 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘High’
PA7~PA18 : Valid
1
R/ B
I/Ox
00h
1
Address(5Cycle)
05h
Col. Add.1,2 & Row Add.1,2,3
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Address(2Cycle)
Data Output
Col. Add.1,2
CA0~CA12
: Valid
: Valid
: Fixed ‘Low’
: Valid
E0h
2
: Valid
R/ B
I/Ox
00h
2
Address(5Cycle)
05h
Col. Add.1,2 & Row Add.1,2,3
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Fixed ‘High’
: Valid
Address(2Cycle)
E0h
Data Output
Col. Add.1,2
CA0~CA12
3
: Valid
tDCBSYW1
tPROG
R/ B
I/Ox
85h
3
Add.(5Cycles)
11h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
81h
*2
Note
Add.(5Cycles)
10h
70h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
: Valid
: Valid
: Fixed ‘Low’
: Valid
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Plane0
: Valid
: Valid
: Fixed ‘High’
: Valid
Plane1
Source page
Source page
Target page
Target page
(1) : Multi Page Read for Copy Back
(2) : Multi Page Random Data Out
(1)
(2)
(3)
Data field
(1)
Spare field
(2)
(3)
Data field
(3) : Multi Page Copy-Back Program
Spare field
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
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Two-Plane Copy-Back Program Operation with Random Data Input
tR
R/ B
I/Ox
60h
Address(3Cycle)
60h
Address(3Cycle)
35h
Page Add.1,2,3
Page Add.1,2,3
PA0~PA5 : Valid
PA6
: Fixed ‘Low’
PA7~PA18 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘High’
PA7~PA18 : Valid
1
R/ B
I/Ox
00h
1
Address(5Cycle)
05h
Col. Add.1,2 & Page Add.1,2,3
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Fixed ‘Low’
: Valid
Address(2Cycle)
E0h
Data Output
Col. Add.1,2
CA0~CA12
2
: Valid
R/ B
I/Ox
00h
2
Address(5Cycle)
05h
Col. Add.1,2 & Page Add.1,2,3
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Fixed ‘High’
: Valid
Address(2Cycle)
E0h
Data Output
Col. Add.1,2
CA0~CA12
3
: Valid
tDBSY
R/ B
I/Ox
85h
3
Add.(5Cycles)
Data
85h
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Add.(2Cycles)
Data
11h
*2
Note
Col. Add.1,2
Col. Add.1,2 & Page Add.1,2,3
Destination Address
4
: Valid
: Valid
: Fixed ‘Low’
: Valid
tPROG
R/ B
I/Ox
81h
4
Add.(5Cycles)
Data
85h
Data
10h
Col. Add.1,2
Col. Add.1,2 & Page Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Add.(2Cycles)
: Valid
: Valid
: Fixed ‘High’
: Valid
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
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2KB Program Operation Timing Guide
The device is designed also to support the program operation with 2KByte data to offer the backward
compatibility to the controller which uses the NAND Flash with 2KByte page. The sequence of command,
address and data input is shown below.
(2KBx2) Program Operation
tDCBSYW1
tPROG
R/ B
I/O0~7
80h
Address & Data Input
11h
80h
Address & Data Input
10h
70h
Note
Col. Add.1,2 & Row Add.1,2,3
2112 Byte Data
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Col. Add.1,2 & Row Add.1,2,3
2112 Byte Data
: Valid
: Valid
: Valid
: Valid
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Must be same with the previous
: Must be same with the previous
: Must be same with the previous
NOTE: 1. Any command between 11h and 81h is prohibited except 70h/F1h and FFh
(2KBx2) Copy-Back
tR
R/ B
I/Ox
00h
Add.(5Cycles)
35h
Data Output
Col. Add.1,2 & Row Add.1,2,3
Source Address
1
tPROG
tDCBSYW1
R/ B
I/Ox
85h
1
Add.(5Cycles)
Data
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Valid
: Valid
11h
85h
Add.(5Cycles)
Data
10h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Must be same with the previous
: Must be same with the previous
: Must be same with the previous
NOTE: 1. Copy-Back is allowed only within the same memory district.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
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TH58NVG5S0FTA20
(2KBx2) Copy-Back with Random Data Input
tR
R/ B
I/Ox
00h
Add.(5Cycles)
35h
Data Output
Col. Add.1,2 & Row Add.1,2,3
Source Address
1
tDCBSYW1
R/ B
I/Ox
85h
1
Add.(5Cycles)
Data
85h
Data
11h
*2
Note
Col. Add.1,2
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Add.(2Cycles)
2
: Valid
: Valid
: Valid
: Valid
tPROG
R/ B
I/Ox
85h
2
Add.(5Cycles)
Data
85h
Add.(2Cycles)
Data
10h
Col. Add.1,2
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Must be same with the previous
PA6
: Must be same with the previous
PA7~PA18 : Must be same with the previous
NOTE: 1. Copy-Back is allowed only within the same memory district.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
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Multi Page Copy-Back using 4KB Buffer RAM
The deveice consists of 4KB pages and can support Multi Plane program operation. The internal RAM
requirement for a controller is 8KB, but for those controllers which support less than 8KB RAM, the sequence of
command, address and data input is shown below for Multi Plane program operation.
District0
District1
Source page
Source page
(1) : Two-Plane Read for Copy-Back
(2) : Random Data Out On Plane 0(Up to 4328Byte)
(3) : Random Data In On Plane 0(Up to 4328Byte)
Target page
Target page
(4) : Random Data Out On Plane 1(Up to 4328Byte)
(5) : Random Data In On Plane 1(Up to 4328Byte)
(1)
(6)
(1)
(6)
4KByte
(6) : Two-Plane Program for Copy-Back
4KByte
Data field
Spare field
(2)
Data field
(3)
(4)
Spare field
(5)
Multi Page Copy-Back with Random Data Input
tR
R/ B
I/Ox
60h
Add.(3Cycle)
60h
Add.(3Cycle)
35h
Row Add.1,2,3
Row Add.1,2,3
PA0~PA5 : Valid
PA6
: Fixed ‘Low’
PA7~PA18 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘High’
PA7~PA18 : Valid
00h
Add.(5Cycle)
05h
Col. Add.1,2 & Row Add.1,2,3
Add.(2Cycle)
DOUT
Col. Add.1,2 Up to 4328Byte
CA0~CA12
CA0~CA12 : Fixed ‘Low’
PA0~PA5 : Fixed ‘Low’
PA6
: Fixed ‘Low’
PA7~PA18 : Fixed ‘Low’
E0h
: Valid
1
tDCBSYW1
R/ B
I/Ox
85h
1
Add.(5Cycle)
DIN
85h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
Add.(2Cycle)
DIN
11h
00h
Add.(5Cycle)
05h
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2,
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Fixed ‘Low’
: Valid
: Fixed ‘Low’
: Fixed ‘Low’
: Fixed ‘High’
: Fixed ‘Low’
Add.(2Cycle)
E0h
DOUT
Col. Add.1,2 Up to 4328Byte
CA0~CA12
: Valid
2
tPROG
R/ B
I/Ox
81h
2
Add.(5Cycle)
DIN
85h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Add.(2Cycle)
DIN
10h
70h
Col. Add.1,2,
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘High’
PA7~PA18 : Valid
NOTE: 1. Copy-Back is allowed only within the same memory district.
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ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
tCEA
CE
WE
tAR
ALE
RE
I/O
tREA
See
table 5
See
table 5
See
table 5
90h
00h
98h
D5h
ID Read
command
Address 00
Maker code
Device code
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
1
0
0
1
1
0
0
0
98h
Table 5. Code table
1st Data
Maker Code
2nd Data
Device Code
1
1
0
1
0
1
0
1
D5h
3rd Data
Chip Number, Cell Type
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
See table
4th Data
Page Size, Block Size
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
See table
5th Data
Plane Number
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
See table
3rd Data
Description
Internal Chip Number
Cell Type
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
4
8
0
0
1
1
2 level cell
4 level cell
8 level cell
16 level cell
57
I/O2
I/O1
0
0
1
1
0
1
0
1
0
1
0
1
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TH58NVG5S0FTA20
4th Data
Description
Page Size
(without redundant area)
1 KB
2 KB
4 KB
8 KB
Block Size
(without redundant area)
64 KB
126 KB
256 KB
512 KB
I/O8
I/O7
I/O6
I/O5
0
0
1
1
0
1
0
1
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
0
0
1
1
0
1
0
1
I/O2
I/O1
5th Data
Description
Plane Number
I/O8
1 Plane
2 Plane
4 Plane
8 Plane
58
I/O7
I/O4
I/O3
0
0
1
1
0
1
0
1
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TH58NVG5S0FTA20
Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE or CE after a “70h” or “F1h” or “F2h” command input. This two signal
control allows the system to poll the progress of each device in multiple memory connections even when
Ready/Busy pins are common-wired. The Status Read can also be used during a Read operation to find out the
Ready/Busy status.
The resulting information is outlined in Table 6 and Tabel 7.
Table 6. Status output table
Definition
Page Program
Block Erase
Cache Program
Read
Cache Read
Pass/Fail
Pass/Fail
Invalid
Invalid
Pass/Fail
Invalid
I/O1
Chip Status1
Pass: 0
Fail: 1
I/O2
Chip Status 2
Pass: 0
Fail: 1
I/O3
Not Used
0
0
0
I/O4
Not Used
0
0
0
I/O5
Not Used
0
0
0
I/O6
Page Buffer Ready/Busy
Ready: 1
Busy: 0
Ready/Busy
Ready/Busy
Ready/Busy
I/O7
Data Cache Ready/Busy
Ready: 1
Busy: 0
Ready/Busy
Ready/Busy
Ready/Busy
I/O8
Write Protect
Not Protected :1
Write Protect
Write Protect
Write Protect
Protected: 0
The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state.
Chip Status 1:
During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.
During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the
current page program operation, and therefore this bit is only valid when I/O6 shows the Ready state.
Chip Status 2:
This bit shows the pass/fail result of the previous page program operation during Auto Page Programming
with Data Cache. This status is valid when I/O7 shows the Ready State.
The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not
15h or 31h.
Tabel 7 : F1h/F2h Read Status Register Definition
Definition
Page Program
Block Erase
Read
I/O 1
Pass : “0”, Fail : “1”
Pass/Fail
Pass/Fail
Not use
I/O 2
Pass : “0”, Fail : “1”
Plane0 Pass/Fail
Plane0 Pass/Fail
Not use
I/O 3
Pass : “0”, Fail : “1”
Plane1 Pass/Fail
Plane1 Pass/Fail
Not use
I/O 4
Don’t-cared
Not use
Not use
Not use
I/O 5
Don’t-cared
Not use
Not use
Not use
I/O 6
Don’t-cared
Not use
Not use
Not use
I/O 7
Busy : “0”, Ready : “1”
Ready/Busy
Ready/Busy
Ready/Busy
I/O 8
Protected : “0”, Not Protected :
“1”
Write Protect
Write Protect
Write Protect
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An application example with multiple devices is shown in the figure below.
CE1
CLE
ALE
WE
RE
CE2
Device
1
Device
2
CE3
CEN
Device
3
CEN + 1
Device
N
Device
N+1
I/O1
to I/O8
RY / BY
RY / BY
Busy
CLE
ALE
WE
CE1
CEN
RE
70h
I/O
70h
Status on Device 1
Status on Device N
System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also
stop the previous program to a page depending on when the FF reset is input.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
80
10
FF
00
Internal VPP
RY / BY
tRST (max 30 µs)
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When a Reset (FFh) command is input during erasing
D0
FF
00
Internal erase
voltage
RY / BY
tRST (max 500 µs)
When a Reset (FFh) command is input during Read operation
00
30
FF
00
RY / BY
tRST (max 10 µs)
When a Reset (FFh) command is input during Ready
FF
00
RY / BY
tRST (max 10 µs)
When a Status Read command (70h) is input after a Reset
FF
70
I/O status : Pass/Fail → Pass
: Ready/Busy → Ready
RY / BY
When two or more Reset commands are input in succession
10
(1)
(2)
(3)
FF
FF
FF
RY / BY
The second
FF
command is invalid, but the third
61
FF
command is valid.
2010-12-13C
TOSHIBA CONFIDENTIAL
TH58NVG5S0FTA20
APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h/71h/F1h.
The WP signal is useful for protecting against data corruption at power-on/off.
2.7 V
2.5 V
0 V
≥ 1ms
VCC
2.7 V
2.5 V
0.5 V
0.5 V
Don’t
care
Don’t
care
CE , WE , RE
CLE, ALE
Don’t
care
VIH
VIL
WP
VIL
2 ms max
Operation
100 µs max
100 µs max
Don’t
care
Invalid
2 ms max
Invalid
Ready/Busy
(2)
Power-on Reset
The device goes into automatic self-initialization during power on if PSL is tied either to GND or NU.
During the initialization process, the device consumes a maximum current of 30mA (ICCO0). If PSL is tied to
VCC, the device will not complete its self-initialization during power on and will not consume ICCO0, and
completes the initialization process with the first Reset command input after power on. During the first FFh
reset Busy period, the device consumes a maximum current of 30mA (ICCO0). In either case (PSL = GND/NU
or VCC), The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3)
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4)
Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h(71h, F1h,F2h) and FFh.
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(5)
TH58NVG5S0FTA20
Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Multi Page Program
command “11h”, Auto Program with Data Cache Command “15h”, or the Reset command “FFh”.
80
FF
WE
Address input
RY / BY
If a command other than “85h” , “10h” , “11h” , “15h” or “FFh” is input, the Program operation is not
performed and the device operation is set to the mode which the input command specifies.
80
XX
Mode specified by the command.
10
Programming cannot be executed.
Command other than
“85h”, “10h”, “11h”, “15h” or “FFh”
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
Data (64)
DATA IN: Data (1)
Data register
Data (64)
Data register
Page 0
Page 1
Page 2
(1)
(2)
(3)
Page 0
Page 1
Page 2
(2)
(32)
(3)
Page 31
(32)
Page 31
(1)
Page 63
(64)
Page 63
(64)
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(7)
TH58NVG5S0FTA20
Status Read during a Read operation
00
Command
00
30
[A]
70
CE
WE
RY/BY
RE
Address N
Status Read
command input
Status output
Status Read
.
The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary
(8)
Auto programming failure
80
10
70
I/O
Fail
80
Address Data
M
input
10
Address Data
N
input
80
If the programming result for page address M is Fail, do not try to program the
page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
command, address and data is necessary.
10
M
N
(9)
RY / BY : termination for the Ready/Busy pin ( RY / BY )
A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.
VCC
VCC
Ready
VCC
R
Device
Busy
RY / BY
tr
tf
CL
VSS
1.5 µs
tr
This data may vary from device to device.
We recommend that you use this data as a
reference when selecting a resistor value.
tf
1.0 µs
1 KΩ
15 ns
10 ns
tr
0.5 µs
0
VCC = 3.3 V
Ta = 25°C
CL = 100 pF
tf
5 ns
2 KΩ
3 KΩ
4 KΩ
R
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(10)
TH58NVG5S0FTA20
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN
80
10
WP
RY / BY
tWW (100 ns MIN)
Disable Programming
WE
DIN
80
10
WP
RY / BY
tWW (100 ns MIN)
Enable Erasing
WE
DIN
60
D0
WP
RY / BY
tWW (100 ns MIN)
Disable Erasing
WE
DIN
60
D0
WP
RY / BY
tWW (100 ns MIN)
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(11)
TH58NVG5S0FTA20
When six address cycles are input
Although the device may read in a sixth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00h
30h
Ignored
Address input
RY / BY
Program operation
CLE
CE
WE
ALE
I/O
80h
Ignored
Address input
66
Data input
2010-12-13C
TOSHIBA CONFIDENTIAL
(12)
TH58NVG5S0FTA20
Several programming cycles on the same page (Partial Page Program)
Each segment can be programmed individually as follows:
1st programming
2nd programming
All 1 s
4th programming
Result
All 1 s
Data Pattern 1
Data Pattern 2
All 1 s
Data Pattern 1
Data Pattern 2
67
All 1 s
Data Pattern 4
Data Pattern 4
2010-12-13C
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(13)
TH58NVG5S0FTA20
Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Bad Block
Bad Block
Please do not perform an erase operation to bad blocks. It may be
impossible to recover the bad block information if the information is
erased.
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the bit lines by select gates.
The number of valid blocks over the device lifetime is as follows:
Valid (Good) Block Number
MIN
TYP.
MAX
UNIT
16064
⎯
16384
Block
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in either the 1st or the 2nd page.
Read Check :
Read either column 0 or 4096 of the 1st page or the
2nd page of each block. If the data of the column is not
FF (Hex), define the block as a bad block.
Start
Block No = 1
Fail
Read Check
Pass
Block No. = Block No. + 1
No
Bad Block *1
Last Block
Yes
End
*1:
No erase operation is allowed to detected bad blocks
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Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
DETECTION AND COUNTERMEASURE SEQUENCE
Block
Erase Failure
Status Read after Erase → Block Replacement
Page
Programming Failure
Status Read after Program → Block Replacement
Single Bit
Programming Failure
“1 to 0”
ECC
•
ECC: Error Correction Code. 4 bit correction per 528Bytes is necessary.
•
Block Replacement
Program
Error occurs
Buffer
memory
Block A
When an error happens in Block A, try to reprogram the
data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses
to Block A ( by creating a bad block table or by using
another appropriate scheme).
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15)
Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
(16)
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two
plane operations.
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Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
4 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
•
Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
•
Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Data
Retention
[Years]
Write/Erase Endurance [Cycles]
•
Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.
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Package Dimensions
Unit: mm
0.25 TYP
18.4 0.1
0.145 0.055
20.0 0.2
0.1
1.0 0.1
0.1 0.05
1.2MAX
0~10
25
12.4MAX
24
12.0 0.1
48
0.5
1
0.22 0.08
0.08 M
TSOP I 48-P-1220-0.50C
0.5 0.1
Weight: 0.53g (typ.)
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Revision History
Date
2009-12-24
2010-06-10
2010-08-02
2010-12-13
Rev.
1.00
1.00
1.00
1.01
Description
Original version
ECC = TBD was changed to 4bit
Chaned from TC58NVG3S
Package was corrected from TSOP I 48-P-1220-0.50 to TSOP I 48-P-1220-0.50C
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
• Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
document.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product
or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
• Product is subject to foreign exchange and foreign trade control laws.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
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