TC58NVG0S3AFT05 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 GBIT (128M × 8 BITS) CMOS NAND EEPROM DESCRIPTION The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND EEPROM) organized as (2048 + 64) bytes × 64 pages × 1024 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NVG0S3A is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES • • • • • • Organization Memory cell array 2112 × 64K × 8 Register 2112 × 8 Page size 2112 bytes Block size (128K + 4K) bytes Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read Mode control Serial input/output Command control • • PIN ASSIGNMENT (TOP VIEW) NC NC NC NC NC GND RY / BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Powersupply VCC = 2.7 V to 3.6 V Program/Erase Cycles 1E5 Cycles (With ECC) Access time Cell array to register 25 µs max Serial Read Cycle 50 ns min Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 50 µA max Package TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.) PIN NAMES 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY / BY Ready/Busy GND Ground Input VCC Power supply VSS Ground 2003-08-20A 1/33 TC58NVG0S3AFT05 BLOCK DIAGRAM VCC VSS Status register Address register I/O1 Column buffer I/O Control circuit to Column decoder I/O8 Command register Data register Row address buffer decoder CE CLE ALE Logic control WE Control circuit RE WP Row address decorder Sense amp Memory cell array RY / BY RY / BY HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VCC Power Supply Voltage −0.6 to 4.6 V VIN Input Voltage −0.6 to 4.6 V VI/O Input /Output Voltage −0.6 V to VCC + 0.3 V (≤ 4.6 V) V PD Power Dissipation 0.3 W TSOLDER Soldering Temperature (10 s) 260 °C TSTG Storage Temperature −55 to 150 °C TOPR Operating Temperature 0 to 70 °C CAPACITANCE *(Ta = 25°C, f = 1 MHz) SYMB0L PARAMETER CONDITION MIN MAX UNIT CIN Input VIN = 0 V 10 pF COUT Output VOUT = 0 V 10 pF * This parameter is periodically sampled and is not tested for every device. 2003-08-20A 2/33 TC58NVG0S3AFT05 VALID BLOCKS (1) SYMBOL NVB PARAMETER Number of Valid Blocks MIN TYP. MAX UNIT 1004 1024 Blocks (1) The TC58NVG0S3A occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. (2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.3 3.6 V VIH High Level input Voltage 2.0 VCC + 0.3 V VIL Low Level Input Voltage −0.3* 0.8 V −2 V (pulse width lower than 20 ns) * DC CHARACTERISTICS (Ta = 0 to 70°C, VCC = 2.7 V~3.3 V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current VIN = 0 V to VCC ±10 µA ILO Output Leakage Current VOUT = 0 V to VCC ±10 µA ICCO1 Reading CE = VIL, IOUT = 0 mA, tcycle = 50 ns 10 30 mA ICCO2 Programming Current 10 30 mA ICCO3 Erasing Current 10 30 mA ICCS1 Standby Current CE = VIH, WP = 0 V/VCC 1 mA ICCS2 Standby Current CE = VCC − 0.2 V, WP = 0 V/VCC 50 µA VOH High Level Output Voltage VCC, IOH = −400 µA 2.4 V VOL Low Level Output Voltage VCC, IOL = 2.1 mA 0.4 V 8 mA IOL ( RY / BY ) Output current of RY / BY pin VOL = 0.4 V 2003-08-20A 3/33 TC58NVG0S3AFT05 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C, VCC = 2.7 V~3.6 V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 0 ns tCLH CLE Hold Time 10 ns tCS CE Setup Time 0 ns tCH CE Hold Time 10 ns tWP Write Pulse Width 25 ns tALS ALE Setup Time 0 ns tALH ALE Hold Time 10 ns tDS Data Setup Time 20 ns tDH Data Hold Time 10 ns tWC Write Cycle Time 50 ns tWH WE High Hold Time 15 ns tWW WP High to WE Low 100 ns tRR Ready to RE Falling Edge 20 ns tRW Ready to WE Falling Edge 20 ns tRP Read Pulse Width 35 ns tRC Read Cycle Time 50 ns tREA RE Access Time (Serial Data Access) 35 ns tCEA CE Access Time 45 ns tCLEA CLE Access Time 45 ns tALEA ALE Access Time 45 ns tREAID RE Access Time (ID Read) 35 ns tOH Data Output Hold Time 10 ns tRHZ RE High to Output High Impedance 30 ns tCHZ CE High to Output High Impedance 20 ns tREH RE High Hold Time 15 ns tIR Output-High-impedance-to- RE Falling Edge 0 ns tRSTO RE Access Time (Status Read) 35 ns tCSTO CE Access Time (Status Read) 45 ns tCLSTO CLE Access Time (Status Read) 45 ns tRHW RE High to WE Low 30 ns tWHC WE High to CE Low 30 ns tWHR WE High to RE Low 30 ns tCR CE Low to RE Low (ID Read) 100 ns tR Memory Cell Array to Starting Address 25 µs tWB WE High to Busy 200 ns tRST Device Reset Time (Read/Program/Erase) 6/10/500 µs 2003-08-20A NOTES 4/33 TC58NVG0S3AFT05 AC TEST CONDITIONS PARAMETER CONDITION Input level 2.4 V, 0.4 V Input pulse rise and fall time 3 ns Input comparison level 1.5 V, 1.5 V Output data comparison level 1.5 V, 1.5 V CL (100 pF) + 1 TTL Output load PROGRAMMING AND ERASING CHARACTERISTICS (Ta = 0 to 70°C, VCC = 2.7 V~3.6 V) SYMBOL PARAMETER MIN TYP. MAX UNIT µs tPROG Average Programming Time 200 700 N Number of Programming Cycles on Same Page (per 512 + 16 bytes) 2 tBERASE Block Erasing Time 2 4 NOTES (1) ms (1) Refer to Application Note (12) toward the end of this document. 2003-08-20A 5/33 TC58NVG0S3AFT05 TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time Hold Time WE tDS tDH I/O1 to I/O8 : VIH or VIL Command Input Cycle Timing Diagram CLE tCLS tCS tCLH tCH CE tWP WE tALS tALH ALE tDS tDH I/O1 to I/O8 : VIH or VIL 2003-08-20A 6/33 TC58NVG0S3AFT05 Address Input Cycle Timing Diagram tCLS CLE tCS tWC tWC tWC CE tWP tWH tWP tWH tWP tWH tWP WE tALS tALH ALE tDS I/O1 to I/O8 tDH tDS CA0 to 7 tDH tDS CA8 to 11 tDH tDS PA0 to 7 tDH PA8 to 15 : VIH or VIL Data Input Cycle Timing Diagram tCLH CLE tCH CE tALS tWC ALE tWP tWH tWP tWP WE tDS I/O1 to I/O8 tDH DIN0 tDS tDH DIN1 tDS tDH DIN2111 : VIH or VIL 2003-08-20A 7/33 TC58NVG0S3AFT05 Serial Read Cycle Timing Diagram tRC tCEA CE tRP tREH RE tOH tRHZ tREA tRP tREA tRP tOH tRHZ tCHZ tOH tRHZ tREA I/O1 to I/O8 tRR RY / BY Status Read Cycle Timing Diagram tCLSTO CLE tCLS tCLH tCS CE tWP tCH WE tWHC tCSTO tCHZ tWHR RE tOH tDS I/O1 to I/O8 tDH 70h* tIR tRSTO tRHZ Status output RY / BY * 70h represents the hexadecimal number : VIH or VIL 2003-08-20A 8/33 TC58NVG0S3AFT05 Read Cycle Timing Diagram tCLEA CLE tCLS tCLH tCLS tCLH tCS tCH tCS tCH tCEA CE tWC WE tALH tALS tALH tALS ALE tR tRC tWB RE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 tDS tDH tREA tRR I/O1 to I/O8 00h CA0 to 7 DOUT DOUT N+1 N Data out from Col. Add. N 30h Col. Add. N RY/BY Read Cycle Timing Diagram: When Interrupted by CE tCLEA CLE tCLS tCLH tCLS tCLH tCS tCH tCS tCH tCEA CE tWC WE tALH tALS tALH tALS tCHZ ALE tR tRC tRHZ tWB RE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 tDS tDH tREA tOH tRR I/O1 to I/O8 00h CA0 to 7 Col. Add. N 30h DOUT DOUT N+1 N Col. Add. N RY/BY 2003-08-20A 9/33 TC58NVG0S3AFT05 Column Address Change in Read Cycle Timing Diagram (1/2) tCLEA CLE tCLS tCLH tCLS tCLH tCS tCH tCS tCH CE tWC tCEA WE tALH tALS tALH tALS ALE tR tWB RE I/O1 to I/O8 tRC tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 00h CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 30h Column address A Page address P tRR tREA DOUT DOUT A A+1 DOUT A+N Page address P RY/BY Column address A 1 Continues to 1 of next page 2003-08-20A 10/33 TC58NVG0S3AFT05 Column Address Change in Read Cycle Timing Diagram (2/2) tCLEA CLE tCLS tCS tCLS tCLH tCH tCS tCLH tCH CE tWC tCEA WE tRHW tALH tALS tALH tALS ALE tRC RE tDS tDH tDS tDH tDS tDH tDS tDH tREA tIR I/O1 to I/O8 DOUT A+N 05h CA0 to 7 CA8 to 11 Column address B E0h DOUT DOUT B B+1 DOUT B + N’ Page address P RY/BY Column address B 1 Continued from 1 of last page 2003-08-20A 11/33 TC58NVG0S3AFT05 Auto-Program Operation Timing Diagram tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALS tALH tProg tWB tALS ALE RE tDS tDS tDH I/O1 to I/O8 80h tDS tDH tDS tDH tDH 10h CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 DIN0 DIN1 70h Status output DIN2111 RY / BY : VIH or VIL : Do not input data while data is being output. 2003-08-20A 12/33 TC58NVG0S3AFT05 Auto Block Erase Timing Diagram CLE tCLS tCS tCLH tCLS CE WE tALS tALH tWB tBERASE ALE RE tDS tDH I/O1 to I/O8 60h RY / BY Auto Block Erase Setup command D0h PA0 to 7 PA8 to 15 Erase Start command : VIH or VIL 70h Busy Status output Status Read command : Do not input data while data is being output. 2003-08-20A 13/33 TC58NVG0S3AFT05 ID Read Operation Timing Diagram tCLS CLE tCLS tCS tCS tCH tCEA CE tCH WE tALS tALH tALH tALEA ALE RE tDH tDH I/O tREAID tREAID tREAID 90h 00h 98h F1h ID Read command Address 00 Maker code Device code tREAID Note 1 tREAID Note 2 Note 3 : VIH or VIL Note 1: 80h or 00h Note 2: 95h or 15h Note 3: 40h or C0h 2003-08-20A 14/33 TC58NVG0S3AFT05 PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Chip Enable: CE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC Figure 1. Pinout The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes High. Write Enable: WE The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + 1) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with appropriate resister. 2003-08-20A 15/33 TC58NVG0S3AFT05 Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. I/O1 2048 I/O8 64 64 Pages = 1 block 65536 pages 1024 blocks A page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112 bytes 1 block = 2112 bytes × 64 pages = (128K + 4K) bytes Capacity = 2112 bytes × 64 pages × 1024 blocks An address is read in via the I/O port over four consecutive clock cycles, as shown in Table 1. 8I/O 2112 Figure 2. Schematic Cell Layout Table 1. Addressing I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 L L L L CA11 CA10 CA9 CA8 Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 First cycle Second cycle CA0 to CA11: Column address PA0 to PA15 : Page address PA6 to PA15 : Block address PA0 to PA5 : NAND address in block Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic Table WP L H * L L H H L H L H * Serial Data Output L L L H During Programming (Busy) * * * * * H During Erasing (Busy) * * * * * H During Reading (Busy) * * * * * * Program, Erase Inhibit * * * * * L Standby * * H * * 0 V/VCC ALE CE Command Input H L Data Input L Address input WE *1 RE CLE * H: VIH, L: VIL, *: VIH or VIL *1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit 2003-08-20A 16/33 TC58NVG0S3AFT05 Table 3. Command table (HEX) First Cycle Second Cycle Acceptable while Busy Serial Data Input 80 Auto Program 10 Read Address Input 00 Column Address Change in Serial Data Output 05 Read Start 30 Read Column Change E0 Auto Block Erase 60 D0 ID Read 90 Status Read 70 ○ Reset FF ○ HEX data bit assignment (Example) Serial Data Input: 80h 1 0 0 0 0 0 0 0 I/O8 7 6 5 4 3 2 I/O1 Table 4. shows the operation states for Read mode. Table 4. Read mode operation states CLE ALE CE WE RE I/O1 to I/O8 Power Output select L L L H L Data output Active Output Deselect L L L H H High impedance Active Standby L L H H * High impedance Standby Read Busy * * * * * High Impedance Active H: VIH, L: VIL, *: VIH or VIL 2003-08-20A 17/33 TC58NVG0S3AFT05 DEVICE OPERATION Read Mode Read mode is set when “00h” and “30h” commands are issued to the Command register. Between the commands, start address for the Read mode need to be issued. Refer to Figure 3. below for sequence and the block diagram (Refer to the detailed timing chart.). CLE CE WE ALE RE RY / BY Column Address M I/O Busy Page Address N 00h 30h M+1 M M+2 Page Address N Start-address input M 2111 Select page N Cell array Figure 3. Read mode (1) operation A data transfer operation from the cell array to the register starts on the rising edge of WE in the 30h command input cycle (after the address information has been latched). The device will be in Busy state during this transfer period. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Random Column Address Change in Read Cycle CLE CE WE ALE RE Busy RY / BY Col. M I/O 00h 30h Col. M Page N Select page N M+1 M+2 M+3 Page N Start from Col. M Start-address input M M M’ Cell array 05h E0h Col. M’ M’ M’ + 1 M’ + 2 M’ + 3 M’ + 4 Page N Start from Col. M’ In the serial data out from the register, the column address can be changed by inputting the column address with 05h and E0h commands. The data are read out in serial from the column address which is input to the device by 05h and E0h commands with RE clock. Figure 4. Random Column Address Change in Serial Read 2003-08-20A 18/33 TC58NVG0S3AFT05 Auto Page Program Operation The device carries out an Automatic Page Program operation when it receives a “10h” Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) CLE CE WE ALE RE RY/BY I/O Din Din Din 80h Col. M Page P Din 70h Status Out Data Data input Program 10h Reading & verification Selected page The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10h” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Figure 7. Auto Page Program operation Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 Block Address input: 2 cycles RY / BY 70 Status Read command Erase Start command I/O Pass Fail Busy 2003-08-20A 19/33 TC58NVG0S3AFT05 ID Read The device contains ID code which identify the device type, the manufacturer, and some features of the device. The ID codes can be read out under the following timing conditions: CLE tCEA CE WE tALEA ALE RE tREAID I/O 90h 00h 98h F1h ID Read command Address 00 Maker code Device code Note 1 Note 2 Note 3 Note 1: 80h or 00h Note 2: 95h or 15h Note 3: 40h or C0h For the specifications of the access times tREAID, tCR and tALEA refer to the AC Characteristics. Figure 13. ID Read Timing Table 6. Code table Descripton I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data 1st Data Maker Code 1 0 0 1 1 0 0 0 98h 2nd Data Device Code 1 1 1 1 0 0 0 1 F1h 3rd Data Chip Number, Cell Type, PGM Page 0 or 1 0 0 0 0 0 0 0 80h or 00h 4th Data Page Size, Block Size, Redundant Size, Organization 0 or 1 0 0 1 0 1 0 1 95h or 15h 5th Data Plane Number, Plane Size 0 or 1 1 0 0 0 0 0 0 40h or C0h 3rd Data Descripton I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 1 0 0 2 0 1 4 1 0 8 1 1 Internal Chip Number 2 level cell 0 0 4 level cell 0 1 8 level cell 1 0 16 level cell 1 1 Cell Type Number of simultaneously programmed pages 1 0 0 2 0 1 4 1 0 8 1 1 Reserved 1 Reserved 2 0 0 or 1 2003-08-20A 20/33 TC58NVG0S3AFT05 4th Data Descripton Page Size (without redundant area) Block Size (without redundant area) Redundant area size (byte/512 byte) Organization I/O8 I/O7 I/O6 I/O5 I/O2 I/O1 1 KB 0 0 2 KB 0 1 4 KB 1 0 8 KB 1 1 I/O2 I/O1 0 0 64 KB 0 0 128 KB 0 1 256 KB 1 0 512 KB 1 1 I/O4 I/O3 8 0 0 16 0 1 Reserved 1 0 Reserved 1 1 I/O4 I/O3 1 0 0 2 0 1 4 1 0 8 1 1 ×8 0 ×16 1 Reserved 0 or 1 5th Data Descripton I/O8 I/O7 I/O6 I/O5 Plane Number 64 Mbit 0 0 0 128 Mbit 0 0 1 256 Mbit 0 1 0 512 Mbit 0 1 1 1 Gbit 1 0 0 2 Gbit 1 0 1 4 Gbit 1 1 0 8 Gbit 1 1 1 Plane Size Reserved 0 or 1 2003-08-20A 21/33 TC58NVG0S3AFT05 Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass /fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a “70h” command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS OUTPUT I/O1 Chip Status 1 Pass: 0 I/O2 Not Used 0 or 1 I/O3 Not Used 0 I/O4 Not Used 0 I/O5 Not Used 0 I/O6 Ready/Busy I/O7 Not Used I/O8 Write Protect Fail: 1 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state. Ready: 1 Busy: 0 0 or 1 Protect: 0 Not Protected: 1 An application example with multiple devices is shown in Figure 6. CLE ALE WE RE CE1 CE2 CE3 CEN CEN + 1 Device 1 Device 2 Device 3 Device N Device N+1 I/O1 to I/O8 RY/BY Busy RY/BY CLE ALE WE CE1 CEN RE I/O 70h 70h Status on Device 1 Status on Device N Figure 6. Status Read timing application example System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2003-08-20A 22/33 TC58NVG0S3AFT05 Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an “FFh” Reset command input during the various device operations is as follows: When a Reset (FFh) command is input during programming Figure 8. 80 10 FF 00 Internal VPP RY/BY tRST (max 10 µs) When a Reset (FFh) command is input during erasing Figure 9. D0 FF 00 Internal erase voltage RY/BY tRST (max 500 µs) When a Reset (FFh) command is input during Read operation Figure 10. 00 FF 00 RY/BY tRST (max 6 µs) When a Status Read command (70h) is input after a Reset Figure 11. FF 70 I/O status : Pass/Fail → Pass : Ready/Busy → Ready RY/BY FF 70 I/O status : Ready/Busy → Busy RY/BY When two or more Reset commands are input in succession Figure 12. (1) (2) (3) FF FF FF RY/BY The second FF command is invalid, but the third FF command is valid. 2003-08-20A 23/33 TC58NVG0S3AFT05 APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The timing sequence shown in Figure 15 is necessary for power-on/off sequence. The device internal initialization start after the power supply reaches appropriate level in power on sequence. During the initialization the device Ready/Busy signal outputs Busy state as shown in the Figure 15. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecting against data corruption at power-on/off. 2.7 V 2.5 V 0V VCC Don’t care Don’t care CE , WE , RE CLE, ALE WP VIH VIL VIL 1 ms max Operation 100 µs max Don’t care Invalid Ready/Busy Figure 15. Power-on/off Sequence (2) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset Figure 16. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3. is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70h, and FFh. 2003-08-20A 24/33 TC58NVG0S3AFT05 (5) Acceptable commands after Serial Input command “80h” Once the Serial Input command “80h” has been input, do not input any command other than the Column Address Change in Auto Program command “10h” or the Reset command “FFh”. 80 FF WE Address input RY / BY If a command other than “10h” or “FFh” is input, the Program operation is not performed and the device operation is set to the mode which the input command specifies. 80 XX 10 Mode specified by the command. Programming cannot be executed. Command other than “10h” or “FFh” (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. From the LSB page to MSB page DATA IN: Data (1) Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) Data register Data (64) Data register Page 0 Page 1 Page 2 (1) (2) (3) Page 0 Page 1 Page 2 (2) (32) (3) Page 31 (32) Page 31 (1) Page 63 (64) Page 63 (64) Figure 17. page programming within a block 2003-08-20A 25/33 TC58NVG0S3AFT05 (7) Status Read during a Read operation 00 command 00 30 [A] 70 CE WE RY/BY RE Status Read command input Address N Status output Status Read Figure 18. The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the device has been set to Status Read mode by a “70h” command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command “00h” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary (8) Auto programming failure Fail 80 10 70 I/O 80 Address Data input M 10 Address Data input N 80 10 M If the programming result for page address M is Fail, do not try to program the page to address N in another block without the data input sequence. Because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. N Figure 19. (9) RY/ BY : termination for the Ready/Busy pin ( RY/ BY ) A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain circuit. V CC Ready VCC 3.0 V R Device VCC 3.0 V 1.0 V RY/BY CL Busy 1.0 V tf tr VSS 1.5 µs tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. tf 1.0 µs Figure 19. 15 ns 10 ns tf tr 0.5 µs 0 VCC = 3.3 V Ta = 25°C CL = 100 pF 5 ns 1 KΩ 2 KΩ 3 KΩ 4 KΩ R 2003-08-20A 26/33 TC58NVG0S3AFT05 (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN 80 10 WP RY/BY tWW (100 ns min) Disable Programming WE DIN 80 10 WP RY/BY tWW (100 ns min) Enable Erasing WE DIN 60 D0 WP RY/BY tWW (100 ns min) Disable Erasing WE DIN 60 D0 WP RY/BY tWW (100 ns min) 2003-08-20A 27/33 TC58NVG0S3AFT05 (11) When five address cycles are input Although the device may read in a fifth address, it is ignored inside the chip. Read operation CLE CE WE ALE I/O 00h 30h Ignored Address input RY / BY Figure 22. Program operation CLE CE WE ALE I/O 80h Ignored Address input Data input Figure 23. 2003-08-20A 28/33 TC58NVG0S3AFT05 (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 8 segments as follows:Data area (column address 0 to 2047): 512 bytes × 4 segments 1st segment: column address 0 to 511 2nd segment: column address 512 to 1023 3rd segment: column address 1024 to 1535 4th segment: column address 1536 to 2047 Redundant area (column address 2048 to 2111): 16 bytes × 4 segments 1st segment: column address 2048 to 2063 2nd segment: column address 2064 to 2079 3rd segment: column address 2080 to 2095 4th segment: column address 2096 to 2111 Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1 s All 1 s Data Pattern 2 All 1 s 8th programming Result All 1 s Data Pattern 1 Data Pattern 2 Data Pattern 8 Data Pattern 8 Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be “1” (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”). 2003-08-20A 29/33 TC58NVG0S3AFT05 (13) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: Bad Block Bad Block At the time of shipment, all data bytes in a valid block are FFh. For bad blocks, all bytes are not in the FFh state. Please don’t perform erase operation to bad blocks. Check if the device has any bad blocks after installation into the system. Figure 27. shows the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit line by the select gate The number of valid blocks at the time of shipment is as follows: Figure 26. Valid (Good) Block Number MIN TYP. MAX UNIT 1004 1024 Block Bad Block Test Flow Read Check: Read the 1st page or the 2nd page of each block. If the column address 0 or 2048 of the 1st page or the 2nd page is not FF (Hex), define the block as a bad block. Start Block No = 1 Fail Read Check Pass Block No. = Block No. + 1 Bad Block *1 No Block No. = 1024 Yes End *1: No erase operation is allowed to detected bad blocks Figure 27. 2003-08-20A 30/33 TC58NVG0S3AFT05 (14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENIE Block Erase Failure Status Read after Erase → Block Replacement Page Programming Failure Status Read after Program → Block Replacement Programming Failure (1) Block Verify after Program → Retry Single Bit “1 to 0” • ECC: Error Correction Code. • Block Replacement (2) ECC Program Error occurs Buffer memory Block A When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using another appropriate scheme). Block B Figure 28. Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. 2003-08-20A 31/33 TC58NVG0S3AFT05 Package Dimensions Weight: 0.53 g (typ.) 2003-08-20A 32/33 TC58NVG0S3AFT05 RESTRICTIONS ON PRODUCT USE 030619EBA • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2003-08-20A 33/33