CAT24M01 1 Mb I2C CMOS Serial EEPROM Description The CAT24M01 is a 1024 kb Serial CMOS EEPROM, internally organized as 131,072 words of 8 bits each. It features a 256−byte page write buffer and supports the Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). External address pins make it possible to address up to four CAT24M01 devices on the same bus. On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications. http://onsemi.com SOIC−8 W SUFFIX CASE 751BD UDFN−8 HU5 SUFFIX CASE 517BU SOIC−8 X SUFFIX CASE 751BE Features • • • • • • • • • • • Supports Standard, Fast and Fast−Plus I2C Protocol 1.8 V to 5.5 V Supply Voltage Range 256−Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range 8−pin PDIP, SOIC, TSSOP and 8−pad UDFN Packages These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant PDIP−8 L SUFFIX CASE 646AA PIN CONFIGURATION NC 1 VCC A1 WP A2 SCL VSS SDA PDIP (L), SOIC (W, X), TSSOP (Y), UDFN (HU5) For the location of Pin 1, please consult the corresponding package drawing. VCC SCL PIN FUNCTION CAT24M01 A2, A1 TSSOP−8 Y SUFFIX CASE 948AL Pin Name SDA A1, A2 WP VSS Figure 1. Functional Symbol Function Device Address SDA Serial Data SCL Serial Clock WP Write Protect VCC Power Supply VSS Ground ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. © Semiconductor Components Industries, LLC, 2012 October, 2012 − Rev. 3 1 Publication Order Number: CAT24M01/D CAT24M01 MARKING DIAGRAMS 24M01A AYMXXX M0L ALL YM G (SOIC−8) (UDFN−8) 24M01A = Specific Device Code A = Assembly Location Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXX = Last Three Digits of XXX = Assembly Lot Number 24M01A AXXX YYWWG (PDIP−8) 24M01A = Specific Device Code A = Assembly Location XXX = Last Three Digits of XXX = Assembly Lot Number YY = Production Year (Last Two Digits) WW = Production Week (Two Digits) G = Pb−Free Designator M0L = Specific Device Code A = Assembly Location Code LL = Assembly Lot Number Y = Year M = Month G = Pb−Free Package Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature –65 to +150 °C Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Notes 3, 4) TDR Parameter Endurance Min Units 1,000,000 Program/Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Test Condition: Page Mode, VCC = 5 V, 25°C. 4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified. Symbol Parameter Test Conditions Max Units 1 mA VCC = 1.8 V 3.5 mA VCC = 5.5 V 5.0 ICCR Read Current Read, fSCL = 400 kHz / 1 MHz ICCW Write Current ISB IL Standby Current I/O Pin Leakage All I/O Pins at GND or VCC Pin at GND or VCC Min TA = −40°C to +85°C 2 TA = −40°C to +125°C 5 TA = −40°C to +85°C 1 TA = −40°C to +125°C 2 mA mA VIL1 Input Low Voltage 2.5 V ≤ VCC ≤ 5.5 V −0.5 0.3 VCC V VIL2 Input Low Voltage 1.8 V ≤ VCC < 2.5 V −0.5 0.25 VCC V VIH1 Input High Voltage 2.5 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.5 V VIH2 Input High Voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V http://onsemi.com 2 CAT24M01 Table 4. PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified. Max Units CIN (Note 5) SDA I/O Pin Capacitance Parameter VIN = 0 V 8 pF CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF WP Input Current, Address Input Current (A1, A2) VIN < VIH, VCC = 5.5 V 75 mA VIN < VIH, VCC = 3.3 V 50 VIN < VIH, VCC = 1.8 V 25 VIN > VIH 2 Symbol IWP, IA (Note 6) Conditions 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 6. When not driven, the WP, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. Table 5. A.C. CHARACTERISTICS (Note 7) VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified. Standard VCC = 1.8 V − 5.5 V Symbol FSCL tHD:STA Min Max Clock Frequency Min 100 START Condition Hold Time tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock Max Fast−Plus VCC = 2.5 V − 5.5 V TA = −405C to +855C Min 400 Max Units 1,000 kHz 4 0.6 0.25 ms 4.7 1.3 0.45 ms 4 0.6 0.40 ms 4.7 0.6 0.25 ms Data In Hold Time 0 0 0 ms Data In Setup Time 250 100 50 ns tSU:STA START Condition Setup Time tHD:DAT tSU:DAT tR (Note 8) SDA and SCL Rise Time 1,000 300 100 ns tF (Note 8) SDA and SCL Fall Time 300 300 100 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti (Note 8) 4 0.6 0.25 ms 4.7 1.3 0.5 ms 3.5 50 0.9 50 Noise Pulse Filtered at SCL and SDA Inputs 50 0.40 50 50 ms ns 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR tPU (Notes 8, 9) 7. 8. 9. Parameter Fast VCC = 1.8 V − 5.5 V Write Cycle Time Power-up to Ready Mode 5 5 5 ms 0.1 0.1 0.1 ms Test conditions according to “A.C. Test Conditions” table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IL = 3 mA (VCC ≥ 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF http://onsemi.com 3 CAT24M01 Power-On Reset (POR) The CAT24M01 incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR behavior protects the device against brown−out failure, following a temporary loss of power. During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2). START The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. STOP Pin Description SCL: The Serial Clock input pin accepts the Serial Clock signal generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A1 and A2: The Address pins accept the device address. These pins have on−chip pull−down resistors. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on−chip pull−down resistor. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command). Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 2 bits, A2, A1, select one of 4 possible memory devices connected on a single I2C bus. The A2 and A1 bits must match the state of the external address pins. The seventh bit, a16 is the most significant internal address bit. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. To select an internal memory location (data byte) a 17−bit address word is required: a16 bit from the Slave address byte followed by two address bytes. Functional Description The CAT24M01 supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24M01 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 4 devices may be connected to the bus as determined by the device address inputs A1 and A2. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 5. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). http://onsemi.com 4 CAT24M01 SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 a16 R/W DEVICE ADDRESS Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Acknowledge Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 5. Bus Timing http://onsemi.com 5 tBUF CAT24M01 WRITE OPERATIONS Acknowledge Polling Acknowledge polling can be used to determine if the CAT24M01 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS). The CAT24M01 will not acknowledge the Slave address, as long as internal Write is in progress. Byte Write In Byte Write mode the Master sends a START, followed by Slave address, two byte address and data to be written (Figure 6). The Slave acknowledges all 4 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 7). During internal Write, the Slave will not acknowledge any Read or Write request from the Master. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24M01. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT24M01 will not acknowledge the data byte and the Write request will be rejected. Page Write The CAT24M01 contains 131,072 bytes of data, arranged in 512 pages of 256 bytes each. The most significant 9 bits of the address word (a16 from the Slave Address byte and most significant Address byte) identify the page and the last 8 bits identify the byte within the page. The 17−bit address word (a16 from the Slave Address byte followed by two address bytes) points to the first byte to be written. Up to 256 bytes can be written in one Write cycle (Figure 8). The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 256 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap−around’ fashion (within the selected page). The internal Write cycle starts immediately following the STOP. Delivery State The CAT24M01 is shipped erased, i.e., all bytes are FFh. http://onsemi.com 6 CAT24M01 S T BUS ACTIVITY: A MASTER R T SLAVE ADDRESS BYTE ADDRESS a15 − a8 a7 − a0 S T O P DATA SDA LINE S P A C K A C K A C K A C K Figure 6. Byte Write Timing SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing S BUS T ACTIVITY: A MASTER R T SLAVE ADDRESS BYTE ADDRESS a15 − a8 a7 − a0 DATA DATA n S T O P DATA n+63 SDA LINE S P A C K A C K A C K A C K A C K Figure 8. Page Write Timing ADDRESS BYTE DATA BYTE 1 8 a7 a0 9 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing http://onsemi.com 7 A C K A C K CAT24M01 READ OPERATIONS The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 11). Here the START is followed by the Slave address (with the R/W bit set to ‘0’) and the desired two byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Immediate Address Read In standby mode, the CAT24M01 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that ‘previous’ byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT24M01 is presented with a Slave address containing a ‘1’ in the R/W bit position (Figure 10), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition. Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT24M01, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will ‘wrap−around’ to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. Selective Read The Read operation can also be started at an address different from the one stored in the internal address counter. S T BUS ACTIVITY: A MASTER R T S T O P SLAVE ADDRESS SDA LINE S P A C K SCL 8 SDA N O A C K DATA 9 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Address Read Timing S T BUS ACTIVITY: A MASTER R T S T A R T BYTE ADDRESS a15 − a8 a7 − a0 SLAVE ADDRESS SDA LINE S SLAVE ADDRESS S T O P DATA S A C K A C K P A C K N O A C K A C K Figure 11. Selective Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x P SDA LINE A C K A C K A C K Figure 12. Sequential Read Timing http://onsemi.com 8 A C K N O A C K CAT24M01 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 9 CAT24M01 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 MAX c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 10 CAT24M01 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.20 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 11 CAT24M01 PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL MIN NOM A E1 E MAX 2.03 A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 e 1.27 BSC L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A e b q L A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. http://onsemi.com 12 CAT24M01 PACKAGE DIMENSIONS UDFN8 3.0x2.0, 0.5P CASE 517BU−01 ISSUE O A B D PIN 1 REFERENCE 0.15 C ÍÍÍ ÍÍÍ ÍÍÍ ÍÍÍ 0.15 C (0.065) E (0.127) DETAIL A DIM A A1 b D D2 E E2 e L TOP VIEW DETAIL A 0.05 C A 0.05 C A1 SIDE VIEW NOTE 4 1 4 SEATING PLANE C 0.10 D2 8X C A B M L 0.10 M C A B E2 5 8 e 8X b 0.10 M C A B 0.05 M C D BOTTOM VIEW NOTE 3 RECOMMENDED MOUNTING FOOTPRINT 1.56 8X 1.06 0.63 3.30 PKG OUTLINE 1 8X 0.50 PITCH NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 0.32 DIMENSIONS: MILLIMETERS http://onsemi.com 13 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.20 0.30 2.00 BSC 1.35 1.45 3.00 BSC 0.85 0.95 0.50 BSC 0.35 0.45 CAT24M01 Example of Ordering Information (Note 10) Specific Device Marking Package Type Temperature Range Lead Finish Shipping (Note 11) CAT24M01LE−G 24M01A PDIP−8 −40°C to +125°C NiPdAu Rail CAT24M01LI−G 24M01A PDIP−8 −40°C to +85°C NiPdAu Rail CAT24M01WE−GT3 24M01A SOIC−8, JEDEC −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAT24M01WI−GT3 24M01A SOIC−8, JEDEC −40°C to +85°C NiPdAu Tape & Reel, 3,000 Units / Reel CAT24M01XE−T2 24M01A SOIC−8, EIAJ −40°C to +125°C Matte−Tin Tape & Reel, 2,000 Units / Reel CAT24M01XI−T2 Device Order Number 24M01A SOIC−8, EIAJ −40°C to +85°C Matte−Tin Tape & Reel, 2,000 Units / Reel CAT24M01YE−GT3 M01C TSSOP−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAT24M01YI−GT3 M01C TSSOP−8 −40°C to +85°C NiPdAu Tape & Reel, 3,000 Units / Reel CAT24M01HU5I−GT3 MOL UDFN8 −40°C to +85°C NiPdAu Tape & Reel, 3,000 Units / Reel 10. All packages are RoHS-compliant (Lead-free, Halogen-free). 11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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