CYPRESS CY7B9911V

CY7B9911V
3.3V RoboClock+™
High Speed Low Voltage Programmable Skew
Clock Buffer
Features
Functional Description
■
All output pair skew <100 ps typical (250 max)
■
3.75 to 110 MHz output operation
■
User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted
1
1
❐ Operation at ⁄2 and ⁄4 input frequency
❐ Operation at 2x and 4x input frequency (input as low as
3.75 MHz)
The CY7B9911V 3.3V RoboClock+™ High Speed Low
Voltage Programmable Skew Clock Buffer (LVPSCB) offers
user selectable control over system clock functions. These
multiple output clock drivers provide the system integrator with
functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50Ω.
They deliver minimal and specified output skews and full swing logic
levels (LVTTL).
■
Zero input-to-output delay
■
50% duty cycle outputs
■
LVTTL outputs drive 50Ω terminated lines
■
Operates from a single 3.3V supply
■
Low operating current
■
32-pin PLCC package
■
Jitter 100 ps (typical)
Logic Block Diagram
Each output is hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs that can skew
up to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and cancels
the transmission line delay effects. When this “zero delay”
capability of the LVPSCB is combined with the selectable
output skew functions, you can create output-to-output delays
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low frequency clock that are multiplied
by two or four at the clock destination. This facility minimizes
clock distribution difficulty enabling maximum system clock
speed and flexibility.
TEST
PHASE
FREQ
DET
FB
REF
FILTER
VCO AND
TIME UNIT
GENERATOR
FS
4F0
4F1
3F0
3F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
SKEW
3Q0
3Q1
SELECT
2Q0
2F0
2F1
MATRIX
2Q1
1Q0
1F0
1F1
1Q1
Cypress Semiconductor Corporation
Document Number: 38-07408 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2007
CY7B9911V
3.3V RoboClock+™
Pin Configuration
FS
VCCQ
REF
GND
4
3
2
1
32 31 30
29
2F1
3F0
TEST
PLCC
2F0
3F1
5
4F0
6
28
GND
4F1
7
27
1F1
VCCQ
8
26
1F0
VCCN
9
25
VCCN
4Q1
10
24
1Q0
4Q0
11
23
1Q1
GND
12
22
GND
GND
13
21
14 15 16 17 18 19 20
GND
2Q0
2Q1
VCCN
FB
VCCN
3Q0
3Q1
CY7B9911V
Pin Definitions
IO
Description
REF
Signal Name
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
FS
I
Three level frequency range select. See Table 1.
1F0, 1F1
I
Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1
I
Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1
I
Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1
I
Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST
I
Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.
1Q0, 1Q1
O
Output pair 1. See Table 2.
2Q0, 2Q1
O
Output pair 2. See Table 2.
3Q0, 3Q1
O
Output pair 3. See Table 2.
4Q0, 4Q1
O
Output pair 4. See Table 2.
VCCN
PWR
Power supply for output drivers.
VCCQ
PWR
Power supply for internal circuitry.
GND
PWR
Ground.
Document Number: 38-07408 Rev. *D
Page 2 of 14
CY7B9911V
3.3V RoboClock+™
Block Diagram Description
Skew Select Matrix
The Phase Frequency Detector and Filter blocks accept inputs
from the Reference Frequency (REF) input and the Feedback
(FB) input. They generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
The skew select matrix is comprised of four independent
sections. Each section has two low skew, high fanout drivers
(xQ0, xQ1), and two corresponding three level function select
(xF0, xF1) inputs. Table 2 shows the nine possible output
functions for each section as determined by the function select
inputs. All times are measured with respect to the REF input
assuming that the output connected to the FB input has 0tU
selected.
VCO and Time Unit Generator
Table 2. Programmable Skew Configurations[1]
Phase Frequency Detector and Filter
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
Table 1. Frequency Range Select and tU
fNOM (MHz)
FS[2, 3]
Min
Max
1
t U = -----------------------f NOM × N
where N =
Calculation[1]
Approximate
Frequency (MHz) At
Which tU = 1.0 ns
Function Selects
Output Functions
1F1, 2F1,
3F1, 4F1
1F0, 2F0,
3F0, 4F0
LOW
LOW
–4tU
LOW
MID
–3tU
–6tU
–6tU
LOW
HIGH
–2tU
–4tU
–4tU
MID
LOW
–1tU
–2tU
–2tU
MID
MID
0tU
0tU
0tU
MID
HIGH
+1tU
+2tU
+2tU
HIGH
LOW
+2tU
+4tU
+4tU
MID
+3tU
+6tU
+6tU
HIGH
+4tU
Divide by 4
Inverted
LOW
15
30
44
22.7
HIGH
MID
25
50
26
38.5
HIGH
HIGH
40
110
16
62.5
1Q0, 1Q1,
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
Divide by 2 Divide by 2
Notes
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see). Nominal frequency (fNOM) always
appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs is fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication
using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 2.8V.
Document Number: 38-07408 Rev. *D
Page 3 of 14
CY7B9911V
3.3V RoboClock+™
Figure 1 shows the typical outputs with FB connected to a zero skew output.[4]
U
U
U
U
U
U
t 0 +1t
t 0 +2t
t 0 +3t
t 0 +4t
t 0 +5t
t 0 +6t
t0
t 0 – 1t U
t 0 – 2t U
t 0 – 3t U
t 0 – 4t U
t 0 – 5t U
t 0 – 6t U
Figure 1. The Typical Outputs with FB Connected to a Zero Skew Output
FB Input
REFInput
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6tU
LL
LH
– 4tU
LM
(N/A)
– 3tU
LH
ML
– 2tU
ML
(N/A)
– 1tU
MM
MM
MH
(N/A)
+1tU
HL
MH
+2tU
HM
(N/A)
+3tU
0tU
HH
HL
+4tU
(N/A)
HM
+6tU
(N/A)
LL/HH
DIVIDED
(N/A)
HH
INVERT
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B9911V to operate as described in “Block Diagram
Description” on page 3. For testing purposes, any of the three
level inputs can have a removable jumper to ground or be tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly control all outputs. Relative
output-to-output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Note
4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).
Document Number: 38-07408 Rev. *D
Page 4 of 14
CY7B9911V
3.3V RoboClock+™
Operational Mode Descriptions
Figure 2. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z0
L1
SYSTEM
CLOCK
FB
REF
FS
LOAD
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
L2
Z0
LOAD
L3
Z0
L4
LOAD
TEST
Z0
LENGTH L1 = L2 = L3 = L4
Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew
clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of the outputs are aligned and drive a
terminated transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency
range is selected with the FS pin. The low skew specification, along with the ability to drive terminated transmission lines (with
impedances as low as 50Ω), enables efficient printed circuit board design.
Figure 3. Programmable Skew Clock Driver
REF
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
LOAD
L1
Z0
LOAD
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
L2
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
LOAD
TEST
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the LVPSCB is programmed to stagger the timing of its
outputs. Each of the four groups of output pairs is programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is sent
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
Document Number: 38-07408 Rev. *D
Z0
retarding the clock signal on shorter traces, all loads receive the
clock pulse at the same time.
In Figure 3 the FB input is connected to an output with 0 ns skew
(xF1, xF0 = MID) selected. The internal PLL synchronizes the FB
and REF inputs and aligns their rising edges to make certain that
all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
Page 5 of 14
CY7B9911V
3.3V RoboClock+™
groups, and the PLL aligns the rising edges of REF and FB, you
can create wider output skews by proper selection of the xFn
inputs. For example, a +10 tU between REF and 3Qx is achieved
by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 =
MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews
to +6 tU, a total of +10 tU skew is realized). Many other configurations are realized by skewing both the outputs used as the FB
input and skewing the other outputs.
Figure 4. Inverted Output Connections
REF
FB
REF
FS
Figure 6. Frequency Divider Connections
REF
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
20 MHz
TEST
Figure 4 shows an example of the invert function of the LVPSCB.
In this example, the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied HIGH, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs with respect to the REF input.
By selecting the output connected to FB, you can have two
inverted and six non-inverted outputs or six inverted and two
non-inverted outputs. The correct configuration is determined by
the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs are also skewed to compensate for varying trace delays
independent of inversion on 4Q.
Figure 5. Frequency Multiplier with Skew Connections
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 5 shows the LVPSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by four and is sent back to
FB. This causes the PLL to increase its frequency until the 3Q0
and 3Q1 outputs are locked at 20 MHz, while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of phase on their rising edge. This enables
the designer to use the rising edges of the 1⁄2 frequency and 1⁄4
frequency outputs without concern for rising edge skew. The
2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80 MHz operation because that is the frequency
of the fastest output.
40 MHz
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Document Number: 38-07408 Rev. *D
20 MHz
80 MHz
FB
REF
FS
4F0
4F1
4Q0
4Q1
10 MHz
3F0
3F1
2F0
2F1
3Q0
3Q1
5 MHz
1F0
1F1
TEST
1Q0
1Q1
2Q0
2Q1
20 MHz
Figure 6 shows the LVPSCB in a clock divider application. 2Q0
is sent back to the FB input and programmed for zero skew. 3Qx
is programmed to divide by four. 4Qx is programmed to divide by
two. Note that the falling edges of the 4Qx and 3Qx outputs are
aligned. This enables use of the rising edges of the 1⁄2 frequency
and 1⁄4 frequency without concern for skew mismatch. The 1Qx
outputs are programmed to zero skew and are aligned with the
2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15 to 30 MHz range, since the highest
frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase,
but still is aligned within the skew specification.
The divided outputs offer a zero delay divider for portions of the
system that divide the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature, an
external divider is added, and the propagation delay of the
divider adds to the skew between the different clock signals.
These divided outputs, coupled with the Phase Locked Loop,
allow the LVPSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable
Page 6 of 14
CY7B9911V
3.3V RoboClock+™
frequency, while still maintaining the low skew characteristics of
and four or divide by two (and four) at the same time. This shifts
the clock driver. The LVPSCB performs all of the functions
its outputs over a wide range or maintain zero skew between
described in this section at the same time. It can multiply by two
selected outputs.
Figure 7. Multi-Function Clock Driver
REF
LOAD
Z0
110 MHz
INVERTED
FB
REF
FS
27.5 MHz
DISTRIBUTION
CLOCK
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
LOAD
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
27.5 MHz
Z0
LOAD
110 MHz
ZERO SKEW
110 MHz
SKEWED –2.273 ns (–4tU)
Z0
LOAD
Z0
Figure 8. Board-to-Board Clock Distribution
LOAD
REF
Z0
L1
FB
SYSTEM
CLOCK
REF
FS
4F0
4F1
LOAD
L2
Z0
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
LOAD
L3
2Q0
2Q1
Z0
L4
TEST
Z0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
Figure 8 shows the CY7B9911V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulates
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Document Number: 38-07408 Rev. *D
Page 7 of 14
CY7B9911V
3.3V RoboClock+™
Maximum Ratings
Output Current into Outputs (LOW)............................. 64 mA
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
Static Discharge Voltage........................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 10%
Commercial
DC Input Voltage ............................................–0.5V to +7.0V
Electrical Characteristics
Over the Operating Range[5]
Parameter
Description
Test Conditions
CY7B9911V
Min
Unit
Max
VOH
Output HIGH Voltage
VCC = Min, IOH = –18 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 35 mA
VIH
Input HIGH Voltage (REF and FB inputs only)
VIL
Input LOW Voltage (REF and FB inputs only)
VIHH
Three Level Input HIGH Voltage (Test, FS,
xFn)[5]
Min ≤ VCC ≤ Max
VIMM
Three Level Input MID Voltage (Test, FS,
xFn)[5]
Min ≤ VCC ≤ Max
0.47 * VCC 0.53 * VCC
VILL
Three Level Input LOW Voltage (Test, FS,
xFn)[5]
Min ≤ VCC ≤ Max
IIH
Input HIGH Leakage Current (REF and FB
inputs only)
VCC = Max, VIN = Max
IIL
Input LOW Leakage Current (REF and FB
inputs only)
VCC = Max, VIN = 0.4V
IIHH
Input HIGH Current (Test, FS, xFn)
VIN = VCC
2.4
V
0.45
V
VCC
V
–0.5
0.8
V
0.87 * VCC
VCC
V
2.0
0.0
V
0.13 * VCC
V
20
μA
μA
–20
200
μA
IIMM
Input MID Current (Test, FS, xFn)
VIN = VCC/2
50
μA
IILL
Input LOW Current (Test, FS, xFn)
VIN = GND
–200
μA
IOS
Short Circuit
Current[7]
VCC = MAX, VOUT = GND (25° only)
–200
mA
ICCQ
Operating Current Used by Internal Circuitry
VCCN = VCCQ = Max, All Com’l
Input Selects Open
Mil/Ind
95
mA
ICCN
Output Buffer Current per Output Pair[8]
VCCN = VCCQ = Max,
IOUT = 0 mA Input Selects Open, fMAX
19
mA
PD
Power Dissipation per Output Pair[9]
VCCN = VCCQ = Max,
IOUT = 0 mA Input Selects Open, fMAX
104
mW
–50
100
Notes
5. For more information see Group A subgroup testing information.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
7. CY7B9911V must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
8. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9911V: ICCN = [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
9. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the
load circuit:
PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1. (See note 8 for variable definition.)
Document Number: 38-07408 Rev. *D
Page 8 of 14
CY7B9911V
3.3V RoboClock+™
Capacitance
Tested initially and after any design or process changes that may affect these parameters.[10]
Parameter
CIN
Description
Test Conditions
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max
Unit
10
pF
Note
10. Applies to REF and FB inputs only.
AC Test Loads and Waveforms
Figure 9. AC Test Loads and Waveforms
VCC
R1
CL
R2
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
R1=100
R2=100
CL = 30 pF
(Includes fixture and probe capacitance)
2.0V
Vth =1.5V
0.8V
≤1ns
TTL AC Test Load
≤1ns
TTL Input Test Waveform
Switching Characteristics – 5 Option
Over the Operating Range [2, 11]
Parameter
fNOM
CY7B9911V-5
Description
Operating Clock
Frequency in MHz
Min
Typ
Max
FS = LOW[1, 2]
15
30
FS = MID[1, 2]
25
50
40
110
FS = HIGH[1, 2 , 3]
Unit
MHz
tRPWH
REF Pulse Width HIGH
5.0
tRPWL
REF Pulse Width LOW
5.0
tU
Programmable Skew Unit
tSKEWPR
Zero Output Matched-Pair Skew (XQ0, XQ1)[13, 14]
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs)[13, 15]
0.25
0.5
ns
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[13, 17]
0.6
0.7
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[13, 17]
0.5
1.0
ns
0.5
0.7
ns
0.5
1.0
ns
ns
ns
See Table 1
Outputs)[17, 17]
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different Class
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[13, 17]
Skew[12, 18]
tDEV
Device-to-Device
1.25
ns
tPD
Propagation Delay, REF Rise to FB Rise
–0.5
0.0
+0.5
ns
tODCV
Output Duty Cycle Variation[19]
–1.0
0.0
+1.0
ns
tPWH
Output HIGH Time Deviation from 50%[20]
2.5
ns
[20]
tPWL
Output LOW Time Deviation from 50%
3
ns
tORISE
Output Rise Time[20, 21]
0.15
1.0
1.5
ns
tOFALL
Output Fall Time[20, 21]
0.15
1.0
1.5
ns
tLOCK
PLL Lock Time[22]
0.5
ms
tJR
Cycle-to-Cycle Output
Jitter
Document Number: 38-07408 Rev. *D
RMS[12]
25
ps
Peak-to-Peak[12]
200
ps
Page 9 of 14
CY7B9911V
3.3V RoboClock+™
Switching Characteristics – 7 Option
Over the Operating Range[2, 11]
Parameter
fNOM
CY7B9911V-7
Description
Operating Clock
Frequency in MHz
Min
Typ
Max
FS = LOW[1, 2]
15
30
FS = MID[1, 2]
25
50
40
110
FS = HIGH[1, 2 , 3]
Unit
MHz
tRPWH
REF Pulse Width HIGH
5.0
tRPWL
REF Pulse Width LOW
5.0
tU
Programmable Skew Unit
tSKEWPR
Zero Output Matched Pair Skew (XQ0, XQ1)[13, 14]
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs)[13, 15]
0.3
0.75
ns
0.6
1.0
ns
1.0
1.5
ns
0.7
1.2
ns
1.2
1.7
ns
ns
ns
See Table 1
Outputs)[13, 17]
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same Class
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[13, 17]
Outputs)[13, 17]
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different Class
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[13, 17]
Skew[12, 18]
tDEV
Device-to-Device
1.65
ns
tPD
Propagation Delay, REF Rise to FB Rise
–0.7
0.0
+0.7
ns
tODCV
Output Duty Cycle Variation[19]
–1.2
0.0
+1.2
ns
tPWH
Output HIGH Time Deviation from 50%[20]
3
ns
tPWL
Output LOW Time Deviation from
50%[20]
3.5
ns
tORISE
Output Rise Time[20, 21]
0.15
1.5
2.5
ns
tOFALL
Output Fall Time[20, 21]
0.15
1.5
2.5
ns
tLOCK
PLL Lock Time[22]
0.5
ms
tJR
Cycle-to-Cycle Output
Jitter
RMS[12]
Peak[12]
100
25
ps
200
ps
Notes
11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading
as shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded
with 30 pF and terminated with 50Ω to VCC/2 (CY7B9911V).
14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
16. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in
Divide-by-2 or Divide-by-4 mode).
18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
20. Specified with outputs loaded with 30 pF for the CY7B9911V-5 and -7 devices. Devices are terminated through 50Ω to VCC/2.tPWH is measured at 2.0V. tPWL
is measured at 0.8V.
21. tORISE and tOFALL measured between 0.8V and 2.0V.
22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07408 Rev. *D
Page 10 of 14
CY7B9911V
3.3V RoboClock+™
AC Timing Diagrams
tREF
tRPWL
tRPWH
REF
tODCV
tPD
tODCV
FB
tJR
Q
tSKEWPR,
tSKEW0,1
tSKEWPR,
tSKEW0,1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3,4
tSKEW3,4
tSKEW3,4
REF DIVIDED BY 2
tSKEW1,3, 4
tSKEW2,4
REF DIVIDED BY 4
Document Number: 38-07408 Rev. *D
Page 11 of 14
CY7B9911V
3.3V RoboClock+™
Ordering Information
Accuracy (ps)
Ordering Code
Package Type
Operating
Range
500
CY7B9911V-5JC
32-Pb Plastic Leaded Chip Carrier
Commercial
500
CY7B9911V-5JCT
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
Commercial
700
CY7B9911V-7JC[23]
32-Pb Plastic Leaded Chip Carrier
Commercial
700
CY7B9911V-7JCT[23]
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
Commercial
CY7B9911V-5JXC
32-Pb Plastic Leaded Chip Carrier
Commercial
500
CY7B9911V-5JXCT
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
Commercial
700
CY7B9911V-7JXC[23]
32-Pb Plastic Leaded Chip Carrier
Commercial
700
CY7B9911V-7JXCT[23]
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
Commercial
Pb-Free
500
Note
23. Parts not recommended for the new design.
Document Number: 38-07408 Rev. *D
Page 12 of 14
CY7B9911V
3.3V RoboClock+™
Package Diagram
Figure 10. 32-Pin Plastic Leaded Chip Carrier J65
51-85002-*B
Document Number: 38-07408 Rev. *D
Page 13 of 14
CY7B9911V
3.3V RoboClock+™
Document History Page
Document Title: CY7B9911V 3.3V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer
Document Number: 38-07408
REV.
ECN NO.
Issue Date
Orig. of
Change
**
114350
3/20/02
DSG
Change from Specification number: 38-00765 to 38-07408
*A
299713
See ECN
RGL
Added Tape and Reel and Pb-free Devices in the Ordering Information table
Added 100 ps typical value for jitter (peak)
RGL
Minor Change: Added a note in ordering table that Pb-free is in Pure Sn
Description of Change
*B
404630
See ECN
*C
1199925
See ECN KVM/AESA Added Note 23: Parts not recommended for the new design in Ordering
Information table
*D
1286064
See ECN
AESA
Change status to final
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07408 Rev. *D
Revised June 20, 2007
Page 14 of 14
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. RoboClock+ is a trademark of Cypress
Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.