CY7B9945V RoboClock® High-Speed Multi-Phase PLL Clock Buffer High-Speed Multi-Phase PLL Clock Buffer Features Functional Description ■ 500 ps max Total Timing Budget (TTB™) window The CY7B9945V high-speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer and communication systems. ■ 24 MHz–200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL outputs driving 50 terminated lines ■ Dedicated feedback output ■ Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns ■ 3.3 V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable Reference Inputs ■ Multiply or Divide Ratios of 1 through 6, 8, 10, and 12 ■ Individual Output Bank Disable ■ Output High Impedance Option for Testing Purposes ■ Integrated Phase Locked Loop (PLL) with Lock Indicator ■ Low Cycle-cycle jitter (<100 ps peak-peak) ■ 3.3 V Operation ■ Industrial Temperature Range: –40 °C to +85 °C ■ 52-pin 1.4 mm TQFP package The device features a guaranteed maximum TTB window specifying all occurrences of output clocks. This includes the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. Ten configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in two banks of four and six outputs. These banks enable a divide function of 1 to 12, with phase adjustments in 625 ps–1300 ps increments up to ±10.4 ns. The dedicated feedback output enables divide-by functionality from 1 to 12 and limited phase adjustments. However, if needed, any one of the ten outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerant feature that enables smooth change over to a secondary clock source when the primary clock source is not in operation. The reference inputs and feedback inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout. For a complete list of related documentation, click here. Logic Block Diagram FS 3 REFA+ REFALO C K REFB+ PLL REFBREFSEL FBK MODE FBF0 3 FBDS0 3 FBDS1 3 1F0 3 1F1 3 1D S0 3 1D S1 3 1F2 3 1F3 3 D iv id e and Phase S e le c t QF 1Q 0 1Q 1 D iv id e and Phase S e le c t 1Q 2 1Q 3 D IS 1 2Q 0 2F0 3 2F1 3 2D S 0 3 2D S1 3 2Q 1 D iv id e and Phase S e le c t 2Q 2 2Q 3 2Q 4 2Q 5 D IS 2 Cypress Semiconductor Corporation Document Number: 38-07336 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 3, 2016 CY7B9945V RoboClock® Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 4 Block Diagram Description .............................................. 5 Time Unit Definition ..................................................... 5 Divide and Phase Select Matrix .................................. 6 Output Disable Description .......................................... 8 Lock Detect Output Description ................................... 8 Factory Test Mode Description ................................... 8 Safe Operating Zone ................................................... 8 Absolute Maximum Conditions ....................................... 9 Operating Range ............................................................... 9 Electrical Characteristics ................................................. 9 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 AC Test Loads and Waveforms ..................................... 10 Switching Characteristics .............................................. 11 Document Number: 38-07336 Rev. *M AC Timing Diagram ........................................................ 13 Ordering Information ...................................................... 14 Ordering Code Definitions ......................................... 14 Package Diagram ............................................................ 15 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC®Solutions ....................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY7B9945V RoboClock® Pinouts REFA+ VCCQ FBK GND QF VCCN 1Q1 VCCN 1Q0 GND FBDS0 FBDS1 LOCK Figure 1. 52-pin TQFP pinout 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 Document Number: 38-07336 Rev. *M REFAREFSEL REFBREFB+ 1F2 FS G ND 1Q 2 VCCN 1Q 3 FBF0 1F0 VCCQ DIS2 MODE GND GND 2Q5 VCCN 2Q4 DIS1 1F1 1F3 VCCQ GND CY7B9945V 1DS0 2F1 2F0 2DS1 G ND 2Q 0 VCCN 2Q 1 2Q 2 VCCN 2Q 3 G ND 1DS1 2DS0 Page 3 of 18 CY7B9945V RoboClock® Pin Definitions Pin Name I/O 34 FS Input 40, 39, 36, 37 REFA+, REFA-, REFB+, REFB- Input 38 REFSEL Input LVTTL Reference Select Input. The REFSEL input controls the configuration of reference input When LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB pair as the reference input. This input has an internal pull down. 42 FBK Input LVTTL Feedback Input Clock. The PLL operates such that the rising edges of the reference and feedback signals are aligned in phase and frequency. This pin provides the clock output QF feedback to the phase detector. 28, 18, 35, 17, 2, 1 1F[0:3], 2F[0:1] Input 19, 26 DIS[1:2] Input 14, 12, 13, 3 [1:2]DS[0:1] Input Three level Output Divider Function Select. Each pair determines the divider ratio Input of the respective bank of outputs. See Table 4. 29 FBF0 Input Three level Feedback Output Phase Function Select. This input determines the Input phase of the QF output. See Table 3. 50, 51 FBDS[0:1] Input Three level Feedback Output Divider Function Select. This input determines the Input divider ratio of the QF output. See Table 4. 48, 46, 32, 30, 5, 7, 8,10, 20, 22 1Q[0:3], 2Q[0:5] Output LVTTL Clock Outputs with Adjustable Phases and fNOM Divide Ratios. The output frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3] and 2F[0:1], respectively. See Table 3 and Table 4. 44 QF Output LVTTL Feedback Clock Output. This output is connected to the FBK input. The output frequency and phase are determined by FBDS[0:1] and FBF0, respectively. See Table 3 and Table 4. 52 LOCK Output LVTTL PLL Lock Indicator. When HIGH, this output indicates that the internal PLL is locked to the reference signal. When LOW, it indicates that the PLL is attempting to acquire lock 25 MODE Input 6, 9, 21, 31, 45, 47 VCCN PWR Power Supply for the Output Buffers 16, 27, 41 VCCQ PWR Power Supply for the Internal Circuitry 4, 11, 15, 23, 24, 33, 43, 49 GND PWR Device Ground Document Number: 38-07336 Rev. *M Type Description Three level Frequency Select. This input must be set according to the nominal Input frequency (fNOM). See Table 1. LVTTL/ Reference Inputs. These inputs can operate as differential PECL or LVDIFF single-ended TTL reference inputs to the PLL. When operating as a single-ended LVTTL input, the complementary input is left open. Three level Output Phase Function Select. Each pair determines the phase of the Input respective bank of outputs. See Table 3. LVTTL Output Disable. Each input controls the state of the respective output bank. When HIGH, the output bank is disabled to HOLD-OFF or High-Z state; the disable state is determined by MODE. When LOW, outputs 1Q[0:3] and 2Q[0:5] are enabled. See Table 5. Three level This pin determines the clock outputs’ disable state. When this input Input is HIGH, the clock outputs disables to high impedance state (High-Z). When this input is LOW, the clock outputs disables to HOLD-OFF mode. When in MID, the device enters factory test mode. Page 4 of 18 CY7B9945V RoboClock® Block Diagram Description Table 1. Frequency Range Select The PLL adjusts the phase and the frequency of its output signal to minimize the delay between the reference (REFA/B+, REFA/B-) and the feedback (FB) input signals. The CY7B9945V has a flexible REF input scheme. These inputs enable the use of either differential LVPECL or single ended LVTTL inputs. To configure as single ended LVTTL inputs, leave the complementary pin open (internally pulled to 1.5 V), then the other input pin is used as a LVTTL input. The REF inputs are also tolerant to hot insertion. The REF inputs are changed dynamically. When changing from one reference input to the other reference input of the same frequency, the PLL is optimized to ensure that the clock outputs period is not less than the calculated system budget (tMIN = tREF (nominal reference period) – tCCJ (cycle-cycle jitter) – tPDEV (max. period deviation)) while reacquiring lock. The FS control pin setting determines the nominal operational frequency range of the divide by one output (fNOM) of the device. fNOM is directly related to the VCO frequency. The FS setting for the device is shown in Table 1. For CY7B9945V, the upper fNOM range extends from 96 MHz to 200 MHz. fNOM (MHz) FS LOW Min Max 24 52 MID 48 100 HIGH 96 200 Time Unit Definition Selectable skew is in discrete increments of time unit (tU). The value of a tU is determined by the FS setting and the maximum nominal output frequency. The equation determines the tU value as follows: tU = 1/(fNOM*N). N is a multiplication factor that is determined by the FS setting. fNOM is nominal frequency of the device. N is defined in Table 2. Table 2. N Factor Determination FS CY7B9945V N fNOM (MHz) at which tU = 1.0 ns LOW 32 31.25 MID 16 62.5 HIGH 8 125 Note 1. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID). Document Number: 38-07336 Rev. *M Page 5 of 18 CY7B9945V RoboClock® Divide and Phase Select Matrix Table 3. Output Phase Select (continued) The Divide Select Matrix is comprised of three independent banks: two of clock outputs and one for feedback. The Phase Select Matrix, enables independent phase adjustments on 1Q[0:1], 1Q[2:3] and 2Q[0:5]. The frequency of 1Q[0:3] is controlled by 1DS[0:1] while the frequency of 2Q[0:5] is controlled by 2DS[0:1]. The phase of 1Q[0:1] is controlled by 1F[0:1], that of 1Q[2:3] is controlled by 1F[2:3] and that of 2Q[0:5] is controlled by 2F[0:1]. The high fanout feedback output buffer (QF) connects to the feedback input (FBK).This feedback output has one phase function select input (FBF0) and two divider function selects FBDS[0:1]. Control Signal Output Phase Function HIGH MID +3tU +3tU +7tU N/A HIGH HIGH +4tU +4tU +8tU +4tU Table 4. Output Divider Select Control Signal [1:2]DS1 [1:2]DS0 and FBDS1 and FBDS0 Output Divider Function Bank1 Bank2 Feedback The phase capabilities that are chosen by the phase function select pins are shown in Table 3. The divide capabilities for each bank are shown in Table 4. LOW LOW /1 /1 /1 LOW MID /2 /2 /2 LOW HIGH /3 /3 /3 Table 3. Output Phase Select MID LOW /4 /4 /4 MID MID /5 /5 /5 MID HIGH /6 /6 /6 HIGH LOW /8 /8 /8 HIGH MID / 10 / 10 / 10 HIGH HIGH / 12 / 12 / 12 Control Signal 1F1 1F0 1F3 1F2 2F1 Output Phase Function 1Q[0:1] 1Q[2:3] 2F0 2Q[0:5] FBF0 QF LOW LOW –4tU –4tU –8tU –4tU LOW MID –3tU –3tU –7tU N/A LOW HIGH –2tU –2tU –6tU N/A MID LOW –1tU –1tU BK1Q[0:1] N/A MID MID 0tU 0tU 0tU 0tU MID HIGH +1tU +1tU BK1Q[2:3] N/A HIGH LOW +2tU +2tU +6tU N/A Figure 2 on page 7 shows the timing relationship of programmable skew outputs. All times are measured with respect to REF with the output used for feedback programmed with 0tU skew. The PLL naturally aligns the rising edge of the FB input and REF input. If the output used for feedback is programmed to another skew position, then the whole tU matrix shifts with respect to REF. For example, if the output used for feedback is programmed to shift –4tU, then the whole matrix is shifted forward in time by 4tU. Thus an output programmed with 4tU of skew gets effectively be skewed 8tU with respect to REF. Note 2. The level set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided. Document Number: 38-07336 Rev. *M Page 6 of 18 CY7B9945V RoboClock® U U U U U U U U t 0 +1t t 0 +2t t 0 +3t t 0 +4t t 0 +5t t 0 +6t t 0 +7t t 0 +8t t0 t 0 – 1t U t 0 – 2t U t 0 – 3t U t 0 – 4t U t 0 – 5t U t 0 – 6t U t 0 – 7t U t 0 – 8t U Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output  FBInput REFInput 1F[1:0] 1F[3:2] 2F[1:0] (N/A) LL –8tU (N/A) LM –7tU (N/A) LH –6tU LL (N/A) –4tU LM (N/A) –3tU LH (N/A) –2tU ML (N/A) –1tU MM MM 0t U MH (N/A) +1t U HL (N/A) +2t U HM (N/A) +3t U HH (N/A) +4t U (N/A) HL +6t U (N/A) HM +7t U (N/A) HH +8t U Note 3. BK1Q denotes following the skew setting of indicated Bank1 outputs. Document Number: 38-07336 Rev. *M Page 7 of 18 CY7B9945V RoboClock® Output Disable Description The output of each output bank can be independently put into a HOLD OFF or high impedance state. The combination of the MODE and DIS[1:2] inputs determines the clock outputs’ state for each bank. When the DIS[1:2] is LOW, the outputs of the corresponding banks are enabled. When DIS[1:2] is HIGH, the outputs for that bank are disabled to a high impedance (HI-Z) or HOLD OFF state. Table 5 defines the disabled outputs functions. The HOLD OFF state is a power saving feature. An output bank is disabled to the HOLD OFF state in a maximum of six output clock cycles from the time the disable input is HIGH. When disabled to the HOLD OFF state, outputs are driven to a logic LOW state on their falling edges. This makes certain that the output clocks are stopped without a glitch. When a bank of outputs is disabled to HI-Z state, the respective bank of outputs go High-Z immediately. Table 5. DIS[1:2] Functionality PLL disconnected; input level supplied to the reference input is used in place of the PLL output. In TEST mode the FB input is tied LOW. All functions of the device remain operational in factory test mode except the internal PLL and output bank disables. The MODE input is designed as a static input. Dynamically toggling this input from LOW to HIGH temporarily causes the device to go into factory test mode (when passing through the MID state). When in the test mode, the device is reset to a deterministic state by driving the DIS2 input HIGH. Doing so disables all outputs and, after the selected reference clock pin has five positive transitions, all internal finite state machines (FSM) are set at a deterministic state. The states depend on the configurations of the divide, skew and frequency selection. All clock outputs stay in High-Z mode and all FSMs stay in the deterministic state until DIS2 is deasserted. This causes the device to reenter factory test mode. Safe Operating Zone MODE DIS[1:2] 1Q[0:3], 2Q[0:5] HIGH/LOW LOW ENABLED HIGH HIGH HI-Z LOW HIGH HOLD-OFF MID X FACTORY TEST Lock Detect Output Description The LOCK detect output indicates the lock condition of the integrated PLL. Lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. Phase error is declared when the phase difference between the two inputs is greater than the specified device propagation delay limit tPD. Figure 3 shows the operating condition of the device not exceeding its allowable maximum junction temperature of 150°C. Figure 3 shows the maximum number of outputs that can operate at 185 MHz (with 25 pF load and no air flow) or 200 MHz (with 10-pF load and no air flow) at various ambient temperatures. At the limit line, all other outputs are configured to divide-by-two (i.e., operating at 92.5 MHz) or lower frequencies. The device operates below maximum allowable junction temperature of 150°C when its configuration (with the specified constraints) falls within the shaded region (safe operating zone). Figure 3 shows that at 85°C, the maximum number of outputs that can operate at 200 MHz is 6. Figure 3. Typical Safe Operating Zone When in the locked state, after four or more consecutive feedback clock cycles with phase errors, the LOCK output is forced LOW to indicate out-of-lock state. If the feedback clock is removed after LOCK has gone HIGH, a “Watchdog” circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting LOCK LOW. This time out period is based upon a divided down reference clock. This assumes that there is activity on the selected REF input. If there is no activity on the selected REF input then the LOCK detect pin does not accurately reflect the state of the internal PLL. Factory Test Mode Description The device enters factory test mode when the MODE is driven to MID. In factory test mode, the device operates with its internal Document Number: 38-07336 Rev. *M 100 Ambient Temperature (C) When in the out-of-lock state, 32 consecutive phase errorless feedback clock cycles are required to enable the LOCK output to indicate lock condition (LOCK = HIGH). Typical Safe Operating Zone (25-pF Load, 0-m/s air flow) 95 90 85 80 75 70 Safe Operating Zone 65 60 55 50 2 4 6 8 10 Number of Outputs at 185 MHz Page 8 of 18 CY7B9945V RoboClock® Absolute Maximum Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –40 C to +125 C Ambient Temperature with Power Applied .................................. –40 C to +125 C Supply Voltage to Ground Potential .............–0.5 V to +4.6 V DC Input Voltage ................................ –0.3 V to VCC + 0.5 V Output Current into Outputs (LOW) ............................ 40 mA Static Discharge Voltage (MIL-STD-883, Method 3015) ................................. > 1100 V Latch-up Current ................................................. > ± 200 mA Operating Range Range Ambient Temperature VCC Commercial 0 °C to +70 °C 3.3 V 10% Industrial –40 °C to +85 °C 3.3 V 10% Electrical Characteristics Over the Operating Range Description LVTTL HIGH Voltage LVTTL LOW Voltage Test Conditions Min Max Unit (QF, 1Q[0:3], 2Q[0:5]) VCC = Min, IOH = –30 mA 2.4 – V LOCK IOH = –2 mA, VCC = Min 2.4 – V (QF, 1Q[0:3], 2Q[0:5]) VCC = Min, IOL= 30 mA – 0.5 V LOCK IOL= 2 mA, VCC = Min – 0.5 V –100 100 A Min < VCC < Max 2.0 VCC + 0.3 V High impedance State Leakage Current LVTTL Input HIGH LVTTL Input LOW Min. < VCC < Max. –0.3 0.8 V LVTTL VIN >VCC VCC = GND, VIN = 3.63 V – 100 A LVTTL Input HIGH Current VCC = Max, VIN = VCC – 500 A LVTTL Input LOW Current VCC = Max, VIN = GND –500 – A Min < VCC < Max 0.87 × VCC – V Min < VCC < Max 0.47 × VCC 0.53 × VCC Three level Input HIGH  Three level Input MID  Three level Input LOW Three level Input HIGH Current FS[0:2],IF[0:3],FBDS[0:1] Three level Input MID Current FS[0:2],IF[0:3],FBDS[0:1] Min < VCC < Max – 0.13 × VCC V VIN = VCC – 200 A 2F[0:1],[1:2]DS[0:1],FBFO VIN = VCC/2 2F[0:1],[1:2]DS[0:1],FBFO Three level Input LOW Current FS[0:2],IF[0:3],FBDS[0:1] V VIN = GND – 400 A –50 50 A –100 100 A –200 – A –400 – A Input Differential Voltage 400 VCC mV Highest Input HIGH Voltage 1.0 VCC V Lowest Input LOW Voltage GND VCC – 0.4 V 2F[0:1],[1:2]DS[0:1],FBFO 0.8 VCC – 0.2 V Internal Operating Current CY7B9945V VCC = Max, fMAX – 250 mA Output Current Dissipation/Pair CY7B9945V VCC = Max, CLOAD = 25 pF, RLOAD = 50 at VCC/2, fMAX – 40 mA Common Mode Range (Crossing Voltage) Notes 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. This is for non-three level inputs. Document Number: 38-07336 Rev. *M Page 9 of 18 CY7B9945V RoboClock® Capacitance Parameter CIN Description Test Conditions Input Capacitance Min Max Unit – 5 pF Test Conditions 52-pin TQFP Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 55 °C/W 16 °C/W TA = 25 °C, f = 1 MHz, VCC = 3.3 V Thermal Resistance Parameter  Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms  For LOCK output only R1 = 910 R2 = 910 CL < 30 pF For all other outputs R1 = 100 R2 = 100 CL < 25 pF to 185 MHz or 10 pF at 200 MHz (Includes fixture and probe capacitance) 3.3 V R1 OUTPUT CL R2 (a) LVTTL AC Test Load 3.3 V 2.0 V 0.8 V GND 2.0 V 0.8 V < 1 ns < 1 ns (b) TTL Input Test Waveform Notes 6. These parameters are guaranteed by design and are not tested. 7. Assumes 25 pF Maximum Load Capacitance up to 185 MHz. At 200 MHz the maximum load is 10 pF. Document Number: 38-07336 Rev. *M Page 10 of 18 CY7B9945V RoboClock® Switching Characteristics Over the Operating Range [8, 9, 10, 11, 12] Parameter Description CY7B9945V-2 CY7B9945V-5 Min Max Min Max Unit fin Clock Input Frequency 24 200 24 200 MHz fout Clock Output Frequency 24 200 24 200 MHz – 200 – 200 ps [13, 14] tSKEWPR Matched Pair Skew 2Q[2:3], 2Q[4:5] tSKEWBNK Intrabank Skew[13, 14] – 250 – 250 ps tSKEW0 Output-Output Skew (same frequency and phase, rise to rise, fall to fall) [13, 14] – 250 – 550 ps tSKEW1 Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall) [13, 14] – 250 – 650 ps tSKEW2 Output-Output Skew (all output configurations outside of tSKEW0 and tSKEW1) [12, 15] – 500 – 800 ps tCCJ1-3 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) – 150 – 150 ps PeakPeak tCCJ4-12 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) – 100 – 100 ps PeakPeak tPD Propagation Delay, REF to FB Rise –250 250 –500 500 ps TTB Total Timing Budget window (same frequency and phase) [16, 17] – 500 – 700 ps tPDDELTA Propagation Delay difference between two devices  tREFpwh tREFpwl REF input (Pulse Width , 1Q[0:1], 1Q[2:3], 2Q[0:1], – 200 – 200 ps HIGH) 2.0 – 2.0 – ns  2.0 – 2.0 – ns REF input (Pulse Width LOW) Notes 8. This is for non-three level inputs. 9. Both outputs of pair must be terminated, even if only one is being used. 10. Each package must be properly decoupled. 11. AC parameters are measured at 1.5 V, unless otherwise indicated. 12. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz. 13. Tested initially and after any design or process changes that affect these parameters. 14. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given output frequency. 15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters. 17. Rise and fall times are measured between 2.0 V and 0.8 V. 18. fNOM must be within the frequency range defined by the same FS state. Document Number: 38-07336 Rev. *M Page 11 of 18 CY7B9945V RoboClock® Switching Characteristics (continued) Over the Operating Range [8, 9, 10, 11, 12] Parameter CY7B9945V-2 Description CY7B9945V-5 Unit Min Max Min Max 0.15 2.0 0.15 2.0 ns tr/tf Output Rise/Fall Time tLOCK PLL Lock TIme From Power Up – 10 – 10 ms tRELOCK1 PLL Relock Time (from same frequency, different phase) with Stable Power Supply – 500 – 500 s tRELOCK2 PLL Re-lock Time (from different frequency, different phase) with Stable Power Supply – 1000 – 1000 s tODCV Output duty cycle deviation from 50% tPWH –1.0 1.0 –1.0 1.0 ns  – 1.5 – 1.5 ns 50% – 2.0 – 2.0 ns – 0.025 – 0.025 UI Output HIGH time deviation from 50% tPWL Output LOW time deviation from tPDEV Period deviation when changing from reference to reference  tOAZ DIS[1:2] HIGH to output high-impedance from ACTIVE [24, 25] 1.0 10 1.0 10 ns tOZA DIS[1:2] LOW to output ACTIVE from output is high impedance  0.5 14 0.5 14 ns Notes 19. tPWH is measured at 2.0 V. tPWL is measured at 0.8 V. 20. fNOM must be within the frequency range defined by the same FS state. 21. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 22. Measured at 0.5 V deviation from starting voltage. 23. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz. 24. Tested initially and after any design or process changes that affect these parameters. 25. These figures are for illustration purposes only. The actual ATE loads may vary. Document Number: 38-07336 Rev. *M Page 12 of 18 CY7B9945V RoboClock® AC Timing Diagram Figure 5. AC Timing Diagram tREFpwl tREFpwh [1:2]Q[0,2] REF t SKEWPR t SKEWPR t PWH tPD t PWL [1:2]Q[1,3] 2.0 V FB 0.8 V tCCJ1-3,4-12 Q [1:2]Q[0:3] t SKEWBNK t SKEWBNK [1:2]Q[0:3] REF TO DEVICE 1 and 2 tODCV tPD tODCV Q FB DEVICE1 tPDELTA tPDELTA t SKEW0,1 t SKEW0,1 Other Q FB DEVICE2 Document Number: 38-07336 Rev. *M Page 13 of 18 CY7B9945V RoboClock® Ordering Information Propagation Delay (ps) Max. Speed (MHz) Package Name Ordering Code Operating Range Package Type Pb-free 250 250 200 CY7B9945V-2AXC AZ52 52-pin TQFP Commercial 200 CY7B9945V-2AXCT AZ52 52-pin TQFP – Tape and Reel Commercial 200 CY7B9945V-2AXI AZ52 52-pin TQFP Industrial 200 CY7B9945V-2AXIT AZ52 52-pin TQFP – Tape and Reel Industrial Ordering Code Definitions CY XXXXXX V - 2 A X C T T = Tape and reel, Blank = Tube Temperature range: C = Commercial Pb-free, Blank = leaded 52-pin TQFP package Speed grade Operating voltage: 3.3 V Part identifier Company Code: CY = Cypress Document Number: 38-07336 Rev. *M Page 14 of 18 CY7B9945V RoboClock® Package Diagram Figure 6. 52-pin TQFP (10 × 10 × 1.4 mm) Package Outline, 51-85131 51-85131 *C Document Number: 38-07336 Rev. *M Page 15 of 18 CY7B9945V RoboClock® Acronyms Table 6. Acronyms Used in this Document Acronym FSM LVPECL LVTTL OE RMS PLL TQFP VCO Description Finite State Machine Low-Voltage Positive Emitter Coupled Logic Low-Voltage Transistor-Transistor Logic Output Enable Root Mean Square Phase Locked Loop Thin Quad Flat Pack Voltage Controlled Oscillator Document Conventions Units of Measure Table 7. Units of Measure Symbol °C dB dBc/Hz fC fF Hz KB Kbit kHz k MHz M µA µF µH µs µV Unit of Measure degrees Celsius decibel decibels relative to the carrier per Hertz femtoCoulomb femtofarad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolt Document Number: 38-07336 Rev. *M Symbol µVrms µW mA mm ms mV nA ns nV pA pF pp ppm ps sps Unit of Measure microvolts root-mean-square microwatt milliampere millimeter millisecond millivolt nanoampere nanosecond nanovolt ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation Page 16 of 18 CY7B9945V RoboClock® Document History Page Document Title: CY7B9945V RoboClock®, High-Speed Multi-Phase PLL Clock Buffer Document Number: 38-07336 Revision ECN Orig. of Change Submission Date ** 111747 CTK 03/04/02 New data sheet *A 116572 HWT 09/05/02 Added TTB Features *B 119078 HWT 10/16/02 Corrected the following items in the Electrical Characteristics table: IIIL, IIIH, IIIM specifications from: three level input pins excluding FBFO to FS[0:2], IF[0:3], FBDS[0:1] and FBFO to 2F[0:1], [1:2]DS[0:1], FBFO Common Mode Range (VCOM) from VCC to VCC–0.2 Corrected typo TQFP to LQFP in Features *C 124645 RGL 03/20/03 Corrected typo LQFP to TQFP in Features *D 128464 RGL 07/25/03 Added clock input frequency (fin) specifications in the switching characteristics table. Description of Change *E 272075 RGL See ECN Minor Change: Fixed the Typical Outputs (Fig. 1) diagram *F 1187144 KVM See ECN Updated Ordering Information table, primarily to add Pb-free devices *G 2761988 CXQ 09/10/09 Changed instances of “50W” to “50” on page 1. Changed “Pb” to “lead” in Ordering Information package type section. Added “Not recommended for new designs” note to all Pb packages. *H 2891379 KVM 03/12/2010 Added Table of Contents Updated Ordering Information table Updated Package Diagram Updated Sales, Solutions, and Legal Information *I 2905846 KVM 04/06/2010 Removed inactive part from Ordering Information table. *J 3196237 BASH 03/15/11 *K 4323331 CINM 03/27/2014 Updated Package Diagram: spec 51-85131 – Changed revision from *A to *C. Updated to new template. Completing Sunset Review. *L 4570146 CINM 11/14/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *M 5257087 PSR 05/03/2016 Changed status from Preliminary to Final. Added Thermal Resistance. Updated to new template. Document Number: 38-07336 Rev. *M Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated to new template. Page 17 of 18 CY7B9945V RoboClock® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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