TSC2007-Q1
SBAS545 – SEPTEMBER 2011
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1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire
Micro TOUCH SCREEN CONTROLLER with I2C™ Interface
Check for Samples: TSC2007-Q1
FEATURES
1
•
•
•
•
•
23
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
4-Wire Touch Screen Interface
Single 1.2 V to 3.6 V Supply/Reference
Ratiometric Conversion
Effective Throughput Rate:
– Up to 20 kHz (8-Bit) or 10 kHz (12-Bit)
Preprocessing to Reduce Bus Activity
I2C Interface Supports:
– Standard, Fast, and High-Speed Modes
Simple, Command-Based User Interface:
– TSC2003-Q1 Compatible
– 8- or 12-Bit Resolution
On-Chip Temperature Measurement
Touch Pressure Measurement
Digital Buffered PENIRQ
On-Chip, Programmable PENIRQ Pull-Up
Auto Power-Down Control
•
•
•
Low Power:
– 32.24 μA at 1.2 V, Fast Mode, 8.2 kHz Eq
Rate
– 39.31 μA at 1.8 V, Fast Mode, 8.2 kHz Eq
Rate
– 53.32 μA at 2.7 V, Fast Mode, 8.2 kHz Eq
Rate
Enhanced ESD Protection:
– ±8 kV HBM
– ±1 kV CDM
– ±25 kV Air Gap Discharge
– ±15 kV Contact Discharge
5 x 6.4 TSSOP-16 Package
U.S. Patent NO. 6246394; other patents pending.
APPLICATIONS
•
•
Media Players
Multiscreen Touch Control Systems
DESCRIPTION
The TSC2007-Q1 is a very low-power touch screen controller designed to work with power-sensitive, handheld
applications that are based on an advanced low-voltage processor. It works with a supply voltage as low as 1.2V,
which can be supplied by a single-cell battery. It contains a complete, ultra-low power, 12-bit, analog-to-digital
(A/D) resistive touch screen converter, including drivers and the control logic to measure touch pressure.
In addition to these standard features, the TSC2007-Q1 offers preprocessing of the touch screen measurements
to reduce bus loading, thus reducing the consumption of host processor resources that can then be redirected to
more critical functions.
The TSC2007-Q1 supports an I2C serial bus and data transmission protocol in all three defined modes: standard,
fast, and high-speed. It offers programmable resolution of 8 or 12 bits to accommodate different screen sizes and
performance needs.
The TSC2007-Q1 is available in a 16-pin TSSOP package. The TSC2007-Q1 is characterized for the –40°C to
+85°C industrial temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
2
2
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TSC2007-Q1
SBAS545 – SEPTEMBER 2011
www.ti.com
VDD/REF
X+
XY+
Y-
Touch
Screen
Drivers
Interface
Mux
Preprocessing
PENIRQ
SAR
ADC
TEMP
AUX
I2C
Serial
Interface
and
Control
SCL
SDA
A[0:1]
Internal
Clock
GND
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
–40°C to +85°C
(1)
PACKAGE
TSSOP – PW
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSC2007IPWRQ1
TS2007I
Reel of 2000
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
VALUE
UNIT
Analog input X+, Y+, AUX to GND
–0.4 to VDD + 0.1
V
Analog input X–, Y– to GND
–0.4 to VDD + 0.1
V
–0.3 to +5
V
Digital input voltage to GND
–0.3 to VDD + 0.3
V
Digital output voltage to GND
–0.3 to VDD + 0.3
V
Power dissipation
(TJ Max - TA)/θJA
Voltage
Voltage range
Thermal impedance, θJA
VDD/REF pin to GND
86
°C/W
Operating free-air temperature range, TA
–40 to +85
°C
Storage temperature range, TSTG
–65 to +150
°C
+150
°C
Vapor phase (60 sec)
+215
°C
Infrared (15 sec)
+220
°C
IEC contact discharge (2)
X+, X–, Y+, Y–
±15
kV
IEC air discharge (2)
X+, X–, Y+, Y–
±25
kV
TSSOP package
Junction temperature, TJ Max
Lead temperature
(1)
(2)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXILIARY ANALOG INPUT
Input voltage range
0
VDD
Input capacitance
V
12
–1
Input leakage current
pF
+1
μA
12
Bits
A/D CONVERTER
Resolution
Programmable: 8 or 12 bits
No missing codes
12-bit resolution
11
Bits
±1.5
LSB (1)
VDD = 1.8V
–1.2
LSB
VDD = 3.0V
–3.1
LSB
VDD = 1.8V
0.7
LSB
VDD = 3.0V
0.1
LSB
TA = +25°C, VDD = 1.8V, command '1011' set '0000'
51
kΩ
TA = +25°C, VDD = 1.8V, command '1011' set '0001'
90
kΩ
Y+, X+
6
Ω
Y–, X–
5
Integral linearity
Offset error
Gain error
TOUCH SENSORS
PENIRQ pull-up resistor, RIRQ
Switch
on-resistance
Switch drivers drive current (2)
100ms duration
Ω
50
mA
INTERNAL TEMPERATURE SENSOR
–40
Temperature range
°C
+85
VDD = 3V
1.94
°C/LSB
VDD = 1.6V
1.04
°C/LSB
VDD = 3V
0.35
°C/LSB
VDD = 1.6V
0.19
°C/LSB
VDD = 3V
±2
°C/LSB
VDD = 1.6V
±2
°C/LSB
VDD = 3V
±3
°C/LSB
VDD = 1.6V
±3
°C/LSB
VDD = 1.2V
3.19
MHz
VDD = 1.8V
3.66
MHz
VDD = 2.7V
3.78
MHz
VDD = 3.6V
3.82
MHz
VDD = 1.2V
1.6
MHz
VDD = 1.8V
1.83
MHz
VDD = 2.7V
1.88
MHz
VDD = 3.6V
1.91
MHz
VDD = 1.6V
0.0056
%/°C
VDD = 3.0V
0.012
%/°C
Differential
method (3)
Resolution
TEMP1 (4)
Differential
method (3)
Accuracy
TEMP1 (4)
INTERNAL OSCILLATOR
8-Bit
Internal clock frequency, fCCLK
12-Bit
Frequency drift
(1)
(2)
(3)
(4)
LSB means Least Significant Bit. With VDD/REF pin = +1.6V, one LSB is 391 μV.
Specified by design, but not tested. Exceeding 50 mA source current may result in device degradation.
Difference between TEMP1 and TEMP2 measurement; no calibration necessary.
Temperature drift is –2.1 mV/°C.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
VIL
Logic level
IIL
CIN
1.2V ≤ VDD < 1.6V
0.7 × VDD
VDD + 0.3
V
1.6V ≤ VDD ≤ 3.6V
0.7 × VDD
VDD + 0.3
V
1.2V ≤ VDD < 1.6V
–0.3
0.2 × VDD
V
1.6V ≤ VDD ≤ 3.6V
–0.3
0.3 × VDD
V
–1
1
μA
SCL and SDA pins
(5)
10
pF
VOH
IOH = 2 TTL loads
VDD – 0.2
VDD
V
VOL
IOL = 2 TTL loads
0
0.2
V
1
μA
10
pF
ILEAK
COUT
SCL and SDA pins
–1
Floating output
(5)
Floating output
Data format
Straight binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage, VDD
Specified performance
VDD = 1.2V
Quiescent supply current
(VDD with sensor off)
12-bit Fast mode
(clock = 400kHz)
PD[1:0] = 0,0
VDD = 1.8V
VDD = 2.7V
Power down supply current
1.2
32.56k eq rate
128
8.2k eq rate
3.6
V
190
μA
μA
32.24
34.42k eq rate
165
8.2k eq rate
39.31
34.79k eq rate
226.2
8.2k eq rate
53.32
Not addressed, SCL = SDA = 1
0
240
μA
μA
335
μA
μA
0.8
μA
POWER ON/OFF SLOPE REQUIREMENTS (5)
VDD off ramp
VDD off time
VDD on ramp
(5)
4
TA = –40°C to +85°C
2
kV/s
TA = –40°C to +85°C, VDD = 0V
1.2
TA = –20°C to +85°C, VDD = 0V
0.3
s
TA = –40°C to +85°C
12
kV/s
s
Not production tested. Specified by design.
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PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(TOP VIEW)
VDD/REF
1
16 AUX
X+
2
15 NC
Y+
3
14 A0
X-
4
13 A1
TSC2007
Y-
5
12 SCL
GND
6
11 SDA
NC
7
10 PENIRQ
NC
8
9
NC
PIN ASSIGNMENTS
PIN NO.
PIN NAME
I/O
A/D
1
VDD/REF
2
DESCRIPTION
X+
I
A
X+ channel input
3
Y+
I
A
Y+ channel input
4
X–
I
A
X– channel input
5
Y–
I
A
Y– channel input
6
GND
7
NC
No connection
8
NC
No connection
9
NC
10
PENIRQ
O
D
Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low.
11
SDA
I/O
D
Serial data I/O
12
SCL
I/O
D
Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to delay a bus
transfer.
13
A1
I
D
Address input bit 1
14
A0
I
D
Address input bit 0
15
NC
16
AUX
I
A
Supply voltage and external reference input
Ground
No connection
No connection
Auxiliary channel input
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TIMING INFORMATION
SDA
tSU, STA
tSU, DAT
tBUF
tHD, STA
tHD, DAT
tLOW
SCL
tSU, STO
tHIGH
tHD, STA
tR
tF
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Detailed I/O Timing
TIMING REQUIREMENTS: I2C Standard Mode (SCL = 100kHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE STANDARD MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
kHz
SCL clock frequency
fSCL
0
Bus free time between a STOP and START condition
tBUF
4.7
μs
Hold time (repeated) START condition
tHD, STA
4.0
μs
Low period of SCL clock
tLOW
4.7
μs
High period of the SCL clock
tHIGH
4.0
μs
Setup time for a repeated START condition
tSU, STA
4.7
Data hold time
tHD, DAT
0
Data setup time
tSU, DAT
250
Rise time for both SDA and SCL signals (receiving)
tR
Cb = total bus capacitance
1000
ns
Fall time for both SDA and SCL signals (receiving)
tF
Cb = total bus capacitance
300
ns
Fall time for both SDA and SCL signals (transmitting)
tF
Cb = total bus capacitance
250
ns
Setup time for STOP condition
tSU, STO
Capacitive load for each bus line
Cb
400
pF
Cycle time
Effective throughput
Equivalent rate = effective throughput × 7
6
μs
3.45
μs
ns
μs
4.0
Cb = total capacitance of one bus line in pF
μs
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
434.7
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
570.9
8 bits
VDD = 1.8V
2.3
kSPS
12 bits
VDD = 1.8V
1.75
kSPS
8 bits
VDD = 1.8V
16.1
kHz
12 bits
VDD = 1.8V
12.26
kHz
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μs
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TIMING REQUIREMENTS: I2C Fast Mode (SCL = 400kHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
400
kHz
SCL clock frequency
fSCL
0
Bus free time between a STOP and START condition
tBUF
1.3
μs
Hold time (repeated) START condition
tHD, STA
0.6
μs
Low period of SCL clock
tLOW
1.3
μs
High period of the SCL clock
tHIGH
0.6
μs
Setup time for a repeated START condition
tSU, STA
0.6
Data hold time
tHD, DAT
0
Data setup time
tSU, DAT
100
Rise time for both SDA and SCL signals (receiving)
tR
Cb = total bus capacitance
20+0.1×Cb
300
ns
Fall time for both SDA and SCL signals (receiving)
tF
Cb = total bus capacitance
20+0.1×Cb
300
ns
Fall time for both SDA and SCL signals (transmitting)
tF
Cb = total bus capacitance
20+0.1×Cb
250
Setup time for STOP condition
tSU, STO
Capacitive load for each bus line
Cycle time
Effective throughput
Equivalent rate = effective throughput × 7
Cb
μs
0.9
μs
ns
ns
μs
0.6
Cb = total capacitance of one bus line in pF
400
pF
μs
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
134.7
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
203.4
μs
8 bits
VDD = 1.8V
7.42
kSPS
12 bits
VDD = 1.8V
4.92
kSPS
8 bits
VDD = 1.8V
51.97
kHz
12 bits
VDD = 1.8V
34.42
kHz
TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 1.7MHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
UNIT
1.7
MHz
fSCL
Hold time (repeated) START condition
tHD, STA
160
ns
Low period of SCL clock
tLOW
320
ns
High period of the SCL clock
tHIGH
120
ns
Setup time for a repeated START condition
tSU, STA
160
Data hold time
tHD, DAT
0
Data setup time
tSU, DAT
10
Rise time for SCL signal (receiving)
tR
Cb = total bus capacitance
20
80
ns
Rise time for SDA signal (receiving)
tR
Cb = total bus capacitance
20
160
ns
Fall time for SCL signal (receiving)
tF
Cb = total bus capacitance
20
80
ns
Fall time for SDA signal (receiving)
tF
Cb = total bus capacitance
20
160
ns
Fall time for both SDA and SCL signals (transmitting)
tF
Cb = total bus capacitance
20
160
ns
Setup time for STOP condition
tSU, STO
Capacitive load for each bus line
Cb
400
pF
Cycle time
Effective throughput
Equivalent rate = effective throughput × 7
0
MAX
SCL clock frequency
ns
150
ns
ns
160
ns
Cb = total capacitance of one bus line in pF
μs
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
58.2
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
109.7
μs
8 bits
VDD = 1.8V
17.17
kSPS
12 bits
VDD = 1.8V
9.12
kSPS
8 bits
VDD = 1.8V
120.22
kHz
12 bits
VDD = 1.8V
63.81
kHz
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TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 3.4MHz)
All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
UNIT
3.4
MHz
fSCL
Hold time (repeated) START condition
tHD, STA
160
ns
Low period of SCL clock
tLOW
160
ns
High period of the SCL clock
tHIGH
60
ns
Setup time for a repeated START condition
tSU, STA
160
Data hold time
tHD, DAT
0
Data setup time
tSU, DAT
10
Rise time for SCL signal (receiving)
tR
Cb = total bus capacitance
10
40
ns
Rise time for SDA signal (receiving)
tR
Cb = total bus capacitance
10
80
ns
Fall time for SCL signal (receiving)
tF
Cb = total bus capacitance
10
40
ns
Fall time for SDA signal (receiving)
tF
Cb = total bus capacitance
10
80
ns
Fall time for both SDA and SCL signals (transmitting)
tF
Cb = total bus capacitance
10
80
ns
Setup time for STOP condition
tSU, STO
Capacitive load for each bus line
Cb
100
pF
Cycle time
Effective throughput
Equivalent rate = effective throughput × 7
8
0
MAX
SCL clock frequency
ns
70
ns
160
ns
Cb = total capacitance of one bus line in pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
8 bits
VDD = 1.8V
12 bits
8 bits
12 bits
ns
46.5
μs
95.3
μs
21.52
kSPS
VDD = 1.8V
10.49
kSPS
VDD = 1.8V
150.65
kHz
VDD = 1.8V
73.46
kHz
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TYPICAL CHARACTERISTICS
At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
POWER-DOWN SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
TEMPERATURE
350
High-Speed Mode = 3.4MHz
300
80
VDD = 3.0V
VDD = 3.6V
Supply Current (mA)
Power-Down Supply Current (nA)
100
60
40
VDD = 1.6V
20
250
Fast Mode = 400kHz
200
150
100
0
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 2.
Figure 3.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
(AUX Conversion)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
600
80
100
300
High-Speed Mode = 3.4MHz
250
Supply Current (mA)
500
Supply Current (mA)
Standard Mode = 100kHz
50
400
Fast Mode = 400kHz
300
200
Standard Mode = 100kHz
100
TA = +25°C
I2C Speed = 400kHz
PD1 = PD0 = 0
X, Y, Z Conversion at 200SSPS
200
with MAV
150
MAV Bypassed
100
Touch Sensor Modeled By:
2kW for X-Plane
2kW for Y-Plane
1kW for Z (Touch Resistance)
50
0
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
1.2
1.6
2.0
2.4
VDD (V)
VDD (V)
Figure 4.
Figure 5.
2.8
3.2
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TYPICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
SUPPLY CURRENT (Part Not Addressed)
vs
TEMPERATURE
SUPPLY CURRENT (Part Not Addressed)
vs
SUPPLY VOLTAGE
250
70
200
High-Speed Mode = 3.4MHz
50
Supply Current (mA)
Supply Current (mA)
60
40
30
20
Fast Mode = 400kHz
10
150
High-Speed Mode = 3.4MHz
100
Standard Mode = 100kHz
50
Fast Mode = 400kHz
Standard Mode = 100kHz
0
0
-40
-20
0
20
40
Temperature (°C)
60
80
1.2
100
2.4
VDD (V)
2.8
Figure 7.
CHANGE IN GAIN
vs
TEMPERATURE
CHANGE IN OFFSET
vs
TEMPERATURE
3.2
3.6
80
100
6
VDD = 1.8V
VDD = 1.8V
4
Delta from +25°C (LSB)
4
Delta from +25°C (LSB)
2.0
Figure 6.
6
2
0
-2
-4
2
0
-2
-4
-6
-6
-40
-20
0
20
40
Temperature (°C)
60
80
100
-40
Figure 8.
10
1.6
-20
0
20
40
Temperature (°C)
60
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
SWITCH ON-RESISTANCE
vs
TEMPERATURE
6
11
X+, Y+: VDD = 3.0V to Pin
X-, Y-: Pin to GND
10
Y+
Y5
8
RON (W)
RON (W)
9
7
Y-
X+
4
X-
6
Y+
3
5
X-
4
X+
2
3
8
7
1.6
2.0
2.4
3.6
3.2
-40
-20
0
20
40
60
VDD (V)
Temperature (°C)
Figure 10.
Figure 11.
SWITCH ON-RESISTANCE
vs
TEMPERATURE
TEMP DIODE VOLTAGE
vs
TEMPERATURE
850
X+, Y+: VDD = 1.8V to Pin
X-, Y-: Pin to GND
6
RON (W)
2.8
Y+
800
Y-
TEMP Diode Voltage (mV)
1.2
X+
5
X4
3
100
TEMP2
Measurement Includes
A/D Converter Offset
and Gain Errors
TEMP1
137.5mV
94.2mV
750
80
700
650
600
550
500
450
2
VDD = 1.8V
400
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
Temperature (°C)
Temperature (°C)
Figure 12.
Figure 13.
60
80
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TYPICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,
and MAV filter enabled (see MAV Filter section), unless otherwise noted.
TEMP1 DIODE VOLTAGE
vs
SUPPLY VOLTAGE
TEMP2 DIODE VOLTAGE
vs
SUPPLY VOLTAGE
704
586
584
582
580
578
576
1.2
Internal Oscillator Clock Frequency (MHz)
700
698
696
694
692
VDD = VREF
574
Measurement Includes
A/D Converter Offset
and Gain Errors
702
TEMP2 Diode Voltage (mV)
Measurement Includes
A/D Converter Offset
and Gain Errors
VDD = VREF
690
1.6
2.0
2.4
VDD (V)
2.8
3.2
3.6
1.2
1.6
2.0
2.4
VDD (V)
2.8
3.2
3.6
Figure 14.
Figure 15.
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs
TEMPERATURE
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs
TEMPERATURE
3.40
Internal Oscillator Clock Frequency (MHz)
TEMP1 Diode Voltage (mV)
588
3.30
3.20
3.10
3.00
2.90
2.80
VDD = 1.2V
2.70
-40
-20
0
20
40
Temperature (°C)
60
80
3.70
3.65
3.60
100
VDD = 1.8V
-40
-20
0
Figure 16.
20
40
Temperature (°C)
60
80
100
Figure 17.
Internal Oscillator Clock Frequency (MHz)
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs
TEMPERATURE
3.90
3.85
3.80
3.75
3.70
VDD = 3.0V
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 18.
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OVERVIEW
The TSC2007-Q1 is an analog interface circuit for a human interface touch screen device. All peripheral
functions are controlled through the command byte and onboard state machines. The TSC2007-Q1 features
include:
• Very low-power touch screen controller
• Very small onboard footprint
• Relieves host from tedious routine tasks by preprocessing, thus saving resources for more critical tasks
• Ability to work on very low supply voltage
• Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required
• Miniature, yet complete; requires no external supporting component
• Enhanced electrostatic discharge (ESD) protection
The TSC2007-Q1 consists of the following blocks (refer to the block diagram on the front page):
• Touch Screen Sensor Interface
• Auxiliary Input (AUX)
• Temperature Sensor
• Acquisition Activity Preprocessing
• Internal Conversion Clock
• I2C Interface
Communication with the TSC2007-Q1 is done via an I2C serial interface. The TSC2007-Q1 is an I2C slave
device; therefore, data are shifted into or out of the TSC2007-Q1 under control of the host microprocessor, which
also provides the serial data clock.
Control of the TSC2007-Q1 and its functions is accomplished by writing to the command register of an internal
state machine. A simple command protocol compatible with I2C is used to address this register.
A typical application of the TSC2007-Q1 is shown in Figure 19.
1.8VDC
1mF
0.1mF
1.2kW
X+
VDD/REF
GND
PENIRQ
1.2kW
Host
Processor
GPIO
Y+
A1
AUX
Auxiliary Input
GND
Y-
Touch
Screen
SDA
SDA
SCL
SCL
A0
TSC2007
X-
GND
Figure 19. Typical Circuit Configuration
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TOUCH SCREEN OPERATION
A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in
resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The
change in the resistance ratio marks the location on the touch screen.
The TSC2007-Q1 supports resistive 4-wire configurations, as shown in Figure 20. The circuit determines location
in two coordinate pair dimensions, although a third dimension can be added for measuring pressure.
4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT
A 4-wire touch screen is typically constructed as shown in Figure 20. It consists of two transparent resistive
layers separated by insulating spacers.
Conductive Bar
Transparent Conductor (ITO)
Bottom Side
Y+
X+
Silver
Ink
Transparent
Conductor (ITO)
Top Side
XY-
ITO = Indium Tin Oxide
Insulating Material (Glass)
Figure 20. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.
The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of the
Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+
and Y– drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the
voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+
lead does not affect the conversion because of the high input impedance of the A/D converter.
Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position
on the screen. This process provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2007-Q1. To determine pen or finger touch, the
pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this
test; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations are shown using the
12-bit resolution mode). There are several different ways of performing this measurement. The TSC2007-Q1
supports two methods. The first method requires knowing the X-plate resistance, the measurement of the
X-position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 21).
Equation 1 calculates the touch resistance:
R TOUCH + RX−plate @
14
ǒ
Ǔ
XPosition Z 2
*1
4096 Z 1
(1)
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The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-position and
Y-position, and Z1. Equation 2 also calculates the touch resistance:
RX−plate @ XPosition 4096
Y
R TOUCH +
*1 *R Y−plate @ 1* Position
4096
4096
Z1
ǒ
Ǔ
ǒ
Ǔ
(2)
Measure X-Position
X+
Y+
Touch
X-Position
Y-
X-
Measure Z1-Position
Y+
X+
Touch
Z1-Position
X-
Y-
Y+
X+
Touch
Z2-Position
X-
YMeasure Z2-Position
Figure 21. Pressure Measurement
When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the
touch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result of
mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.
This settling time must be accounted for, or else the converted value is incorrect. Therefore, a delay must be
introduced between the time the driver for a particular measurement is turned on, and the time a measurement is
made.
In some applications, external capacitors may be required across the touch screen for filtering noise picked up by
the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these
capacitors provides a low-pass filter to reduce the noise, but creates an additional settling time requirement when
the panel is touched. The settling time typically shows up as gain error.
To solve this problem, the TSC2007-Q1 can be commanded to turn on the drivers only, without performing a
conversion. Time can then be allowed to perform a conversion before the command is issued.
The TSC2007-Q1 touch screen interface can measure position (X,Y) and pressure (Z).
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INTERNAL TEMPERATURE SENSOR
In some applications, such as battery recharging, an ambient temperature measurement is required. The
temperature measurement technique used in the TSC2007-Q1 relies on the characteristics of a semiconductor
junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic
versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of
the VBE voltage and then monitoring the delta of that voltage as the temperature changes.
The TSC2007-Q1 offers two modes of temperature measurement. The first mode requires calibration at a known
temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in
Figure 22, is used during this measurement cycle. This voltage is typically 580mV at +25°C with a 10μA current.
The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this
voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage would be
stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an
equivalent temperature measurement resolution of 0.35°C/LSB (1LSB = 732μV with VREF = 3.0V).
VDD
TEMP2
TEMP1
+IN
Converter
-IN
GND
Figure 22. Functional Block Diagram of Temperature Measurement Mode
The second mode does not require a test temperature calibration, but uses a two-measurement (differential)
method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This
mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times larger
than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is
represented by:
DV + kT
q @ ln(N)
(3)
Where:
N = the resistance ratio = 91.
k = Boltzmann's constant = 1.3807 × 10–23 J/K (joules/kelvins).
q = the electron charge = 1.6022 × 10–19 C (coulombs).
T = the temperature in kelvins (K).
This method can provide a much improved absolute temperature measurement, but a lower resolution of
1.6°C/LSB. The resulting equation to solve for T is:
q @ DV
T+
k @ ln(N)
(4)
Where:
ΔV = VBE (TEMP2) – VBE(TEMP1) (in mV)
∴ T = 2.573 ⋅ ΔV (in K)
or T = 2.573 ⋅ ΔV – 273 (in °C)
Temperature 1 and temperature 2 measurements have the same timing as the other data acquisition cycles
shown in Figure 33 and Figure 34.
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ANALOG-TO-DIGITAL CONVERTER
Figure 23 shows the analog inputs of the TSC2007-Q1. The analog inputs (X, Y, and Z touch panel coordinates,
chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register
(SAR) A/D converter. The A/D architecture is based on capacitive redistribution architecture, which inherently
includes a sample-and-hold function.
VDD/REF
50kW
RIRQ
PENIRQ
90kW
Pen Touch
X+
TEMP2
TEMP1
Control
Logic
MAV
C3-C0
GND
X-
VDD
Y+
+IN
Y-
+REF
Converter
-IN
-REF
GND
AUX
GND
Figure 23. Analog Input Section (Simplified Diagram)
A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to
provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a
differential input to the converter and a differential reference input architecture, it is possible to negate errors
caused by the driver switch on-resistance.
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Reference
The TSC2007-Q1 uses an external voltage reference that is applied to the VDD/REF pin. The upper reference
voltage range is the same as the supply voltage range, which allows for simple, 1.2V to 3.6V, single-supply
operation of the chip.
Reference Mode
There is a critical item regarding the reference when making measurements while the switch drivers are on. For
this discussion, it is useful to consider the basic operation of the TSC2007-Q1 (see Figure 19). The application
used in the following example shows the device being used to digitize a resistive touch screen. If the touch
screen controller uses a single-ended reference mode, as shown in Figure 24, a measurement of the current Y
position of the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y–
drivers, and digitizing the voltage on X+. For this measurement, the resistance in the X+ lead does not affect the
conversion; it does affect the settling time, but the resistance is usually small enough that this timing is not a
concern. However, because the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers
does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input
or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost
across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the
touch screen, providing an additional source of error. Therefore, the TSC2007-Q1 does not support single-ended
reference mode.
VDD/REF
Y+
+IN
X+
+REF
Converter
-IN
-REF
Y-
GND
Figure 24. Simplified Diagram of Single-Ended Reference
This situation is resolved, as shown in Figure 25, by using the differential mode; the +REF and –REF inputs are
connected directly to Y+ and Y–, respectively. This mode makes the A/D converter ratiometric. The result of the
conversion is always a percentage of the external reference, regardless of how it changes in relation to the
on-resistance of the internal switches.
VDD/REF
Y+
X+
+IN
+REF
Converter
-IN
-REF
Y-
GND
Figure 25. Simplified Diagram of Differential Reference
(Both Y Switches Enabled, X+ is Analog Input)
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Touch Screen Settling
In some applications, external capacitors may be required across the touch screen to filter noise picked up by the
touch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide a
low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched.
The settling time typically shows up as a gain error. The problem is that the input and/or reference has not
settled to its final steady-state value before the A/D converter samples the input(s) and provides the digital
output. Additionally, the reference voltage may continue to change during the measurement cycle.
To resolve these settling-time problems, the TSC2007-Q1 can be commanded to turn on the drivers only without
performing a conversion (see Table 3). Time can then be allowed, before the command is issued, to perform a
conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate
for the touch screen to settle.
Variable Resolution
The TSC2007-Q1 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often
practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower
resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which
also lowers power consumption.
8-Bit Conversion
The TSC2007-Q1 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed,
and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a
conversion result can be read by transferring only one data byte. The internal clock runs twice as fast at 4MHz.
The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewer
clock cycles and provides lower power consumption.
Conversion Clock and Conversion Time
The TSC2007-Q1 contains an internal clock, which drives the state machines inside the device that perform the
many functions of the part. This clock is divided down to provide a clock that runs the A/D converter. The
frequency of this clock is 4MHz clock for 8-bit mode, and 2MHz for the 12-bit mode.
Data Format
The TSC2007-Q1 output data are in straight binary format as shown in Figure 26. This figure shows the ideal
output code for the given input voltage and does not include the effects of offset, gain, or noise.
FS = Full-Scale Voltage = VREF(1)
1LSB = VREF(1)/4096
1LSB
11...111
Output Code
11...110
11...101
00...010
00...001
00...000
0V
Input Voltage
(2)
FS - 1LSB
(V)
(1)
Reference voltage at converter: +REF – (–REF). See Figure 23.
(2)
Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 23.
Figure 26. Ideal Input Voltages and Output Codes
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Touch Detect
The PENIRQ can be used as an interrupt to the host. RIRQ is an internal pull-up resistor with a programmable
value of either 50kΩ (default) or 90kΩ. Write command '1011' (setup command) followed by data '0001' sets the
pull-up to 90kΩ. NOTE: The first three bits must be '0's and the select bit is the last bit. To change the pull-up
back to 50kΩ, issue write command '1011' followed by data '0000'.
An example for the Y-position measurement is detailed in Figure 27. The PENIRQ output is pulled high by an
internal pull-up. While in power-down mode with PD0 = 0, the Y– driver is on and connected to GND, and the
PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground
through the touch screen, and the PENIRQ output goes low because of the current path through the panel to
GND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-position, the X+
input is disconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage current from
flowing through the touch screen, thus causing no errors.
In addition to the measurement cycles for X-, Y-, and Z-position, commands that activate the X-drivers, Y-drivers,
and Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ
pull-down transistor, and disable the pen-interrupt output function, regardless of the value of the PD0 bit. Under
these conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to the
TSC2007-Q1 contains PD0 = 1, the pen-interrupt output function is disabled and cannot detect when the panel is
touched. In order to re-enable the pen-interrupt output function under these circumstances, a command byte
must be written to the TSC2007-Q1 with PD0 = 0.
When the bus master sends the address byte with the R/W bit = 0, and the TSC2007-Q1 sends an acknowledge,
the pen-interrupt function is disabled. If the command that follows the address byte contains PD0 = 0, then the
pen-interrupt function is enabled at the end of a conversion. This action is approximately 100μs (12-bit mode) or
50μs (8-bit mode) after the TSC2007-Q1 receives a STOP/START condition, following the receipt of a command
byte (see Figure 31 and Figure 30 for further details about when the conversion cycle begins).
In both cases previously listed, it is recommended that whenever the host writes to the TSC2007-Q1, the master
processor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts when
the PENIRQ line is disabled in the cases previously listed.
Connect to
Analog Supply
PENIRQ
VDD/REF
VDD
RIRQ
Pen Touch
Control
Logic
TEMP1
High when
the X+ or Y+
driver is on.
X+
TEMP2
Y+
Sense
GND
Y-
ON
GND
High when the X+ or Y+
driver is on, or when any
sensor connection/shortcircuit tests are activated.
Vias go to system analog ground plane.
GND
Figure 27. Example of a Pen-Touch Induced Interrupt via the PENIRQ Pin
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Preprocessing
The TSC2007-Q1 has a combined MAV filter (median value filter and averaging filter).
MAV Filter
If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate the
data without noise. In this case, the median value filter operation helps remove the noise. The array of seven
converted results is sorted first. The middle three values are then averaged to produce the output value of the
MAV filter.
The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperature
measurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter may
be bypassed through the setup command; see Table 3 and Table 4.
7 measurements input
into temporary array
7
7 Acquired
Data
Sort by
descending order
Averaging output
from window of 3
7
3
Figure 28. MAV Filter Operation (Patent Pending)
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I2C INTERFACE
The TSC2007-Q1 supports the I2C serial bus and data transmission protocol in all three defined modes:
standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are slaves. The bus must be controlled by a master device that generates the serial
clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2007-Q1
operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL.
The following bus protocol has been defined (see Figure 29):
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy Both data and clock lines remain HIGH.
Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines
a START condition.
Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data Valid The state of the data line represents valid data, when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between START and STOP conditions is not limited
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth-bit.
Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz
clock rate), and a high-speed mode (1.7MHz or 3.4MHz clock rate) are each defined. The
TSC2007-Q1 works in all three modes.
Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Of course, setup and hold times must be taken into account. A
master must signal an end of data to the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.
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Figure 29 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave
address and each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is
transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other
than the last byte. At the end of the last received byte, a not-acknowledge is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends
with a STOP condition or a repeated START condition. Because a repeated START condition is also the
beginning of the next serial transfer, the bus is not released.
The TSC2007-Q1 may operate in the following two modes:
1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit.
2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data are
transmitted on SDA by the TSC2007-Q1 while the serial clock is input on SCL. START and STOP conditions
are recognized as the beginning and end of a serial transfer.
I2C Fast or Standard Mode (F/S Mode)
In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information
section.
In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a
START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has
finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high, as shown in Figure 29. The bus is free for another transmission after a STOP
condition has occurred. Figure 29 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The
address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA
state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are
transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word
plus acknowledge bit).
SDA
MSB
Slave Address
R/W
Direction Bit
Acknowledgement
Signal from Receiver
Acknowledgement
Signal from Receiver
1
SCL
2
6
7
8
9
1
2
3-8
8
ACK
START
Condition
9
ACK
Repeated If More Bytes Are Transferred
STOP Condition
or Repeated
START Condition
Figure 29. Complete Fast- or Standard-Mode Transfer
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I2C High-Speed Mode (Hs Mode)
The TSC2007-Q1 can operate with high-speed I2C masters. To do so, the pull-up resistor on SCL must be
changed to an active pull-up, as recommended in the I2C specification.
Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus
specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:
1. START condition (S)
2. 8-bit master code (00001xxx)
3. Not-acknowledge bit (N)
Figure 30 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for
triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code
indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the
Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is
followed by a not-acknowledge bit (N).
After the not-acknowledge bit (N) and SCL have been pulled-up to a HIGH level, the master switches to
Hs-mode and enables the current-source pull-up circuit for SCL (at time tH shown in Figure 30). Because other
devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables the
current-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus
speeding up the last part of the rise time of the SCL.
The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit
address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition
and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up
circuit. This disabling enables other devices, such as the TSC2007-Q1, to delay the serial transfer (until the
converted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The master
re-enables its current-source pull-up circuit again when all devices have released SCL, and SCL reaches a HIGH
level, which speeds up the last part of the SCL signal rise time.
Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode
after a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link a
number of Hs mode transfers, separated by repeated START conditions (Sr).
8-Bit Master Code 00001xxx
S
N
tH
SDA
SCL
1
2 to 5
6
7
8
9
Fast or Standard Mode
R/W
7-Bit Slave Address
Sr
A
n x (8-Bit DATA
+
A/N)
Sr P
SDA
SCL
1
2 to 5
6
7
8
9
1
2 to 5
6
7
8
9
If P then
Fast or Standard Mode
High-Speed Mode
= Current Source Pull-Up
tH
= Resistor Pull-Up
If Sr (dotted lines)
then High-Speed Mode
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
tFS
Figure 30. Complete High-Speed Mode Transfer
24
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DIGITAL INTERFACE
ADDRESS BYTE
The TSC2007-Q1 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are
factory-preset to comply with the I2C standard for A/D converters and are always set at '10010'. The logic state of
the address input pins (A1-A0) determines the two LSBs of the device address to activate communication.
Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one
time.
The A1-A0 address inputs are read whenever an address byte is received, and should be connected to the
supply pin (VDD/REF) or the ground pin (GND). The slave address is latched into the TSC2007-Q1 on the falling
edge of SCL after the read/write bit has been received by the slave.
The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation
is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2007-Q1
monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the
appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
Table 1. I2C Slave Address Byte
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
1
0
0
1
0
A1
A0
R/W
Bit D0: R/W
1: I2C master read from TSC (I2C read addressing).
0: I2C master write to TSC (I2C write addressing).
COMMAND BYTE
Table 2. Command Byte Definition (Excluding the Setup Command) (1)
(1)
BIT
NAME
DESCRIPTION
D7-D4
C3-C0
All Converter Function Select bits as detailed in Table 3, except for the setup command ('1011').
D3-D2
PD1-PD0
D1
M
0: 12-bit (Lower speed referred to as the 2MHz clock).
1: 8-bit (Higher speed referred to as the 4MHz clock).
D0
X
Don't care.
00:
01:
10:
11:
Power down between cycles. PENIRQ enabled.
A/D converter on. PENIRQ disabled.
A/D converter off. PENIRQ enabled.
A/D converter on. PENIRQ disabled.
The command byte definition for the setup command is shown in Table 4.
Bits D7-D4: C3-C0—Converter function select bits. These bits select the input to be converted and the converter
function to be executed, activate the drivers, and configure the PENIRQ pull-up resistor (RIRQ). Table 3 lists the
possible converter functions.
Bits D3-D2: PD1-PD0—Power-down bits. These two bits select the power-down mode that the TSC2007-Q1 will
be in after the current command completes, as shown in Table 2.
It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If
multiple X-, Y-, and Z-position measurements will be done one right after another (such as when averaging), PD0
=1 will leave the touch screen drivers on at the end of each conversion cycle.
Bit D1: M—Mode bit. If M = 0, the TSC2007-Q1 is in 12-bit mode. If M = 1, 8-bit mode is selected.
Bit D0: X—Don’t care.
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When the TSC2007-Q1 powers up, the power-down bits must be written to ensure that the device is placed into
the mode that achieves the lowest power. Therefore, immediately after power-up, send a command byte that
sets PD1 = PD0 = 0, so that the device will be in the lowest power mode, powering down between conversions.
Table 3. Converter Function Select
(1)
INPUT TO
A/D
CONVERTER
X-DRIVERS
Y-DRIVERS
ACK
REFERENCE
MODE
OFF
Y
Single-Ended
OFF
N
Single-Ended
OFF
Y
Single-Ended
OFF
N
Single-Ended
OFF
OFF
Y
Single-Ended
N/A
OFF
OFF
N
Single-Ended
Reserved
N/A
OFF
OFF
N
Single-Ended
Reserved
N/A
OFF
OFF
N
Single-Ended
0
Activate X-drivers
N/A
ON
OFF
Y
Differential
0
1
Activate Y-drivers
N/A
OFF
ON
Y
Differential
1
0
Activate Y+, X-drivers
N/A
X– ON
Y+ ON
Y
Differential
0
1
1
Setup command (1)
N/A
OFF
OFF
N
N/A
1
1
0
0
Measure X position
Y+
ON
OFF
Y
Differential
1
1
0
1
Measure Y position
X+
OFF
ON
Y
Differential
1
1
1
0
Measure Z1 position
X+
X– ON
Y+ ON
Y
Differential
1
1
1
1
Measure Z2 position
Y–
X– ON
Y+ ON
Y
Differential
C3
C2
C1
C0
FUNCTION
0
0
0
0
Measure TEMP0
TEMP0
OFF
0
0
0
1
Reserved
N/A
OFF
0
0
1
0
Measure AUX
AUX
OFF
0
0
1
1
Reserved
N/A
OFF
0
1
0
0
Measure TEMP1
TEMP1
0
1
0
1
Reserved
0
1
1
0
0
1
1
1
1
0
0
1
0
1
0
1
The setup command has an additional four bits of data. These data are static; that is, they are not changed by other commands, except
for the power-on reset. The default value for these bits after power-on reset is 0000. Table 4 shows the definition of these data bits.
Table 4. Command Byte Definition for the Setup Command
BIT
26
NAME
DESCRIPTION
D7-D4
C3-C0 = '1011'
Setup command; must write '1011'.
D3-D2
PD1-PD0 = '00'
Reserved; must write '00'.
D1
Filter control
D0
PENIRQ pull-up resistor (RIRQ) select
0: Use the onboard MAV filter (default).
1: Bypass the onboard MAV filter.
0: RIRQ = 50kΩ (default).
1: RIRQ = 90kΩ.
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START A CONVERTER FUNCTION/WRITE CYCLE
A conversion/write cycle begins when the master issues the address byte containing the slave address of the
TSC2007-Q1, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 1. Once the eighth bit has been
received, and the address matches the A1-A0 address input pin setting, the TSC2007-Q1 issues an
acknowledge.
When the master receives the acknowledge bit from the TSC2007-Q1, the master writes the command byte to
the slave (see Table 2). After the command byte is received by the slave, the slave issues another acknowledge
bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in
Figure 31.
SCL
Address Byte
1
SDA
0
0
1
0
Command Byte
A1
A0
R/W
0
0
C3
C2
C1
C0 PD1 PD0
TSC2007
ACK
M
X
TSC2007
ACK
Acquisition
START
0
Conversion
STOP or
Repeated START
Figure 31. Complete I2C Serial Write Transmission
If the master sends additional command bytes after the initial byte, but before sending a STOP or repeated
START condition, the TSC2007-Q1 does not acknowledge those bytes.
The input multiplexer channel for the A/D converter is selected when bits C3 through C0 are clocked in. If the
selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers turn on once the acquisition
period begins.
When R/W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of the
command byte has been latched, and ends when a STOP or repeated START condition has been issued. A/D
conversion starts immediately after the acquisition period. The multiplexer inputs to the A/D converter are
disabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective
touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 31.
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READ A CONVERSION/READ CYCLE
For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This
idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007-Q1. The master
should wait for at least 10μs before attempting to read data from the TSC2007-Q1 to realize this best
performance. However, the master does not need to wait for a completed conversion before beginning a read
from the slave, if full 12-bit performance is not necessary.
Data access begins with the master issuing a START condition followed by the address byte (see Table 1) with
R/W = 1.
When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first
byte of serial data then follows (D11-D4, MSB first).
After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.
The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,
followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to
indicate that the last data byte has been received. If the master somehow acknowledges the second data byte,
invalid data are returned (FFh). This condition applies to both 12-and 8-bit modes. See Figure 32 for a complete
I2C read transmission.
SCL
Address Byte
SDA
1
0
0
1
0
Data Byte 2
Data Byte 1
A1 A0 R/W
1
START
0
D11 D10
TSC2007
ACK
D9 D8 D7 D6 D5 D4
0
D3 D2 D1 D0
MASTER
ACK
0
0
0
0
1
MASTER STOP or
NACK
Repeated
START
Figure 32. Complete I2C Serial Read Transmission
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THROUGHPUT RATE AND I2C BUS TRAFFIC
Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is
much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The
throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit
resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the
system to use on other devices.
Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal
4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency
reduces to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate.
12-Bit Operation
For 12-bit operation, sending the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each
write cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle
takes 29 I2C cycles (START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Seven
sample-and-conversions take 19 x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks.
For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 5. Because the first
acquisition cycle overlaps with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For
12-bit mode, (19 × 7 + 19) – 4 = 148 CCLKs plus I/O are required.
8-Bit Operation
For 8-bit operation, sending the conversion result across the I2C bus takes 40 bus clocks (SCL clock). Each write
cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 20
I2C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-conversions takes 16 x 7
internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.2V, the complete
processed data cycle time calculations are shown in Table 5. Because the first acquisition cycle overlaps with the
I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 8-bit mode, (16 × 7 + 19) – 4 = 127
CCLKs plus I/O are required.
Table 5. Measurement Cycle Time Calculations
STANDARD MODE: 100kHz (Period = 10μs)
8-Bit
40 × 10μs + 127 × 313ns = 439.8μs (2.27kSPS through the I2C bus)
12-Bit
49 × 10μs + 148 × 625ns = 582.5μs (1.72kSPS through the I2C bus)
FAST MODE: 400kHz (Period = 2.5μs)
8-Bit
40 × 2.5μs + 127 × 313ns = 139.8μs (7.15kSPS through the I2C bus)
12-Bit
49 × 2.5μs + 148 × 625ns = 215μs (4.65kSPS through the I2C bus)
HIGH-SPEED MODE: 1.7MHz (Period = 588ns)
8-Bit
40 × 588ns + 127 × 313ns = 63.3μs (15.79kSPS through the I2C bus)
12-Bit
49 × 588ns + 148 × 625ns = 121.3μs (8.24kSPS through the I2C bus)
HIGH-SPEED MODE: 3.4MHz (Period = 294ns)
8-Bit
40 × 294ns + 127 × 313ns = 51.6μs (19.39kSPS through the I2C bus)
12-Bit
49 × 294ns + 148 × 625ns = 106.9μs (9.35kSPS through the I2C bus)
As an example, use VDD = 1.2V and 12-bit mode with the Fast-mode I2C clock (fSCL = 400kHz). The equivalent
TSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 =
32.55kSPS). The supply current to the TSC for this rate and configuration is 128μA. To achieve an equivalent
sample throughput of 8.2kSPS using the device without preprocessing, the TSC2007-Q1 consumes only
(8.2/32.55) × 128μA = 32.24μA.
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Table 6. Effective and Equivalent Throughput Rates
SUPPLY
VOLTAGE
I C BUS SPEED
(fSCL)
RESOLUTION
TSC
CONVERSION
CYCLE TIME
(μs)
100kHz
Standard
8-bit
433.6
2.31
16.14
40
127
3780
264.6
12-bit
568.7
1.76
12.31
49
148
1880
531.9
8-bit
133.6
7.49
52.40
40
127
3780
264.6
12-bit
201.2
4.97
34.79
49
148
1880
531.9
8-bit
57.1
17.50
122.53
40
127
3780
264.6
12-bit
107.5
9.30
65.09
49
148
1880
531.9
8-bit
45.4
22.04
154.31
40
127
3780
264.6
12-bit
93.1
10.74
75.16
49
148
1880
531.9
8-bit
434.7
2.30
16.10
40
127
3660
273.2
12-bit
570.9
1.75
12.26
49
148
1830
546.4
8-bit
134.7
7.42
51.97
40
127
3660
273.2
12-bit
203.4
4.92
34.42
49
148
1830
546.4
8-bit
58.2
17.17
120.22
40
127
3660
273.2
12-bit
109.7
9.12
63.81
49
148
1830
546.4
2
400kHz
Fast
2.7V
1.7MHz
High-Speed
3.4MHz
High-Speed
100kHz
Standard
400kHz
Fast
1.8V
1.7MHz
High-Speed
EQUIVALENT
THROUGHPUT
(kSPS)
NO.
OF
SCL
NO.
OF
CCLK
fCCLK
(kHz)
CCLK
PERIODS
(ns)
3.4MHz
High-Speed
8-bit
46.5
21.52
150.65
40
127
3660
273.2
12-bit
95.3
10.49
73.46
49
148
1830
546.4
100kHz
Standard
8-bit
439.8
2.27
15.92
40
127
3190
313.5
12-bit
582.5
1.72
12.02
49
148
1600
625.0
8-bit
139.8
7.15
50.07
40
127
3190
313.5
12-bit
215.0
4.65
32.56
49
148
1600
625.0
8-bit
63.3
15.79
110.51
40
127
3190
313.5
12-bit
121.3
8.24
57.70
49
148
1600
625.0
8-bit
51.6
19.39
135.72
40
127
3190
313.5
12-bit
106.9
9.35
65.47
49
148
1600
625.0
400kHz
Fast
1.2V
1.7MHz
High-Speed
3.4MHz
High-Speed
30
EFFECTIVE
THROUGHPUT
(kSPS)
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I2C Write
I2C Read
Clock Stretched
SCL
CCLK
Address Byte
SDA
1
0
0
1
0
Command Byte
A1
R/W
A0 0
0
C3 C2
C1 C0 PD1 PD0
Address Byte
M
TSC2007
ACK
X
0
0
1
0
1
A0
R/W
1
Acquisition 1
6 SCLs
D11 D10
0
D9
D8
D7
D6
D5
TSC2007
ACK
TSC2007
ACK
START
Data Byte 2
Data Byte 1
A1
0
Conversion 1
15 CCLKs
STOP or
REPEATED START (
Acquisition 2
4 CCLKs
Conversion 7
15 CCLKs
Conversion 2
15 CCLKs
D4
0
D3
D2
D1
D0
0
0
0
1
MASTER
NACK
MASTER
ACK
MAV Filter
19 CCLKs
0
STOP or
REPEATED START
)
148 CCLKs (Filter is Enabled, 12-Bit Mode)
Figure 33. Data Acquisition Cycle (Filter Enabled)
I2C Write
I2C Read
Clock Stretched
SCL
CCLK
Address Byte
SDA
1
0
0
1
0
Command Byte
A1
A0
R/W
0
C3 C2
TSC2007
ACK
START
Address Byte
Data Byte 2
Data Byte 1
R/W
0
C1
C0 PD1 PD0
M
X
0
1
0
0
1
0
TSC2007
ACK
A1
A0
1
0
D11 D10
TSC2007
ACK
Acquisition 1
6 SCLs
Conversion 1
15 CCLKs
STOP or
REPEATED START (
D9
D8
D7
D6
D5
D4
0
D3
MASTER
ACK
D2
D1
D0
0
0
0
0
1
MASTER
NACK
STOP or
REPEATED START
)
15 CCLKs (Filter is Disabled, 12-Bit Mode)
Figure 34. Data Acquisition Cycle (Filter Disabled)
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POWER-ON RESET (POR)
During TSC2007-Q1 power-up, an internal power-on reset (POR) is automatically implemented. The POR brings
the TSC to the default working condition, and checks the A0 and A1 pins for the two LSBs of the I2C address.
The TSC2007-Q1 senses the power-up curve to decide whether or not to implement a POR.
It is required to follow the power-on/off slope and interval requirements, as provided in the Electrical
Characteristics
, in order to ensure a proper POR of the TSC2007-Q1.
tVDD_ON_RAMP
tVDD_OFF_RAMP
1.2V to 3.6V
0.9V
VDD
0.3V
0V
tVDD_OFF
Figure 35. Power-On Reset Timing
Table 7. Timing Requirements for Figure 35
PARAMETER
TEST CONDITIONS
MIN
TA = –40°C to +85°C
VDD off ramp
VDD off time
VDD on ramp
MAX
UNIT
2
kV/s
TA = –40°C to +85°C, VDD = 0V
1.2
TA = –20°C to +85°C, VDD = 0V
0.3
s
TA = –40°C to +85°C
12
kV/s
s
VDD Off Time for Valid POR (s)
1.4
1.2
1.0
Recommended VDD Off Time
for TA = -40°C to +85°C
0.8
0.6
0.4
0.2
0
Typical VDD Off Time for Various Temperatures
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 36. VDD Off Time vs Temperature
32
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TSC2007-Q1
TSC2007-Q1
SBAS545 – SEPTEMBER 2011
www.ti.com
LAYOUT
The following layout suggestions should obtain optimum performance from the TSC2007-Q1. Keep in mind that
many portable applications have conflicting requirements for power, cost, size, and weight. In general, most
portable devices have fairly clean power and grounds because most of the internal components are very low
power. This situation would mean less bypassing for the converter power and less concern regarding grounding.
However, each situation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care should be taken with the physical layout of the TSC2007-Q1 circuitry. The basic
SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,
and digital inputs that occur immediately before latching the output of the analog comparator. Therefore, during
any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages
can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage,
layout, and the exact timing of the external event. The error can change if the external event changes in time
with respect to the SCL input.
With this consideration in mind, power to the TSC2007-Q1 should be clean and well-bypassed. A 0.1μF ceramic
bypass capacitor should be placed as close to the device as possible. In addition, a 1μF to 10μF capacitor may
also be needed if the impedance of the connection between VDD/REF and the power supply is high.
A bypass capacitor is generally not needed on the VDD/REF pin because the internal reference is buffered by an
internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any
bypass capacitor that is used without oscillation.
The TSC2007-Q1 architecture offers no inherent rejection of noise or voltage variation with regard to using an
external reference input, which is of particular concern when the reference input is tied to the power supply. Any
noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered
out, voltage variation because of line frequency (50Hz or 60Hz) can be difficult to remove. Some package
options have pins labeled as VOID. Avoid any active trace going under any pin marked as VOID unless it is
shielded by a ground or power plane.
The GND pin should be connected to a clean ground point. In many cases, this point is the analog ground. Avoid
connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout
includes an analog ground plane dedicated to the converter and associated analog circuitry.
In the specific case of use with a resistive touch screen, care should be taken with the connection between the
converter and the touch screen. Resistive touch screens have fairly low resistance; therefore, the interconnection
should be as short and robust as possible. Loose connections can be a source of error when the contact
resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch-screen applications (for example,
applications that require a back-lit LCD panel). This electromagnetic interference (EMI) noise can be coupled
through the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Several
things can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected
to ground, which couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y–, X+, and
X– to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and
requires a longer time for panel voltages to stabilize. The resistor value varies depending on the touch screen
sensor used. The PENIRQ pull-up resistor (RIRQ) may be adequate for most of sensors.
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TSC2007-Q1
33
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2012
PACKAGING INFORMATION
Orderable Device
TSC2007IPWRQ1
Status
(1)
Package Type Package
Drawing
ACTIVE
TSSOP
PW
Pins
Package Qty
16
2000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TSC2007-Q1 :
• Catalog: TSC2007
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TSC2007IPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TSC2007IPWRQ1
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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