SN74LVC1G04-EP www.ti.com ................................................................................................................................................. SCES691A – MARCH 2007 – REVISED OCTOBER 2008 SINGLE INVERTER GATE FEATURES 1 • • • • • • 2 • • Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Custom temperature ranges available DESCRIPTION/ORDERING INFORMATION This single inverter gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G04 performs the Boolean function Y = A. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated SN74LVC1G04-EP SCES691A – MARCH 2007 – REVISED OCTOBER 2008 ................................................................................................................................................. www.ti.com ORDERING INFORMATION TA –55°C to 125°C (1) (2) PACKAGE (1) SOT (SOT-23) – DBV ORDERABLE PART NUMBER Reel of 3000 SN74LVC1G04MDBVREP TOP-SIDE MARKING (2) SBKM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV: The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUT A OUTPUT Y H L L H LOGIC DIAGRAM (POSITIVE LOGIC) A 2 Submit Documentation Feedback 2 4 Y Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G04-EP SN74LVC1G04-EP www.ti.com ................................................................................................................................................. SCES691A – MARCH 2007 – REVISED OCTOBER 2008 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 206 °C/W 150 °C Continuous current through VCC or GND θJA Package thermal impedance Tstg Storage temperature range (1) (2) (3) (4) (4) –65 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G04-EP Submit Documentation Feedback 3 SN74LVC1G04-EP SCES691A – MARCH 2007 – REVISED OCTOBER 2008 ................................................................................................................................................. www.ti.com Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 0.65 × VCC VCC = 4.5 V to 5.5 V VIL UNIT 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V VCC = 4.5 V –32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current Δt/Δv Input transition rise or fall rate 8 16 VCC = 3 V (1) 4 mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA mA –24 ns/V 5 Operating free-air temperature –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G04-EP SN74LVC1G04-EP www.ti.com ................................................................................................................................................. SCES691A – MARCH 2007 – REVISED OCTOBER 2008 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH VCC – 0.1 1.2 IOH = –8 mA 2.3 V 1.9 TYP (1) MAX 2.3 IOH = –32 mA 4.5 V IOL = 100 µA 3.6 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 3.8 0.4 3V IOL = 24 mA IOL = 32 mA ICC VI = 5.5 V or GND IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND CI VI = VCC or GND (1) All typical values are at VCC = 3.3 V, TA = 25°C. 0.55 0 to 5.5 V ±5 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 500 µA VI = 5.5 V or GND VI or VO = 5.5 V V 0.55 4.5 V Ioff UNIT V 2.4 3V IOL = 16 mA A input 3.6V 1.65 V IOH = –24 mA II MIN IOH = –4 mA IOH = –16 mA VOL VCC 3 V to 5.5 V 3.3 V 3.5 pF Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V MIN MAX 3 VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX MIN MAX 1.4 8.0 1 5.7 1 4.5 13.9 VCC = 5 V ± 0.5 V UNIT ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP f = 10 MHz 16 18 18 Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G04-EP VCC = 5 V 20 Submit Documentation Feedback UNIT TYP pF 5 SN74LVC1G04-EP SCES691A – MARCH 2007 – REVISED OCTOBER 2008 ................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G04-EP SN74LVC1G04-EP www.ti.com ................................................................................................................................................. SCES691A – MARCH 2007 – REVISED OCTOBER 2008 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G04-EP Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) SN74LVC1G04MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SBKM V62/07625-01XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SBKM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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OTHER QUALIFIED VERSIONS OF SN74LVC1G04-EP : Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 • Catalog: SN74LVC1G04 • Automotive: SN74LVC1G04-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LVC1G04MDBVREP SOT-23 DBV 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 3.2 B0 (mm) K0 (mm) P1 (mm) 3.2 1.4 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G04MDBVREP SOT-23 DBV 5 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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