LS7083NS‐14 June 2013 QUADRATURE CLOCK CONVERTER FEATURES: • • • • • • • X1 and x4 mode selection Up to 16MHz output clock frequency Programmable output clock pulse width On-chip filtering of inputs for optical or magnetic encoder applications TTL and CMOS compatible I/Os +3V to +12V operation (VDD – VSS) LS7083NS-14 (SOIC) – See Figure 1. PIN ASSIGNMENT TOP VIEW Applications: • Interface incremental encoders to Up/Down Counters (See Figure 6A and 6B) DESCRIPTION: The LS7083NS-14 is a CMOS quadrature clock converter. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7083NS-14 are converted to strings of Up Clocks and Down Clocks. These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. INPUT/OUTPUT DESCRIPTION: VDD (Pin 2) Supply voltage positive terminal. RBIAS (Pin 3) Input for external component connection. A resistor connected between this input and VSS adjusts the output clock pulse width (TOW). For proper operation, the output clock pulse width must be less than or equal to the A, B pulse separation (TOW ≤ TPS). VSS (Pin 4) Supply voltage negative terminal. A (Pin 5) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. B (Pin 10) Quadrature Clock Input B. This input has a filter circuit identical to input A. Mode (Pin 11) Mode is a 3-state input to select resolutions x1, x2, or x4. The selected resolution multiplies the input quadrature clock rate by 1, 2 and 4 respectively; in producing the outputs UPCK/DNCK and CLK (see Figure 2). The Mode input logic levels selects resolutions as follows: Logic 0 = x1 Float = x2 Logic 1 = x4 7083NS-14-062713-1 FIGURE 1. DNCK (Pin 12) This is the DOWN Clock Output. This output consists of low-going pulses generated when A input lags the B input. UPCK (Pin 13) This is the UP Clock Output. This output consists of low-going pulses generated when A input leads the B input. . ABSOLUTE MAXIMUM RATINGS: PARAMETER DC Supply Voltage Voltage at any Input Operating Temperature Storage Temperature SYMBOL VDD - VSS VIN TA TSTG VALUE 16.0 VSS – 0.3 to VDD + 0.3 0 to +70 -55 to +150 UNIT V V °C °C DC ELECTRICAL CHARACTERISTICS: (All voltages referenced to VSS, TA = 0°C to 70°C.) PARAMETER Supply Voltage SYMBOL VDD MIN 3.0 MAX 12.0 UNIT V Supply Current IDD - 100 μA MODE Logic Low A, B Logic Low VIL VIL - 0.5VDD 0.7 1.0 2.8 V V V V VDD = 3V VDD = 5V VDD = 12V MODE Logic High A, B Logic High VIH VIH VDD - 0.5 2.0 3.0 6.6 - V V V V VDD = 3V VDD = 5V VDD = 12V ALL OUTPUTS: Sink Current VOL = 0.4V IOL 1.3 1.9 2.9 - mA mA mA VDD = 3V VDD = 5V VDD = 12V IOH 0.83 1.1 1.6 - mA mA mA VDD = 3V VDD = 5V VDD = 12V SYMBOL MIN MAX UNIT CONDITIONS TVD - 250 170 71 ns ns ns VDD=3V VDD = 5V VDD = 12V A,B inputs: Pulse Width TPW TVD+TOW Infinite ns - A to B or B to A Phase Delay TPS TOW Infinite ns - A,B frequency fA,B - 1 / 2TPW Hz - Input to Output Delay TDS - 280 220 120 ns ns ns VDD = 3V VDD = 5V VDD = 12V Includes input validation delay Output Clock Pulse Width TOW 50 - ns See Fig. 4 & 5 Source Current VOH = VDD - 0.5V CONDITIONS VDD = 12V, All input frequencies = 0Hz RBIAS = 2MΩ TRANSIENT CHARACTERISTICS: (TA = 0°C to 70°C.) PARAMETER A,B inputs: Validation Delay 7083NS-14-062713-2 NOTE: Output clocks labeled 1,2 and 4 have the following interpretations. 1. Generated in x1, x2 and x4 modes. 2. Generated in x2 and x4 modes only. 3. Generated in x4 mode only. FIGURE 2. LS7083NS-14 INPUT/OUTPUT TIMING FIGURE 3. LS7083NS-14 BLOCK DIAGRAM The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, or for any infringements of patent rights of others which may result from its use. 7083NS-14-062713-3 FIGURE 4. TOW vs RBIAS, kΩ FIGURE 6A. TYPICAL APPLICATION FOR LS7083NS-14 in x4 MODE 7083NS-14-062713-4 FIGURE 5. TOW vs RBIAS, MΩ FIGURE 6B. TYPICAL APPLICATION FOR LS7083NS-14 in x2 MODE