INTEGRAL IN74HC193

TECHNICAL DATA
IN74HC193
Presettable 4-Bit Binary UP/DOWN Counter
High-Performance Silicon-Gate CMOS
The IN74HC193 is identical in pinout to the LS/ALS193. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When
the Parallel Load input is taken low the data is loaded independently of
either clock input. This feature allows the counters to be used as
devide-by-n by modifying the count lenght with the preset inputs. In
addition the counter can also be cleared. This is accomplished by
inputting a high on the Master Reset input. All 4 internal stages are set
to low independently of either clock input.Both a Terminal Count
Down (TCD) and Terminal Count Up (TCU) Outputs are provided to
enable cascading of both up and down counting functions. The TCD
output produces a negative going pulse when the counter underflows
and TCU outputs a pulse when the counter overflows. The counter can
be cascaded by connecting the TCU and TCD outputs of one device to
the Count Up Clock and Count Down Clock inputs, respectively, of the
next device.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
258
ORDERING INFORMATION
IN74HC193N Plastic
IN74HC193D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
IN74HC193
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
259
IN74HC193
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
VOH
Test Conditions
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL
Guaranteed Limit
Maximum Low-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
8.0
80
160
µA
FUNCTION TABLE
MR
PL
Inputs
CPU
H
X
L
L
L
H
L
H
L
H
L
H
X = don’t care
260
X
X
H
H
Mode
CPD
X
X
H
H
Reset(Asyn.)
Preset(Asyn.)
No Count
Count Up
Count Down
No Count
The IN74HC193 is an UP/DOWN MODULO16 Binary Counter.
Logic equations
For Terminal Count:
TCU = Q0 • Q1 • Q2 • Q3 • CPU
TCD = Q0 • Q1 • Q2 • Q3 • CPD
IN74HC193
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
V
25 °C to
-55°C
≤85°C
≤125°C
Unit
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1 and 6)
2.0
4.5
6.0
12
36
43
3.2
16
19
2.6
13
15
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
tPLH, tPHL
Maximum Propagation Delay, PL to Q
(Figures 3 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to Terminal
Count (Figures 2 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH, tTHL
Maximum Output Transition Time,Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
20
18
110
23
20
ns
-
10
10
10
pF
Symbol
fmax
CIN
CPD
Parameter
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
60
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C to -55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Pn to PL
(Figure 4)
2.0
4.5
6.0
100
20
18
125
35
22
150
30
26
ns
th
Minimum Hold Time, Pn to PL
(Figure 4)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
tw
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tw
Minimum Pulse Width, PL
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
ns
tw
Minimum Pulse Width, MR
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
ns
Minimum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
100
500
400
100
500
400
100
500
400
ns
tr, tf
261
IN74HC193
262
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Test Circuit
IN74HC193
TIMING DIAGRAM
263
IN74HC193
EXPANDED LOGIC DIAGRAM
264