CAV25512 512-Kb SPI Serial CMOS EEPROM Description The CAV25512 is a 512−Kb Serial CMOS EEPROM device internally organized as 64Kx8 bits. This features a 128−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25512 device. The device features software and hardware write protection, including partial as well as full array protection. On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications. http://onsemi.com SOIC−8 V SUFFIX CASE 751BD Features • • • • • • • • • • • • • • Automotive Temperature Grade 1 (−40°C to +125°C) 10 MHz SPI Compatible 2.5 V to 5.5 V Supply Voltage Range SPI Modes (0,0) & (1,1) 128−byte Page Write Buffer Additional Identification Page with Permanent Write Protection Self−timed Write Cycle Hardware and Software Protection Block Write Protection − Protect 1/4, 1/2 or Entire EEPROM Array Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention SOIC and TSSOP 8−lead Packages This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant VCC SI CS CAV25512 WP TSSOP−8 Y SUFFIX CASE 948AL PIN CONFIGURATION CS HOLD WP SCK VSS SI SOIC (V), TSSOP (Y) PIN FUNCTION Pin Name Chip Select SO Serial Data Output WP Write Protect VSS Ground Serial Data Input HOLD SCK Function CS SCK HOLD VCC SO SI SO 1 VCC Serial Clock Hold Transmission Input Power Supply VSS Figure 1. Functional Symbol ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2013 June, 2013 − Rev. 0 1 Publication Order Number: CAV25512/D CAV25512 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Parameter Symbol NEND (Note 3, 4) TDR Endurance Data Retention Min Units 1,000,000 Program / Erase Cycles 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C. 4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D. C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified) Symbol Parameter Test Conditions Min Max Units ICCR Supply Current (Read Mode) Read, SO open, fSCK = 10 MHz 3 mA ICCW Supply Current (Write Mode) Write, CS = VCC 2 mA ISB1 Standby Current VIN = GND or VCC, CS = VCC, WP = VCC, HOLD = VCC, VCC = 5.5 V 3 mA ISB2 Standby Current VIN = GND or VCC, CS = VCC, WP = GND, HOLD = GND, VCC = 5.5 V 5 mA Input Leakage Current VIN = GND or VCC 2 mA ILO Output Leakage Current CS = VCC VOUT = GND or VCC −2 2 mA VIL Input Low Voltage −0.5 0.3VCC V VIH Input High Voltage 0.7VCC VCC + 0.5 V VOL Output Low Voltage IOL = 3.0 mA 0.4 V VOH Output High Voltage IOH = −1.6 mA IL −2 VCC − 0.8V http://onsemi.com 2 V CAV25512 Table 4. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) (Note 2) Test Symbol COUT CIN Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) Min Typ Max Units VOUT = 0 V 8 pF VIN = 0 V 8 pF Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 5) Parameter Symbol Min Max Units 10 MHz fSCK Clock Frequency DC tSU Data Setup Time 10 ns tH Data Hold Time 10 ns tWH SCK High Time 40 ns tWL SCK Low Time 40 ns tLZ HOLD to Output Low Z 25 ns tRI (Note 6) Input Rise Time 2 ms tFI (Note 6) Input Fall Time 2 ms tHD HOLD Setup Time 0 ns tCD HOLD Hold Time 10 ns tV Output Valid from Clock Low 40 tHO Output Hold Time tDIS Output Disable Time 20 ns tHZ HOLD to Output High Z 25 ns tCS CS High Time 40 ns tCSS CS Setup Time 30 ns tCSH CS Hold Time 30 ns tCNS CS Inactive Setup Time 30 tCNH CS Inactive Hold Time 30 tWPS WP Setup Time 10 ns tWPH WP Hold Time 10 ns tWC (Note 7) 0 ns ns Write Cycle Time 5 ms 5. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 6. This parameter is tested initially and after a design or process change that affects the parameter. 7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. Table 6. POWER−UP TIMING (Notes 6, 8) Symbol Parameter Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms 8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. http://onsemi.com 3 CAV25512 Pin Description Functional Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAV25512. CS: The chip select input pin is used to enable/disable the CAV25512. When CS is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAV25512 must be preceded by a high to low transition and concluded with a low to high transition of the CS input. WP: The write protect input pin will allow all write operations to the device when held high. When WP pin is tied low and the WPEN bit in the Status Register (refer to Status Register description, later in this Data Sheet) is set to “1”, writing to the Status Register is disabled. HOLD: The HOLD input pin is used to pause transmission between host and CAV25512, without having to retransmit the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, it is recommended the HOLD input to be tied to VCC, either directly or through a resistor. The CAV25512 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8−bit instruction register. The instruction set and associated op−codes are listed in Table 7. Reading data stored in the CAV25512 is accomplished by simply providing the READ command and an address. Writing to the CAV25512, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later. After a high to low transition on the CS input pin, the CAV25512 will accept any one of the six instruction op−codes listed in Table 7 and will ignore all other possible 8−bit combinations. The communication protocol follows the timing from Figure 2. The CAV25512 features an additional Identification Page (128 bytes) which can be accessed for Read and Write operations when the IPL bit from the Status Register is set to “1”. The user can also choose to make the Identification Page permanent write protected. Table 7. INSTRUCTION SET Instruction Opcode WREN 0000 0110 Enable Write Operations Operation WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory tCS CS tCSS tCNH tWH tWL tCSH tCNS SCK tSU tH tRI tFI VALID IN SI tV tV tDIS tHO SO HI−Z VALID OUT Figure 2. Synchronous Data Timing http://onsemi.com 4 HI−Z CAV25512 Status Register protected sections of memory. While hardware write protection is active, only the non−block protected memory can be written. Hardware write protection is disabled when the WP pin is high or the WPEN bit is 0. The WPEN bit, WP pin and WEL bit combine to either permit or inhibit Write operations, as detailed in Table 10. The IPL (Identification Page Latch) bit determines whether the additional Identification Page (IPL = 1) or main memory array (IPL = 0) can be accessed both for Read and Write operations. The IPL bit is set by the user with the WRSR command and is volatile. The IPL bit is automatically reset after read/write operations. The LIP (Lock Identification Page) bit is set by the user with the WRSR command and is non−volatile. When set to 1, the Identification Page is permanently write protected (locked in Read−only mode). Note: The IPL and LIP bits cannot be set to 1 using the same WRSR instruction. If the user attempts to set (“1”) both the IPL and LIP bit in the same time, these bits cannot be written and therefore they will remain unchanged. The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non−volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read−only. The WPEN (Write Protect Enable) bit acts as an enable for the WP pin. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. This condition prevents writing to the status register and to the block Table 8. STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN IPL 0 LIP BP1 BP0 WEL RDY Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 0 1 C000−FFFF Quarter Array Protection 1 0 8000−FFFF Half Array Protection 1 1 0000−FFFF Full Array Protection Table 10. WRITE PROTECT CONDITIONS WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable http://onsemi.com 5 CAV25512 WRITE OPERATIONS Write Enable and Write Disable The CAV25512 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of the memory location(s) to be written must be outside the protected area, as defined by BP0 and BP1 bits from the status register. The internal Write Enable Latch and the corresponding Status Register WEL bit are set by sending the WREN instruction to the CAV25512. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3. The WREN instruction must be sent prior to any WRITE or WRSR instruction. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write operations by resetting the WEL bit, will protect the device against inadvertent writes. CS SCK 0 SI SO 0 0 0 0 1 1 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) Figure 3. WREN Timing CS SCK SI SO 0 0 0 0 0 1 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) Figure 4. WRDI Timing http://onsemi.com 6 0 CAV25512 Byte Write Following completion of the write cycle, the CAV25512 is automatically returned to the write disable state. Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and a data byte as shown in Figure 5. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). Write Identification Page The additional 128−byte Identification Page (IP) can be written with user data using the same Write commands sequence as used for Page Write to the main memory array (Figure 6). The IPL bit from the Status Register must be set (IPL = 1) using the WRSR instruction, before attempting to write to the IP. The address bits [A15:A7] are Don’t Care and the [A6:A0] bits define the byte address within the Identification Page. In addition, the Byte Address must point to a location outside the protected area defined by the BP1, BP0 bits from the Status Register. When the full memory array is write protected (BP1, BP0 = 1,1), the write instruction to the IP is not accepted and not executed. Also, the write to the IP is not accepted if the LIP bit from the Status Register is set to 1 (the page is locked in Read−only mode). Page Write After sending the first data byte to the CAV25512, the host may continue sending data, up to a total of 128 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previously loaded data. Table 11. BYTE ADDRESS Device Address Significant Bits # Address Clock Pulses Main Memory Array A15 − A0 16 Identification Page A6 − A0 16 CS 0 1 2 3 4 5 6 7 21 8 22 23 24 25 26 27 28 29 30 31 SCK OPCODE SI 0 0 0 0 0 0 DATA IN BYTE ADDRESS* 1 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 AN HIGH IMPEDANCE SO * Please check the Byte Address Table (Table 11) Dashed Line = mode (1, 1) Figure 5. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 21 SCK 0 0 0 0 0 0 23 24−31 32−39 24+(N−1)x8−1 .. 24+(N−1)x8 24+Nx8−1 BYTE ADDRESS* OPCODE SI 22 1 0 AN DATA IN A0 Data Data Data Byte 1 Byte 2 Byte 3 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Data Byte N 7..1 0 * Please check the Byte Address Table (Table 11) Figure 6. Page WRITE Timing http://onsemi.com 7 CAV25512 Write Status Register Write Protection The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3, 4, 6 and 7 can be written using the WRSR command. The Write Protect (WP) pin can be used to protect the Block Protect bits BP0 and BP1 against being inadvertently altered. When WP is low and the WPEN bit is set to “1”, write operations to the Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit is set to “0”. The WP input timing is shown in Figure 8. CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 0 MSB HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Figure 7. WRSR Timing tWPS tWPH CS SCK WP WP Dashed Line = mode (1, 1) Figure 8. WP Timing http://onsemi.com 8 3 CAV25512 READ OPERATIONS Read from Memory Array SO pin. If the CS continues to be held low, the internal address register defined by [A6:A0] bits is automatically incremented and the next data byte from the IP is shifted out. The byte address must not exceed the 128−byte page boundary. To read from memory, the host sends a READ instruction followed by a 16−bit address. After receiving the last address bit, the CAV25512 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAV25512 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the full content of the status register. For easy detection of the internal write cycle completion, both during writing to the memory array and to the status register, we recommend sampling the RDY bit only through the polling routine. After detecting the RDY bit ”0”, the next RDSR instruction will always output the expected content of the status register. Read Identification Page Reading the additional 128−byte Identification Page (IP) is achieved using the same Read command sequence as used for Read from main memory array (Figure 9). The IPL bit from the Status Register must be set (IPL = 1) before attempting to read from the IP. The [A6:A0] are the address significant bits that point to the data byte shifted out on the CS 0 1 2 3 4 5 6 7 8 20 21 10 9 22 23 24 25 26 27 28 29 30 SCK OPCODE SI 0 0 0 0 0 0 BYTE ADDRESS* 1 1 A0 AN DATA OUT HIGH IMPEDANCE SO 7 Dashed Line = mode (1, 1) * Please check the Byte Address Table (Table 11) 6 5 4 3 2 1 0 MSB Figure 9. READ Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK OPCODE SI SO 0 0 0 0 0 DATA OUT HIGH IMPEDANCE MSB Dashed Line = mode (1, 1) Figure 10. RDSR Timing http://onsemi.com 9 3 0 CAV25512 Hold Operation below the POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. The CAV25512 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior to any writes to the device. After power up, the CS pin must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the device goes into a write disable mode. The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op−code will be ignored and the serial output pin (SO) will remain in the high impedance state. The HOLD input can be used to pause communication between host and CAV25512. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During the pause, the data output pin (SO) is tri−stated (high impedance) and SI transitions are ignored. To resume communication, HOLD must be taken high while SCK is low. Design Considerations The CAV25512 device incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ Dashed Line = mode (1, 1) Figure 11. HOLD Timing http://onsemi.com 10 CAV25512 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 11 CAV25512 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM 1.20 A E1 E MAX A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.20 0.65 BSC e L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 12 CAV25512 ORDERING INFORMATION Device Order Number Specific Device Marking CAV25512VE−GT3 CAV25512YE−GT3 Package Type Temperature Range Lead Finish Shipping (Note 11) 25512A SOIC−8, JEDEC −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel S12A TSSOP−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel 9. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 10. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com 11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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