PRELIMINARY CY8C20111, CY8C20121 CapSense Express™ - One Button and Two Button Capacitive Controllers 1. Features 2. Overview ■ Capacitive Button Input tied to a Configurable Output ❐ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor shapes, and sizes ■ Target Applications ❐ Printers ❐ Cellular handsets ❐ LCD monitors ❐ Portable DVD players The CapSense Express™ controllers support two capacitive sensing (CapSense) buttons and two general purpose outputs in CY8C20121 and one CapSense button and one general purpose output in CY8C20111. The device functionality is configured through the I2C port and can be stored in on-board nonvolatile memory for automatic loading at power on. The digital outputs are controlled from CapSense inputs in factory default settings, but are user configurable for direct control through I2C. ■ Industry's Best Configurability ❐ ❐ ❐ ❐ Custom sensor tuning Output supports strong 20 mA sink current Output state can be controlled through I2C or directly from CapSense input state Run time reconfigurable over I2C ■ Advanced Features ❐ Plug-and-play with factory defaults – tuned to support up to 1 mm overlay ❐ Nonvolatile storage of custom settings ❐ Easy integration into existing products – configure output to match system ❐ No external components required ❐ World class free configuration tool ■ Wide Range of Operating Voltages ❐ 2.45V to 2.9V ❐ 3.10V to 3.6V ❐ 4.75V to 5.25V ■ I2C Communication ❐ Supported from 1.8V ❐ Internal pull up resistor support option ❐ Data rate up to 400 kbps. 2 ❐ Configurable I C addressing ■ Industrial Temperature Range: –40°C to +85°C ■ Available in 8-Pin SOIC Package Cypress Semiconductor Corporation Document Number: 001-53516 Rev. ** • The four key blocks that make up the CY8C20111 and CY8C20121 controllers are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, and I2C communications. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense buttons and outputs and permanently store the settings. The standard I2C serial communication interface allows the host to configure the device and read sensor information in real time. I2C address is fully configurable without any external hardware strapping. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 20, 2009 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 3. Pinouts Figure 1. CY8C20111 Pin Diagram - 8 SOIC - 1 Button Table 1. Pin Definitions – 8 SOIC- 1 Button Pin No Name Description 1 VSS 2 I2C SCL I2C Clock 3 I2C SDA I2C Data 4 CS0 CapSense Input 5 NC No Connect 6 DIG0 7 NC 8 VDD Ground Digital Output No Connect Supply Voltage Figure 2. CY8C20121 Pin Diagram – 8 SOIC- 2 Button Table 2. Pin Definitions – 8 SOIC- 2 Button Pin No Name Description 1 VSS 2 I2C SCL I2C Clock 3 I2C SDA I2C Data 4 CS0 CapSense Input 5 CS1 CapSense Input 6 DIG0 Digital Output 7 DIG1 Digital Output 8 VDD Supply Voltage Ground Document Number: 001-53516 Rev. ** Page 2 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 4. Typical Circuits 4.1 Circuit-1: One Button and One LED[1] 4.2 Circuit-2: One Button and One LED with I2C Interface Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev. ** Page 3 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 4.3 Circuit-3: Two Buttons and Two LEDs with I2C Interface 4.4 Circuit-4: Compatibility with 1.8V I2C Signaling[2] Note 2. 1.8V < VDD_I2C < VDD_CE and 2.4V < VDD_CE < 5.25V. Document Number: 001-53516 Rev. ** Page 4 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 4.5 Circuit-5: Powering Down CapSense Express Device for Low Power Requirements Output enable Output LDO VDD I2C Pull UPs LED Master Or Host CapSense Express SDA I2C BUS SCL For low power requirements, if Vdd is to be turned off, the above concept can be used. The Vdds of CapSense Express, I2C pull ups, and LEDs must be from the same source. Turning off the Vdd ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins can cater to the power supply requirement of the circuit, the LDO can be avoided. 5. Operating Modes 6. I2C Interface The CapSense Express devices support the industry standard I2C protocol, which can be used to: ■ Configure the device ■ Read the status and data registers of the device ■ Control device operation ■ Execute commands 5.1 Normal Mode The I2C address can be modified during configuration. In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access. Writing to these registers can be done only in setup mode. 6.1 I C Device Addressing 5.2 Setup Mode 2 The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending one byte address; first 7-bit contains address and LSb indicates the data transfer direction. Zero in the LSb indicates the write transaction form master and one indicates read transfer by the master. Table 3 shows example for different I2C addresses. All registers have read and write access (except those which are read only) in this mode. The acknowledgment times are longer compared to normal mode. When CapSense scanning is disabled (command code 0x0A in command register 0xA0), the acknowledgment times can be improved to values similar to the normal mode of operation. Table 3. I2C Addresses 7 Bit Slave Address (in Dec) D7 D6 D5 D4 D3 D2 D1 D0 8 Bit Slave Address (in Hex) 1 0 0 0 0 0 0 1 0(W) 02 1 0 0 0 0 0 0 1 1(R) 03 75 1 0 0 1 0 1 1 0(W) 96 75 1 0 0 1 0 1 1 1(W) 97 Document Number: 001-53516 Rev. ** Page 5 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 6.2 I2C Clock Stretching “Clock stretching” or “bus stalling” in I2C communication protocol is a state in which the slave holds the SCL line low to indicate that it is busy. In this condition, the master is expected to wait until the SCL is released by the slave. When an I2C master communicates with the CapSense Express device, the CapSense Express stalls the I2C bus after the reception of each byte (that is, just before the ACK/NAK bit) until processing of the byte is complete and critical internal functions are executed. Use a fully I2C compliant master to communicate with the CapSense Express device. An I2C master which does not support clock stretching (a bit banged software I2C Master) must wait for a specific amount of time specified (as shown in the section Format for Register Write and Read) for each register write and read operation before the next bit is transmitted. It is mandatory to check the SCL status (it should be high) before I2C master initiates any data transfer with CapSense Express. If the master fails to do so and continues to communicate, the communication is erroneous. The following diagrams represent the ACK time delays shown in the Register Map on page 7. Figure 3. Write ACK Time Representation Figure 4. Read ACK Time Representation 6.3 Format for Register Write and Read Register write format. Start Slave Addr + W A Reg Addr A Data A Register read format. Start Slave Addr + W Start Slave Addr + R A A Reg Addr Data A A Stop Data A Legends: Master Slave Data ..... A ..... Data Data N A Stop Stop A - ACK N- NAK 7. Registers Table 4. Register Conventions Convention RW R WPR FD Description Register have both read and write access Register have only read access Write register with pass code Factory defaults Document Number: 001-53516 Rev. ** Page 6 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Table 5. Register Map Writable Only in Setup Mode[3] Factory Default Values of Registers (in Hex) I2C Max ACK Time in Normal Mode (ms)[5] Register Address (in Hex) Access OUTPUT_PORT 04 W CS_ENABLE 07 RW DIG_ENABLE 08 RW SET_STRONG_DM 11 RW OP_SEL_0 1C RW LOGICAL_OPR_INPUT0 1E RW OP_SEL_1[4] 21 RW LOGICAL_OPR_INPUT1[4] 23 RW CS_NOISE_TH 4E RW CS_BL_UPD_TH 4F RW CS_SETL_TIME 50 RW Yes CS_OTH_SET 51 RW Yes 00 00 CS_HYSTERISIS 52 RW 0A 0A 0.11 CS_DEBOUNCE 53 RW 03 03 CS_NEG_NOISE_TH 54 RW 14 14 CS_LOW_BL_RST 55 RW 14 CS_FILTERING 56 RW 20 CS_SCAN_POS_0 5C RW Yes 00 CS_SCAN_POS_1[4] 5D RW Yes CS_FINGER_TH_0 66 RW CS_FINGER_TH_1[4] 67 RW CS_IDAC_0 70 RW CS_IDAC_1[4] 71 RW I2C_ADDR_LOCK 79 RW DEVICE_ID 7A R Name I2C Max ACK Time in Setup Mode (ms)[5] Page No. 1 Button 2 Button 01 03 Yes 01 03 11 9 Yes 01 03 11 10 Yes 01 03 11 10 82 82 0.12 11 12 01 01 0.12 11 12 82 0.12 11 12 02 0.12 11 12 28 0.11 11 13 64 64 0.11 A0 A0 28 64 0.10 9 11 13 35 13 35 14 11 14 0.11 11 15 0.11 11 15 14 0.11 11 15 20 0.11 11 16 00 11 16 01 11 16 64 0.14 11 17 64 0.14 11 17 0A 0.14 11 17 0A 0.14 11 17 00 00 0.11 11 17 11 21 0.11 11 18 0A DEVICE_STATUS 7B R 03 03 0.11 11 18 I2C_ADDR_DM 7C RW 00 00 0.11 11 19 CS_READ_BUTTON 81 RW 00 00 0.12 11 19 CS_READ_BLM 82 R 00 00 0.12 11 20 CS_READ_BLL 83 R 00 00 0.12 11 20 CS_READ_DIFFM 84 R 00 00 0.12 11 20 CS_READ_DIFFL 85 R 00 00 0.12 11 20 CS_READ_RAWM 86 R 00 00 0.12 11 20 CS_READ_RAWL 87 R 00 00 0.12 11 20 CS_READ_STATUS 88 R 00 00 0.12 11 21 COMMAND_REG A0 W 00 00 0.10 11 21 Notes 3. These registers are writable only after entering into setup mode. All other registers are available for read and write in normal and setup mode. 4. These registers are available only in CY8C20121 device. 5. The Ack times specified are 1x I2C Ack times. Document Number: 001-53516 Rev. ** Page 7 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Table 6. CapSense Express Commands Command [5] W 00 A0 00 Executable Mode Description Duration the Device is NOT Accessible after ACK (in ms)[5] Get firmware revision Setup/Normal 0 W 00 A0 01 Store current configuration to NVM Setup/Normal 120 W 00 A0 02 Restore factory configuration Setup/Normal 120 W 00 A0 03 Write NVM POR defaults Setup/Normal 120 W 00 A0 04 Read NVM POR defaults Setup/Normal 5 W 00 A0 05 Read current configurations (RAM) Setup/Normal 5 W 00 A0 06 Reconfigure device (POR) Setup 5 W 00 A0 07 Set Normal mode of operation Setup/Normal 0 W 00 A0 08 Set Setup mode of operation Setup/Normal 0 W 00 A0 09 Start scan Setup/Normal 10 W 00 A0 0A Stop scan Setup/Normal 5 W 00 A0 0B Get CapSense scan status Setup/Normal 0 Note 6. ‘W’ indicates the write transfer. The next byte of data represents the 7 bit I2C address. Document Number: 001-53516 Rev. ** Page 8 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.1 OUTPUT_PORT Output Port Register OUTPUT_PORT: 04h 1 Button 7 6 5 4 3 2 1 0 Access: FD W:01 Bit Name DIG[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD W:03 Bit Name DIG[1:0] This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be changed using this register. Bit Name Description 1:0 DIG [1:0] A bit set in this register sets the logic level of the output. 0 Logic ‘0’ 1 Logic ‘1’ 7.2 CS_ENABLE Select CapSense Input Register CS_ENABLE: 07h (Writable only in Setup mode) 1 Button 7 6 5 4 3 2 1 0 Access: FD RW:01 Bit Name CS[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD RW:03 Bit Name CS[1:0] This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. Bit Name Description 1:0 CS [1:0] These bits are used to enable CapSense inputs. 0 Disable CapSense input 1 Enable CapSense input Document Number: 001-53516 Rev. ** Page 9 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.3 DIG_ENABLE Select DIG Output Register GPO_ENABLE: 08h (Writable only in Setup mode) 1 Button 7 6 5 4 3 2 1 0 Access: FD RW:01 Bit Name DIG[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD RW:03 Bit Name DIG [1:0] This register is used to enable DIG (Digital) outputs. If DIG output is enabled, the strong drive mode register (11h) should also be set. If DIG output is disabled the drive mode of these pins is High Z. Bit Name Description 1:0 DIG [1:0] These bits are used to enable DIG outputs. 0 Disable DIG output 1 Enable DIG output 7.4 SET_STRONG_DM Sets Strong Drive Mode for DIG Outputs. SET_STRONG_DM: 11h (Writable only in Setup mode) 1 Button 7 6 5 4 3 2 1 0 Access: FD RW:01 Bit Name DM [0] 2 Button 7 6 5 4 3 2 1 0 Access: FD RW:03 Bit Name DM [1:0] This register sets strong drive mode for DIG (Digital) outputs. To set strong drive mode the pin should be enabled as GP output. Bit Name Description 1:0 DM [1:0] These bits are used to set the strong drive mode to DIG outputs. 0 Strong drive mode not set 1 Strong drive mode set Document Number: 001-53516 Rev. ** Page 10 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Figure 5. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] LOGICAL_OPR_INPUT0 [0] A INVERSION LOGIC ENB AND / OR Logic selection CS0 DIG0 B S OP_SEL_0 [0] OP_SEL_0 [7] OP_SEL_0 [1] Figure 6. CY8C20121 Digital Logic Diagram LOGICAL_OPR_INPUTx [0] OUTPUT_PORT [x] ENB A CS0 A LOGICAL_OPR_INPUTx [1] ENB INVERSION LOGIC AND / OR Logic selection AND / OR Logic selection DIGx B S B S CS1 OP_SEL_x [7] OP_SEL_x [0] OP_SEL_x [1] INPUT SELECTION LOGIC Document Number: 001-53516 Rev. ** Page 11 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.5 OP_SEL_x Logic Operation Selection Registers OP_SEL_0: 1Ch OP_SEL_1: 21h (Not available for 1 Button) 1/2Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW: 0 RW: 0 RW: 0 Op_En InvOp Operator This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to get the logic operation output on DIG0 output and OP_SEL_1 for DIG1 output. Write to these registers during the disable state of respective DIG output pins does not have any effect. The input to the logic operation can be selected in LOGIC_OPRX registers. The selected inputs can be ORed or ANDed. The output of logic operation can also be inverted. Bit Name 7 Op_En 1 InvOp 0 Operator Description This bit enables or disables logic operation. 0 Disable logic operation 1 Enable logic operation This bit enables or disables logic operation output inversion. 0 Logic operation output not inverted 1 Logic operation output inverted This bit selects which operator should be used to compute logic operation. 0 Logic operator OR is used on inputs 1 Logic operator AND is used on inputs 7.6 LOGICAL_OPR_INPUTx Selects Input for Logic Operation LOGICAL_OPR_INPUT0: 1Eh LOGICAL_OPR_INPUT0 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name 7 LOGICAL_OPR_INPUT1: 23h (Not available for 1 button) 6 5 4 3 2 1 0 RW:01 CSL[0] 6 5 4 3 2 1 0 RW:01 CSL [1:0] LOGICAL_OPR_INPUT1 2 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:02 CSL [1:0] These registers are used to give the input to logic operation block. The inputs can be only CapSense input status. Bit Name Description 1:0 CSL [1:0] These bits selects the input for logic operation block. Document Number: 001-53516 Rev. ** Page 12 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.7 CS_NOISE_TH Noise Threshold Register CS_NOISE_TH: 4Eh 1/2 Button 7 6 5 4 3 Access: FD RW:28 Bit Name NT[7:0] 2 1 0 This register sets the noise threshold value. For individual sensors, count values above this threshold do not update the baseline. This count is relative to baseline. This parameter is common for all sensors. The range is 3 to 255 and it should satisfy the equation NT < Min (Finger Threshold – Hysteresis – 5). Recommended value is 40% of finger threshold. Bit Name Description 7:0 NT [7:0] These bits are used to set the noise threshold value. 7.8 CS_BL_UPD_TH Baseline Update Threshold Register CS_BL_UPD_TH: 4Fh 1/2 Button 7 6 5 4 3 Access: FD RW:64 Bit Name BLUT[7:0] 2 1 0 When the new raw count value is above the current baseline and the difference is below the noise threshold, the difference between the current baseline and the raw count is accumulated into a “bucket.” When the bucket fills, the baseline increments and the bucket is emptied. This parameter sets the threshold that the bucket must reach for the baseline to increment. In other words, lower value provides faster baseline update rate and vice versa. This parameter is common for all sensors. The range is 0 to 255. Bit Name 7:0 BLUT [7:0] Description These bits set the threshold that the bucket must reach for baseline to increment. 7.9 CS_SETL_TIME Settling Time Register CS_SETL_TIME: 50h (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name 6 5 4 3 RW:A0 STLNG_TM[7:0] 2 1 0 The settling time parameter controls the duration of the capacitance-to-voltage conversion phase. The parameter setting controls a software delay that allows the voltage on the integrating capacitor to stabilize. This parameter is common for all sensors. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. The range is 2 to 255. Bit Name 7:0 STLNG_TM [7:0] Document Number: 001-53516 Rev. ** Description These bits are used to set the settling time value. Page 13 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.10 CS_OTH_SET CapSense Clock Select, Sensor Auto Reset Register CS_OTH_SET: 51h (Writable only in Setup mode) 1/2 Button 7 6 5 4 3 Access: FD RW: 00 RW: 0 Bit Name CS_CLK[1:0] Sns_Ar 2 1 0 The registers set the CapSense module frequency of operation and enables or disables the sensor auto reset. CS_CLK bits provides option to select variable clock input for the CapSense block. A sensor design having higher paratactic requires lower clock for better performance and vice versa. Sensor Auto Reset determines whether the baseline is updated at all times or only when the signal difference is below the noise threshold. When set to ‘1’ (enabled), the baseline is updated constantly. This setting limits the maximum time duration of the sensor, but it prevents the sensors from permanently turning on when the raw count suddenly rises without anything touching the sensor. This sudden rise can be caused by a large power supply voltage fluctuation, a high energy RF noise source, or a very quick temperature change. When the parameter is set to ‘0’ (disabled), the baseline is updated only when raw count and baseline difference is below the noise threshold parameter. This parameter may be enabled unless there is a demand to keep the sensors in the on state for a long time. This parameter is common for all sensors. Bit Name Description 6:5 CS_CLK[1:0] These bits selects the CapSense clock. CS_CLK[1:0] 00 01 10 11 3 Sns_Ar Frequency of Operation IMO IMO/2 IMO/4 IMO/8 This bit is used to enable or disable sensor auto reset. 0 Disable Sensor auto reset 1 Enable Sensor auto reset 7.11 CS_HYSTERISIS Hysteresis Register CS_HYSTERISIS: 52h 1/2 Button 7 6 5 4 3 Access: FD RW:0A Bit Name HYS[7:0] 2 1 0 The Hysteresis parameter adds to or subtracts from the finger threshold depending on whether the sensor is currently active or inactive. If the sensor is off, the difference count must overcome the ‘finger threshold + hysteresis’. If the sensor is on, the difference count must go below the ‘finger threshold – hysteresis’. It is used to add debouncing and “stickiness” to the finger detection algorithm. This parameter is common for all sensors. Possible values are 0 to 255. However, the setting must be lower than the finger threshold parameter setting. Recommended value for hysteresis is 15 percent of finger threshold. Bit Name 7:0 HYS [7:0] Document Number: 001-53516 Rev. ** Description These bits are used to set the hysteresis value. Page 14 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.12 CS_DEBOUNCE Debounce Register. CS_DEBOUNCE: 53h 1/2 Button 7 6 5 4 3 Access: FD RW:0A Bit Name DB[7:0] 2 1 0 The Debounce parameter adds a debounce counter to the ‘sensor active transition’. For the sensor to transition from inactive to active, the consecutive samples of difference count value must stay above the ‘finger threshold + hysteresis’ for the number specified. This parameter is common for all sensors. Possible values are 1 to 255. A setting of ‘1’ provides no debouncing. Bit Name 7:0 DB [7:0] Description These bits are used to set the debounce value. 7.13 CS_NEG_NOISE_TH Negative Noise Threshold Register CS_NEG_NOISE_TH: 54h 1/2 Button 7 6 5 4 3 Access: FD RW:0A Bit Name NNT[7:0] 2 1 0 This parameter adds a negative difference count threshold. If the current raw count is below the baseline and the difference between them is greater than this threshold, the baseline is not updated. However, if the current raw count stays in the low state (difference greater than the threshold) for the number of samples specified by the Low Baseline Reset parameter, the baseline is reset. This parameter is common for all sensors. Bit Name 7:0 NNT [7:0] Description These bits are used to set the negative noise value. 7.14 CS_LOW_BL_RST Low Baseline Reset Register CS_LOW_BL_RST: 55h 1/2 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:0A LBR[7:0] This parameter works together with the Negative Noise Threshold parameter. If the sample count values are below the baseline minus the negative noise threshold for the specified number of samples, the baseline is set to the new raw count value. It essentially counts the number of abnormally low samples required to reset the baseline. It is generally used to correct the finger-on-at-startup condition. This parameter is common for all sensors. Bit Name 7:0 LBR [7:0] Document Number: 001-53516 Rev. ** Description These bits are used to set the Low Baseline Reset value. Page 15 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.15 CS_FILTERING CapSense Filtering Register CS_FILTERING: 56h 1/2 Button 7 Access: FD RW: 0 RstBl Bit Name 6 5 RW: 1 I2C_DS 4 RW: 0 Avg_En 3 2 1 0 RW: 00 Avg_Order[1:0] This register provides an option for forced baseline reset and to enable and configure two different types of software filters. Bit Name 7 RstBl 5 I2C_DS 4 Avg_En [1:0] Description This bit resets all the baselines and it is auto cleared to ‘0’. 0 All Baselines are not reset 1 All baselines are reset When this bit is set to ‘1’ the CapSense scan sample is dropped if I2C communication was active during scanning. 0 Disable the I2C drop sample filer 1 Enable the I2C drop sample filter This bit enables average filter on raw counts. 0 Disable the average filter 1 Enable the average filter These bits are used to select the number of CapSense samples to average: Avg_Order[1:0] Avg_Order[1:0] in Hex 00 01 10 11 Samples to Average 2 4 8 16 7.16 CS_SCAN_POS_x Scan Position Registers CS_SCAN_POS_0: 5Ch (Writable only in Setup mode) 1/2 Button 7 6 5 4 3 2 1 0 Access: FD RW: 0 Bit Name Scan_Pstn CS_SCAN_POS_1: 5Dh (Not available for 1 Button) (Writable only in Setup mode) 2 Button 7 6 5 4 3 2 1 0 Access: FD RW: 1 Bit Name Scan_Pstn This register is used to set the position of the sensors in the switch table for proper scanning sequence because the CapSense sensors are scanned in sequence. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit Name 0 Scan_Pstn Document Number: 001-53516 Rev. ** Description This bit sets the scan position. Page 16 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.17 CS_FINGER_TH_x Finger Threshold Registers CS_FINGER_TH_0: 66h 1/2 Button CS_FINGER_TH_1: 67h (Not available in 1 Button) 7 6 5 4 3 Access: FD RW: 64 Bit Name FT[7:0] 2 1 0 This register sets the finger threshold value for CapSense inputs. Possible values are 3 to 255. This parameter should be configured individually for each CapSense inputs. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit Name [7:0] FT [7:0] Description These bit set the finger threshold for CapSense inputs. 7.18 CS_IDAC_x IDAC Setting Registers CS_IDAC_0: 70h CS_IDAC_1: 71h (Not available in 1 Button) 1/2 Button 7 6 5 4 3 Access: FD RW: 0A Bit Name IDAC[7:0] 2 1 0 The IDAC register controls the sensitivity of the CapSense algorithm. This register is used to tune the CapSense input for specific design or overlays. Decreasing the value of this register increases the sensitivity of the CapSense buttons and vice versa. Decreasing the value of IDAC increases noise and vice versa. Possible values are 1 to 255. If the value is set to 0 then the value is reset to default value 10. The recommended value is greater than 4. Setting value < 4 creates excessive amount of noise. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit Name [7:0] Description IDAC [7:0] These bit set the IDAC values. 7.19 I2C_ADDR_LOCK I2C Address Lock Registers I2C_ADDR_LOCK: 79h 1/2 Button 7 6 5 4 3 2 Access: FD 1 0 WPR: 0 I2CAL Bit Name 2 2 This register is used to unlock and lock the I C address register (7Ch) access. The device I C address should be modified by writing new address to register 7Ch after unlocking the access using this register. Write to the 7C register during the locked state does not have any effect and the new address take effect only after the access is locked. To lock or unlock the I2C AL bit, the following three bytes must be written to register 79h: ■ unlock I2CAL: 3Ch A5h 69h ■ lock I2CAL: 96h 5Ah C3h Reading the I2CAL bit from register 79h indicates the current access state. Bit Name 0 I2CAL Document Number: 001-53516 Rev. ** Description This bit gives the lock/unlock status of I2C address. 0 Unlocked 1 Locked Page 17 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.20 DEVICE_ID Device ID Register DEVICE_ID: 7Ah 1 Button Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 R: 11 DEV_ID[7:0] 2 1 0 7 6 5 4 2 1 0 3 R: 21 DEV_ID[7:0] This register contains the device and product ID. The device and product ID corresponds to “xx” in CY8C201xx. Bit Name 7:0 DEV_ID [7:0] Description These bits contain the device and product ID. Part No CY8C20111 CY8C20121 Device/Product ID 11 21 7.21 DEVICE_STATUS Device Status Register DEVICE_STATUS: 7Bh 1/2 Button 7 6 Access: FD R : 00 Bit Name Ip_Volt[1:0] 5 R: 0 IRES 4 R:0 Load_FD 3 R: 0 No_NVM_Wr 2 1 R: 0 CSE 0 R: 0 DIGE This register contains the device status. Bit Name 7:6 Ip_Volt [1:0] Description Supply voltage is automatically detected and these bits are set accordingly. Ip_Volt[1:0] 00 01 10 11 5 IRES 4 Load_FD 3 No_NVM_Wr 1 CSE 0 DIGE Document Number: 001-53516 Rev. ** Supply Voltage 5 3.3 2.7 Reserved When set to ‘1’, this bit indicates that an internal reset occurred. 0 indicates the last system reset was not internal reset 1 indicates the last system reset was internal reset This bit indicates whether factory defaults are loaded during power up. 0 User default configuration is loaded during power up 1 Factory default configuration is loaded during power up When set to ‘1’, this bit indicates that the supply voltage applied to the device Is too low for a write to nonvolatile memory operation, and no write is performed. This bit must be checked before any Store or Write POR command. This bit indicates whether CapSense function is enabled or disabled. 0 Functionality of CapSense block is disabled 1 Functionality of CapSense block is enabled This bit indicates whether GP Output function is enabled or disabled. 0 Functionality of Digital output block is disabled 1 Functionality of Digital output block is enabled Page 18 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.22 I2C_ADDR_DM Device I2C Address and I2C Pin Drive Mode Register I2C_ADDR_DM: 7Ch 1 Button 7 6 5 4 3 2 Access: FD RW: 0 RW: 00 Bit Name I2CIP_EN I2C_ADDR[6:0] 1 0 This register sets the drive mode of I2C pins and I2C slave address. To write to this register, register 79h must first be unlocked. The value written to register 7Ch is applied only after locking register 79h again. Bit Name 7 I2CIP_EN 6:0 I2C_ADDR [6:0] Description This bit is used to set the I2C pins drive mode. 0 Internal pull up enabled 1 Internal pull up disabled Used to set the device I2C address. 7.23 CS_READ_BUTTON Button Select Register I2C_ADDR_DM: 81h 1 Button 7 6 5 4 3 2 1 0 Access: FD RW: 0 RW: 0 Bit Name RD_EN CSBN[0] 2 Button 7 Access: FD RW: 0 RW: 00 Bit Name RD_EN CSBN[1:0] 6 5 4 3 2 1 0 The scan result of a CapSense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h-87h registers. This register is used to select a CapSense input to read the raw count, difference count, and baseline. Only the pins defined as CapSense inputs in register 07h can be used with this register. Trying to select other pins not defined as CapSense does not have any change. Bit Name 7 RD_EN 1:0 CSBN [1:0] Description This bit enables the CapSense raw data reading. 0 Disable CapSense scan result reading 1 Enable CapSense scan result reading These bits decide which CapSense button scan result are read. When writing to this register, the bitmask must contain only one bit set to ’1’, otherwise the data is discarded. CSBN [1:0] 01 10 Document Number: 001-53516 Rev. ** CapSense Button No 1 2 Page 19 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.24 CS_READ_BLx Baseline Value MSB/LSB Registers CS_READ_BLM: 82h 1/2 Button CS_READ_BLL: 83h 7 6 5 4 3 Access: FD R: 00 Bit Name BL [7:0] 2 1 0 1 0 Reading from this register returns the 2-byte current baseline value for the selected CapSense input. Bit Name 7:0 BL [7:0] Description These bits represent the baseline value. 7.25 CS_READ_DIFFx Difference Count Value MSB/LSB Registers CS_READ_DIFFM: 82h 1/2 Button 7 CS_READ_DIFFL: 83h 6 5 4 3 Access: FD R: 00 Bit Name DIF [7:0] 2 Reading from this register returns the 2-byte current difference count for the selected CapSense input. Bit Name Description 7:0 DIF [7:0] These bits represent the sensor difference count. 7.26 CS_READ_RAWx Difference Count Value MSB/LSB Registers CS_READ_RAWM: 82h 1/2 Button 7 CS_READ_RAWL: 83h 6 5 4 3 Access: FD R: 00 Bit Name RC [7:0] 2 1 0 Reading from this register returns the 2-byte current raw count value for the selected CapSense input. Bit Name 7:0 RC [7:0] Document Number: 001-53516 Rev. ** Description These bits represent the raw count value. Page 20 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.27 CS_READ_STATUS Sensor On Status Register CS_READ_STATUS: 88h 1 Button 7 6 5 4 3 2 1 0 Access: FD R: 0 Bit Name BT_ST[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD R: 00 Bit Name BT_ST[1:0] This register gives the sensor ON/OFF status. A bit ‘1’ indicates sensor is ON and ‘0’ indicates sensor is OFF. Bit Name Description 1:0 BT_ST [1:0] These bits used to represent sensor status. 0 Sensor OFF 1 Sensor ON 7.28 COMMAND_REG Command Register COMMAND_REG: A0h 1/2 Button 7 6 5 4 3 Access: FD W: 00 Bit Name Cmnd [7:0] 2 1 0 Commands are executed by writing the command code to the command register. Bit Name 7:0 Cmnd [7:0] Command Code Description Refer to the following table for command register opcodes. Name Description 00h Get Firmware Revision The I2C buffer is loaded with the one byte firmware revision value. Reading one byte after writing this command returns the firmware revision. The upper nibble of the firmware revision byte is the major revision number and the lower nibble is the minor revision number. 01h Store Current Configuration to NVM The current register settings are saved in nonvolatile memory (Flash). This setting is automatically loaded after the next device reset/power up or if the Reconfigure Device (06h) command is issued. 02h Restore Factory Configuration Replaces the saved user configuration with the factory default configuration. Current settings are unaffected by this command. New settings are loaded after the next device reset/power up or if the 06h command is issued. 03h Write POR Defaults Sends new power up defaults to the CapSense controller without changing current settings unless the 06h command is issued afterwards. This command is followed by 123 data bytes according to the POR Default Data Structure table. The CRC is calculated as the XOR of the 122 data bytes (00h-79h). If the CRC check fails or an incomplete block is sent, the slave responds with an ACK and the data is NOT saved to Flash. To define new POR defaults: Document Number: 001-53516 Rev. ** ■ Write command 03h ■ Write 122 data bytes with new values of registers (use the _flash.iic file generated from s/w tool) ■ Write one CRC byte calculated as XOR of previous 122 data bytes Page 21 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Command Code 04h 05h Name Read POR Defaults Read Device Configuration (RAM) Description Reads the POR settings stored in the nonvolatile memory. To read POR defaults: ■ Write command 04h ■ Read 122 data bytes ■ Read one CRC byte Reads the current device configuration. Gives the user "flat-address-space" access to all device settings. To read device configuration: ■ Write command 05h ■ Read 122 data bytes ■ Read one CRC byte 06h Reconfigure Device (POR) Immediately reconfigures the device with actual POR defaults from Flash. Has the same effect on the registers as a POR. This command can only be executed in setup operation mode (command code 08). 07h Set Normal Operation Mode Sets the device in normal operation mode. In this mode, CapSense pin assignments cannot be modified; settling time, IDAC setting, external capacitor, and sensor auto-reset also cannot be modified. 08h Set Setup Operation Mode Sets the device in setup operation mode. In this mode, CapSense pin assignments can be changed along with other parameters. 09h Start CapSense Scanning Allows the user to start CSA scanning after it has been stopped using command 0x0A. Note that at POR, scanning is enabled and started by default if one or more sensors are enabled. 0Ah Stop CapSense Scanning Allows the user to stop CSA scanning. A system host controller might initiate this command before powering down the device to make sure that during power down no CapSense touches are detected. When CSA scanning is stopped by the user and the device is still in the valid VCC operating range, the following behavior is supported: 0Bh Returns CapSense Scanning Status Document Number: 001-53516 Rev. ** ■ Any change to configuration can still be done (as long as VCC is in operating range). ■ Command code 0x06 overrides the status of stop/scan by enabling and starting CSA scanning if one or more sensors are enabled. ■ CapSense read-back values return 0x00. The I2C buffer is loaded with the one-byte CSA scanning status value. After writing the value 0Bh to the A0h register, reading one byte returns the CSA scanning status. It returns the LVD_STOP_SCAN and STOP_SCAN bits. LVD_STOP_SCAN is bit 3 - Set when CSA is stopped because VCC is outside the valid operating range. STOP_SCAN is bit 2 - Set when CSA is stopped by the user by writing command 0x0A. Page 22 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 8. Layout Guidelines and Best Practices Sl. No. Category Min Max Recommendations/Remarks 1 Button Shape 2 Button Size 5 mm 3 Button Button Spacing = Button Ground Clearance 4 Button Ground Clearance 0.5 mm 5 Ground Flood - Top Layer Hatched ground 7 mil trace and 45 mil grid (15% filling) 6 Ground Flood - Bottom Layer Hatched ground 7 mil trace and 70 mil grid (10% filling) 7 Trace Length from Sensor to PSoC - Buttons 8 Trace Width 9 Trace Routing Traces should be routed on the non sensor side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal. 10 Via Position for the Sensors Via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 11 Via Hole Size for Sensor Traces 12 No. of Via on Sensor Trace 13 CapSense Series Resistor Placement 14 Distance between any CapSense Trace to Ground Flood 15 Device Placement Mount the device on the layer opposite to sensor. The CapSense trace length between the device and sensors should be minimum 16 Placement of Components in 2 Layer PCB Top layer-sensor pads and bottom layer-PSoC, other components and traces. 17 Placement of Components in 4 Layer PCB Top layer-sensor pads, second layer – CapSense traces, third layer-hatched ground, bottom layer- PSoC, other components and non CapSense traces 18 Overlay Thickness - Buttons 19 Overlay Material Should to be non conductive material. Glass, ABS Plastic, Formica 20 Overlay Adhesives Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are recommended. 21 LED Back Lighting Cut a hole in the sensor pad and use rear mountable LEDs. Refer Example PCB Layout Design with Two CapSense Buttons and Two LEDs on page 26. 22 Board Thickness Standard board thickness for CapSense FR4 based designs is 1.6 mm. Document Number: 001-53516 Rev. ** Solid round pattern, round with LED hole, rectangle with round corners 0.17 mm 15 mm 10 mm 8 mm 2 mm Button ground clearance = Overlay Thickness 200 mm < 100 mm. 0.20 mm 0.17 mm (7 mil) 10 mil 1 10 mil 0 mm 2 1 10mm Place CapSense series resistors close to PSoC for noise suppression.CapSense resistors have highest priority place them first. 20 mil 20 mil 2 mm 1 mm Page 23 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Figure 7. Button Shapes Figure 8. Button Layout Design X: Button to ground clearance Y: Button to button clearance Figure 9. Recommended Via-hole Placement Document Number: 001-53516 Rev. ** Page 24 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 8.1 Example PCB Layout Design with Two CapSense Buttons and Two LEDs Figure 10. Top Layer Figure 11. Bottom Layer Document Number: 001-53516 Rev. ** Page 25 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 9. Operating Voltages For details on I2C 1x Ack time, refer Register Map on page 7 and CapSense Express Commands on page 8. I2C 4x Ack time is approximately four times the values mentioned in these tables. 10. CapSense Constraints Parameter Min Typ Parasitic Capacitance (CP) of the CapSense Sensor Overlay Thickness Supply Voltage Variation (VDD) Document Number: 001-53516 Rev. ** 0 1 Max Units 30 pF 2 mm Notes All layout best practices followed, properly tuned and noise free condition. ± 5% Page 26 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 11. Electrical Specifications 11.1 Absolute Maximum Ratings Parameter Description Min Typ Max Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C (0°C to 50°C). Extended duration storage temperatures above 65°C degrade reliability TSTG Storage temperature –55 25 +100 °C TA Ambient temperature with power applied –40 – +85 °C VDD Supply voltage on VDD relative to VSS –0.5 – +6.0 V VIO DC input voltage VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tri-state VSS – 0.5 – VDD + 0.5 V IMIO Maximum current into any GPIO pin –25 – +50 mA ESD Electro static discharge voltage 2000 – – V LU Latch up current – – 200 mA Human body model ESD 11.2 Operating Temperature Min Typ Max Unit TA Parameter Ambient temperature Description –40 – +85 °C TJ Junction temperature –40 – +100 °C Document Number: 001-53516 Rev. ** Notes Page 27 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 11.3 DC Electrical Characteristics 11.3.1 DC Chip Level Specifications Parameter Description Min Typ Max Unit VDD Supply voltage 2.40 – 5.25 V IDD Supply current – 1.5 2.5 mA Notes Conditions are VDD = 3.10V, TA = 25°C 11.3.2 5V and 3.3V DC General Purpose I/O Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C<TA<85°C, 3.10V to 3.6V -40°C<TA<85°C. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Parameter Description Min Typ Max Unit – – V VOH1 High output voltage VDD – 0.2 Notes IOH < 10 µA/pin, VDD > 3.10V VOH2 High output voltage VDD – 0.9 – – V IOH = 1 mA/pin, VDD > 3.10V VOL Low output voltage – – 0.75 V IOL = 20 mA/pin, VDD > 3.10V, maximum of 40 mA sink current COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. 11.3.3 2.7 DC General Purpose I/O Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.90V and -40°C<TA<85°C, respectively. Typical parameters apply to 2.7V at 25°C and are for design guidance only. Min Typ Max Unit VOH1 Parameter High output voltage Description VDD – 0.2 – – V IOH < 10 µA/pin Notes VOH2 High output voltage VDD – 0.5 – – V IOH = 0.2 mA/pin VOL Low output voltage – – 0.75 V IOL = 10 mA/pin, maximum of 20 mA sink current COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. 11.3.4 2.7V DC Spec for I2C Line with 1.8V External Pull-Up This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.9V and 3.10V to 3.60V, and -40°C<TA <85°C, respectively. Typical parameters apply to 2.7V at 25°C. The I2C lines drive mode must be set to open drain and pulled up to 1.8V externally. Parameter Description Min Typ Max Unit Notes – – 0.4 V IOL=5 mA/pin, maximum of 10 mA device sink current 2.4<VDD <2.9V and 3.1<VDD <3.6V. VOLP Low output voltage VIL Input low voltage – – 0.75 V VDD = 2.4 to 2.90V and 3.10V to 3.6V. VIH Input high voltage 1.4 – – V VDD = 2.4 to 2.7V. 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. 4 5.6 8 kΩ Min Typ Max Unit – – 2.36 2.60 2.40 2.65 V V 2 CI2C Capacitive load on I C pins RPU Pull up resistor 11.3.5 DC POR and LVD Specifications Parameter VPPOR0 VPPOR1 Description VDD Value for PPOR Trip VDD= 2.7V VDD= 3.3V, 5V Document Number: 001-53516 Rev. ** Notes VDD must be greater than or equal to 2.5V during startup or reset from watchdog. Page 28 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 11.3.6 DC Flash Write Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C<TA<85°C, 3.10V to 3.6V and -40°C<TA<85°C or 2.4V to 2.90V and -40°C<TA<85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications are valid only within the range: 25°C±20°C during the Flash Write operation. It is at the user’s own risk to operate out of this temperature range. If Flash writing is done out of this temperature range, the endurance and data retention reduces. Symbol VddIWRITE IDDP FlashENPB FlashDR Description Supply Voltage for Flash Write Operations[6] Supply Current for Flash Write Operations Flash Endurance Flash Data Retention Min 2.7 – 50,000 10 Typ – 5 – – Max – 25 – – Units V mA – Years Notes Erase/write cycles 11.4 CapSense Electrical Characteristics Max (V) Typ (V) Min (V) Conditions for Supply Voltage Result 3.6 3.3 3.1 <2.9 The device automatically reconfigures itself to work in 2.7V mode of operation. >2.9 or <3.10 2.90 5.25 2.7 5.0 2.45 4.75 This range is not recommended for CapSense usage. <2.45V The scanning for CapSense parameters shuts down until the voltage returns to over 2.45V. >3.10 The device automatically reconfigures itself to work in 3.3V mode of operation. <2.4V The device goes into reset. <4.73V The scanning for CapSense parameters shuts down until the voltage returns to over 4.73V. Note 7. Commands involving Flash Writes (0x01, 0x02, 0x03) must be executed only within the same VCC voltage range detected at POR (power on, or command 0x06) and above 2.7V. Document Number: 001-53516 Rev. ** Page 29 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 11.5 AC Electrical Specifications 11.5.1 5V and 3.3V AC General Purpose I/O Specifications Parameter Description Min Max Unit Notes TRise Rise time, strong mode, Cload = 50 pF 15 80 ns VDD = 3.10V to 3.6V and 4.75V to 5.25V, 10% - 90% TFall Fall time, strong mode, Cload = 50 pF 10 50 ns VDD = 3.10V to 3.6V and 4.75V to 5.25V, 10% - 90% Min Max Unit 11.5.2 2.7V AC General Purpose I/O Specifications Parameter Description Notes TRise Rise time, strong mode, Cload = 50 pF 15 100 ns VDD = 2.4V to 2.90V, 10% - 90% TFall Fall time, strong mode, Cload = 50 pF 10 70 ns VDD = 2.4V to 2.90V, 10% - 90% 11.5.3 AC I2C Specifications Parameter FSCLI2C Description SCL clock frequency THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated Standard Mode Fast Mode Min Max Min Max 0 100 0 400 kbps 4.0 – 0.6 – µs Units TLOWI2C LOW period of the SCL clock 4.7 – 1.3 – µs THIGHI2C HIGH period of the SCL clock 4.0 – 0.6 – µs TSUSTAI2C Setup time for a repeated START condition 4.7 – 0.6 – µs 2 0 – 0 – µs 2 TSUDATI C Data setup time 250 – 100 – ns TSUSTOI2C Setup time for STOP condition 4.0 – 0.6 – µs TBUFI2C BUS free time between a STOP and START condition 4.7 – 1.3 – µs TSPI2C Pulse width of spikes suppressed by the input filter – – 0 50 ns THDDATI C Data hold time Notes Fast mode not supported for VDD < 3.0V ~ ~ ~ ~ Figure 12. Definition of Timing for Fast/Standard Mode on the I2C Bus tf tLOWI2C tr tSUDATI2C ~ ~ tf ~ ~ SDA tHDSTAI2C tSPI2C tBUFI2C tr S tHDDATI2C Document Number: 001-53516 Rev. ** tHIGHI2C tSUSTAI2C ~ ~ tHDSTAI2C ~ ~ SCL Sr tSUSTOI2C P S Page 30 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 12. Examples of Frequently Used I2C Commands Sl. No. I2C Commands[7] Requirement Comment 1 Enter into setup mode W 00 A0 08 2 Enter into normal mode W 00 A0 07 3 Load factory defaults to RAM registers W 00 A0 02 4 Do a software reset W 00 A0 08 W 00 A0 06 5 Save current configuration to flash W 00 A0 01 6 Load factory defaults to RAM registers and save as user configuration W W W W 7 Disable combinational logic output to DIG0 W 00 1C 00 8 Disable combinational logic output to DIG1 W 00 21 00 9 Clearing (logic 0) the both DIG0 and DIG1 outputs W 00 04 00 10 Setting (logic 1) the DIG0 and clearing (Logic 0) the DIG1 outputs W 00 04 01 11 Clearing (logic 0) the DIG0 and Setting (Logic 1) the DIG1 outputs W 00 04 02 12 Setting (logic 1) the both DIG0 and DIG1 outputs W 00 04 03 13 Change CapSense clock to IMO/2 W 00 A0 08 W 00 51 20 W 00 A0 07 ; Enter into setup mode ; CapSense clock is set as IMO/2 ; Enter into normal mode 14 Change value of IDAC0 to ‘x’h W 00 70 x ‘x’ represents new value of IDAC register 15 Change value of IDAC1 to ‘y’h W 00 71 y ‘y’ represents new value of IDAC register 16 Change value of IDAC0 and IDAC1 to ‘x’h and ‘y’h W 00 70 x y ‘x’ and ‘y’ represents new value of IDAC register 17 Change the value FT0 to ‘x’h W 00 66 x ‘x’ represents new value of FT register 18 Change the value FT1 to ‘y’h W 00 67 y ‘y’ represents new value of FT register 19 Change the value FT0 and FT1 to ‘x’h and ‘y’h W 00 66 x y ‘x’ and ‘y’ represents new value of FT registers 20 Change noise threshold to ‘x’h W 00 4E x 21 Read CapSense button CS0 scan results W 00 81 81 W 00 82 R 00 RD RD RD RD RD RD ; Select CapSense button for reading scan result ; Set the read point to 82h ; Consecutive 6 reads gets baseline, difference count and raw count (all two byte each) 22 Read CapSense button status register W 00 88 R 00 RD ; Set the read pointer to 88 ; Reading a byte gets status CapSense inputs 00 A0 08 00 A0 02 00 A0 01 00 A0 06 ; Enter into setup mode ; Do software reset ; Enter into setup mode ; Load factory defaults to SRAM ; Save the configuration to Flash. Wait for time specified in Table 6. ; Do software reset Combinational logic output on DIG0 and DIG1 should be disabled before dong this operation (SL# 7 and 8) Note 8. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples. Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations. Document Number: 001-53516 Rev. ** Page 31 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 13. Ordering Information Ordering Code Package Diagram Package Type Operating Temperature CapSense Blocks CapSense Inputs Digital Outputs XRES Pin CY8C20111-SX1I 51-85066 8 SOIC Industrial Yes 1 1 No CY8C20111-SX1IT 51-85066 8 SOIC (Tape and Reel) Industrial Yes 1 1 No CY8C20121-SX1I 51-85066 8 SOIC Industrial Yes 2 2 No CY8C20121-SX1IT 51-85066 8 SOIC (Tape and Reel) Industrial Yes 2 2 No Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). 13.1 Ordering Code Information CY 8 C 201 xx - SX 1 I T Tape and Reel Thermal Rating : Industrial 8 pin pinout Package Type : SOIC Pb- Free Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress Semiconductors Company ID: CY = Cypress Document Number: 001-53516 Rev. ** Page 32 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 14. Package Diagram Figure 13. 8-Pin (150-Mil) SOIC (51-85066) 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document Number: 001-53516 Rev. ** Page 33 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 15. Document History Page Document Title: CY8C20111, CY8C20121 CapSense Express™ - One Button and Two Button Capacitive Controllers Document Number: 001-53516 Rev. ECN. Orig. of Change Submission Date ** 2709248 SLAN/PYRS See ECN Description of Change New data sheet 16. Sales, Solutions, and Legal Information 16.1 Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 16.2 Products PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53516 Rev. ** Revised May 20, 2009 Page 34 of 34 CapSense Express™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback