AS3412 Ultra Small ANC Speaker Driver General Description The AS3412 is a speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. They are intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. An internal OTP-ROM can be optionally used to store the microphones gain calibration settings. The AS3412 can be used in different configurations for best trade-off in terms of noise cancellation, required filtering functions and mechanical designs. The AS3412 targeting feed-forward topology is used to effectively reduce frequencies typically up to 2-3 kHz. The filter loop for the system is determined by measurements, for each specific headset individually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of this device are listed below: Figure 1: Added Value of Using AS3412 Benefits Features • Low noise floor • Low noise amplifiers • Integrated music bypass switch • Depletion mode transistors for passive music bypass • Smallest ANC form factor • WL-CSP package (2.2x2.2mm, 0.4mm pitch) Applications The devices are ideal for Ear Pieces, Headsets, Hands-Free Kits, Mobile Phones, and Voice Communicating Devices. ams Datasheet [v1-00] 2016-Apr-06 Page 1 Document Feedback AS3412 − General Description Block Diagram The functional blocks of the AS3412 are shown below: Figure 2: Functional Blocks of AS3412 CFL Y CVNEG CPP CPN GND VNEG VNEG QOP1L IOP1L MICACL CACL QMICL ANC Filter Left VBAT VMIC CMICL VBAT Charge Pump MICL CVBAT Music Bypass LINL MUTE TRSDA/BPL 3x PROM TRSCL/BPR AS3412 HPL ANC Processing AGND HPR LINR Music Bypass MICR I2C CMICR MIC Supply MUTE VMIC MICS VMIC CMICS ANC/CSDA QOP1R IOP1R ANC Filter Right MODE/CSCL CACR QMICR MICACR On/Off/Monitor/PBO AS3412 Block Diagram: This figure shows the functional blocks of the AS3412. Page 2 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Pin Assignment Pin Assignment Pin Diagram Figure 3: Pin Diagram of AS3412 A1 CPP A2 GND A3 VNEG A4 QOP1R A5 QMICR B1 VBAT B2 HPL B3 CPN B4 IOP1R B5 AGND C1 LINL C2 LINR C3 TRSDA/ BPL C4 MICR C5 ANC/ CSDA D1 HPR D2 QOP1L D3 IOP1L D4 MICL D5 MO DE/ CSCL E1 TRSCL/ BPR E2 QMICL E3 MICACL E4 MICS E5 MICACR Pin Description Figure 4: AS3412 Pin Assignment Pin Name Pin Number Pin Type Description AGND B5 ANA OUT Analog reference ground. Has to be connected to GND pin. For better noise performance a star shaped ground concept is the preferred option to connect these pins together. LINL C1 ANA IN Line input EQ left channel. ANA IN/OUT Data input for production trimming. Can be connected to LINL pin to enable production trimming via 3.5mm audio jack. Furthermore this pin features also music bypass function for the left audio channel in off mode operation in order to replace and external analog switch. TRSDA/ BPL ams Datasheet [v1-00] 2016-Apr-06 C3 Page 3 Document Feedback AS3412 − Pin Assignment Pin Name Pin Number Pin Type Description TRSCL/ BPR E1 ANA IN/OUT Clock input for production trimming. Can be connected to LINR pin to enable production trimming via 3.5mm audio jack. Furthermore this pin features also music bypass function for the right audio channel in off mode operation in order to replace an external analog switch. LINR C2 ANA IN Line input EQ right channel. ANC / CSDA C5 DIG IN Serial interface data for I²C interface and ANC control to enable/disable ANC. MODE / CSCL D5 DIG IN Serial Interface Clock for I²C interface and control pin for power up/down and Monitor mode. MICACL E3 ANA OUT Microphone preamplifier AC coupling ground terminal. This pin requires a 10μF capacitor connected to AGND pin. MICL D4 ANA IN ANC microphone input left channel. MICS E4 SUP OUT Microphone Supply output. This pin needs an output blocking capacitor with 10μF. MICR C4 ANA IN ANC microphone preamplifier input right channel. MICACR E5 ANA OUT Microphone preamplifier AC coupling ground terminal. This pin requires a 10μF capacitor connected to AGND pin. QMICR A5 ANA OUT ANC microphone preamplifier output right channel. IOP1R B4 ANA IN ANC filter OpAmp1 input right channel. QOP1R A4 ANA OUT ANC filter OpAmp1 output right channel. HPL B2 ANA OUT Headphone amplifier output left channel HPR D1 ANA OUT Headphone amplifier output right channel VBAT B1 SUP IN Positive supply terminal of IC. CPP A1 ANA OUT VNEG charge pump flying capacitor positive terminal. GND A2 GND VNEG charge pump ground terminal. Has to be connected to AGND pin. For better noise performance a star shaped ground concept is the preferred option to connect these pins together. CPN B3 ANA OUT VNEG charge pump flying capacitor negative terminal. VNEG A3 SUP OUT VNEG charge pump output. QOP1L D2 ANA IN Filter OpAmp1 output left channel. IOP1L D3 ANA OUT Filter OpAmp1 input left channel. QMICL E2 SUP IN ANC microphone preamplifier output left channel. Page 4 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings of AS3412 Symbol Parameter Min Max Units Comments Electrical Parameters VGND_MAX Ground Terminals -0.5 0.5 V Applicable for pin AGND and GND VSUP_MAX Supply Voltage to Ground -0.5 2.1 V Applicable for pin VBAT VNEG_MAX Negative Terminals -2.0 0.5 V Applicable for pin VNEG VCP_MAX Charge Pump Terminals VNEG-0.5 VNEG+0.5 V Applicable for pins CPN and CPP VHP_MAX Headphone Pins VNEG-0.5 VNEG+0.5 V Applicable for pins HPR and HPL VANA_MAX Analog Pins VNEG-0.5 VNEG+0.5 V Applicable for pins LINL, LINR, MICL/R, HPR, HPL, QMICL/R, IOP1x, QOP1x, CPP, CPN, TRSCL/BPR, TRSDA/BPL, MICACL and MICACR VCON_MAX Control Pins VNEG-0.5 5 V Applicable for pins ANC/CSDA and MODE/CSCL Other Pins VNEG-0.5 5 V Applicable for pins MICS VOTHER_MAX ISCR Input Current (latch-up immunity) (1) (2) ±100 mA JEDEC 17 Continuous Power Dissipation (TA = 70°C) PT Continuous power dissipation - tbd mW Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ± 2000 V JEDEC JESD22-A114C Temperature Ranges and Storage Conditions RTHJA Junction to Ambient Thermal Resistance ams Datasheet [v1-00] 2016-Apr-06 tbd tbd °C/W Page 5 Document Feedback AS3412 − Absolute Maximum Ratings Symbol TJ TSTRG Parameter Min Operating Junction Temperature Storage Temperature Range TBODY Package Body Temperature RHNC Relative Humidity (non-condensing) MSL Moisture Sensitivity Level -55 5 Max Units 85 °C 125 °C 260 °C 85 % 1 Comments IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.” Unlimited floor lifetime Note(s): 1. Latch-up test was performed with VBAT supplied and both AGND and GND grounded. 2. VNEG, CPP, CPN, MICACL and MICACR are not Latch-up stressed because these are passive pins. Page 6 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Electrical Characteristics Electrical Characteristics V BAT = 1.6V to 1.8V, TA = -20ºC to 85ºC. Typical values are at V BAT = 1.6V, TA = 25ºC, unless otherwise specified. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Electrical Characteristics of AS3412 Symbol TA Parameter Condition Ambient Temperature Range Min Max Unit -20 85 °C 0 0 V Supply Voltages GND Reference Ground VBAT Battery Supply Voltage 1.6 1.8 V VNEG Charge Pump Voltage -1.8 -1.45 V VDELTA Difference of Ground Supplies GND, AGND -0.1 0.1 V 0 3.7 V VNEG VBAT V 0 3.7 V VNEG VBAT V VNEG -0.3 or -1.8 VBAT +0.5 or 1.8 V VNEG VBAT V To achieve good performance, the negative supply terminals should be connected to a low impedance ground plane. Other Pins Microphone Supply Voltage MICS VANALOG Analog Pins MICACL, MICACR,LINR, LINL, HPR, HPL, QMICL, QMICR, IOP1x, and QOP1x VCONTROL Control Pins MODE/CSCL, ANC/CSDA Charge Pump pins CPN and CPP V TRIM Application Trim Pins TRSCL/BPR and TRSDA/BPL VMIC Microphone Inputs MICL and MICR VMICS VCP ams Datasheet [v1-00] 2016-Apr-06 Page 7 Document Feedback AS3412 − Electrical Characteristics Figure 7: Electrical Characteristics (continued) Symbol Parameter Condition Min Typ Max Unit Block Power Requirements IOFF Off mode current MODE/CSCL pin low, device switched off 0.4 1 10 μA ISYS Reference supply current VBAT = 1.8V; Bias generation, oscillator, POR; VNEG disabled 0.16 0.25 0.3 mA VBAT = 1.8V; no signal, stereo, normal mode 0.82 1.4 2 mA VBAT = 1.8V; no signal, stereo, ECO mode 0.58 1.1 1.4 mA VBAT = 1.8V; no signal, normal mode 1.5 2.4 3.1 mA VBAT = 1.8V; no signal, ECO mode 1.18 2.0 2.9 mA VBAT = 1.8V; no load 0.36 0.5 0.9 mA VBAT = 1.6V; no load 0.36 0.4 0.85 mA VBAT = 1.8V; OP1L and OP1R enabled, normal mode 0.85 1.25 1.75 mA VBAT = 1.8V; OP1L and OP1R enabled, ECO mode 0.65 0.9 1.37 mA VBAT = 1.6V; OP1L and OP1R enabled, normal mode 0.8 1.2 1.68 mA VBAT = 1.6V; OP1L and OP1R enabled, ECO mode 0.6 0.85 1.32 mA IMIC IHP IMICS IOP1 Mic gain stage current Headphone stage current MICS charge pump current OP1 supply current Typical System Power Consumption PFF PFF_ECO Typical power consumption feed forward application OP1L, OP1R enabled, Microphone supply enabled, no load, VBAT=1.6V 10 mW Typical power consumption feed forward application in ECO mode All blocks in ECO mode OP1L, OP1R enabled Microphone supply enabled, no load, VBAT=1.6V 8 mW Electrical Characteristics: Shows the electrical characteristics like typical supply voltages as well as system current consumption. Page 8 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Detailed Description This section provides a detailed description of the device related components. Audio Line Input The chip features one stereo line input for music playback. In monitor mode the line inputs can also be muted in order to stop music playback and increase speech intelligibility. Figure 8: Stereo Line Input MUTE to left headphone amplifier MUTE to right headphone amplifier LINL Music Left RLI N CLI N LINR Music Right CLI N RLI N Stereo Line Input: This diagram shows the internal structure of the line input. If there is a high pass function desired in an application, to block very low frequencies that could harm the speaker, or eliminate little offset voltages a simple capacitor C LIN could do this function. The implementation is shown in Figure 8. The correct capacitor value for the desired cut-off frequency can be calculated with the following formula: (EQ1) 1 C LIN = ---------------------------------------------------2 ⋅ π ⋅ R LIN ⋅ f cut – off A typical cut-off frequency in an audio application is 20Hz. With an input impedance R LIN of typ. 2k and a desired cut off frequency of 20Hz the input capacitor should be bigger than 4μF. Therefore a typical value of 4.7μF is recommended. ams Datasheet [v1-00] 2016-Apr-06 Page 9 Document Feedback AS3412 − Detailed Description Parameter V BAT=1.65V, TA= 25ºC unless otherwise specified Figure 9: Line Input Parameter Symbol Parameter Condition Min Typ Max Unit VLIN Input Signal Level 0.9*VBAT VPEAK RLIN Input Impedance 2 kΩ Line Input Parameter: This table shows the detailed electrical characteristics of the line input. Microphone Inputs The AS3412 offers two low noise microphone inputs with full digital control and a dedicated DC offset cancellation pin for each microphone input. In total each gain stage offers up to 63 gain steps of 0.5dB resulting in a gain range from 0dB to +31dB. The microphone gain is stored digitally during production on an OTP memory. Besides the standard microphone gain register for left and right channel, the chip features also two additional microphone gain registers for monitor mode. Thus, in monitor mode, a completely different gain setting for left and right microphone can be selected to implement voice filter functions in order to amplify the speech band for better speech intelligibility. Figure 10: Stereo Microphone Input MICL MUTE_MIC_LEFT MUTE AGC QMICL MUTE AGC QMICR MICACL MICACR MICR MUTE_MIC_RIGHT Stereo Microphone Input: This diagram shows the internal structure of the stereo microphone preamplifier including the mute switch as well as the automatic gain control (AGC). Page 10 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description To avoid unwanted start-up pop noise, a soft-start function is implemented for an automatic gain ramping of the device. In case of an overload condition on the microphone input (e.g. high sound pressure level), an internal state machine reduces the microphone gain automatically. For some designs it might be useful to switch off this feature. Especially in feed-back systems very often infrasound can cause an overload condition of the microphone preamplifier which results in low frequency noise. This behavior can be avoided by disabling the AGC function. Input Capacitor Selection The microphone preamplifier needs one bias resistor (R Bias) per channel as well as DC blocking capacitors (C MIC ). The capacitors C AC are DC blocking capacitors to avoid DC amplification of the non-inverting microphone preamplifier. This capacitor has an influence on the frequency response because the internal feedback resistors create a high pass filter together with the capacitor C AC. The typical application circuit is shown in Figure 11 with all necessary components. Figure 11: Microphone Capacitor Selection Circuit MICS RBIAS CMIC MICL MUTE_MIC_LEFT MUTE AGC QMICL AGC QMICR RMICIN ANC Microphone CAC MICACL MICACR CAC RMICIN ANC Microphone CMIC MICR MUTE MUTE_MIC_RIGHT MICS RBIAS Microphone Capacitor Selection Circuit: This diagram shows a typical microphone application circuit with all necessary components to operate the amplifier. ams Datasheet [v1-00] 2016-Apr-06 Page 11 Document Feedback AS3412 − Detailed Description The corner frequency of this high pass filter is defined with the capacitor C AC and the gain of the headphone amplifier. Figure 12 shows an overview of typical cut-off frequencies with different microphone gain settings. Figure 12: Microphone Cut-Off Frequency Overview Microphone Gain R1 R2 Fcut-off 0dB 22.2kΩ 0Ω 1.7Hz 3dB 15716Ω 6484Ω 1.9Hz 6dB 11126Ω 11074Ω 2.2Hz 9dB 7877Ω 14323Ω 2.7Hz 12dB 5576Ω 16623Ω 3.5Hz 15dB 3948Ω 18252Ω 4.5Hz 18dB 2795Ω 19405Ω 6.1Hz 21dB 1979Ω 20221Ω 8.4Hz 24dB 1400Ω 20800Ω 11.5Hz 27dB 992Ω 21208Ω 16.3Hz 30dB 702Ω 21498Ω 22.7Hz Microphone Cut-Off Frequency Overview: This table shows an overview of the different cut-off frequencies with CAC=10μF, CMIC= 2.2μF and RMICIN=22kΩ of the microphone preamplifier. Filter Simulations: It is important when doing the ANC filter simulations to include all microphone filter components to incorporate the gain and phase influence of these components. In the cut-off frequency overview, capacitor C AC was defined as 10μF which results in a rather low cut-off frequency for best ANC filter design. If a different capacitor value is desired in the application, the following formula defines the transfer function of the high pass circuit of the microphone preamplifier: 2 (EQ2) 2 2 2 4 ⋅ C AC ⋅ f ⋅ ( R 1 + R 2 ) ⋅ π + 1 A = ----------------------------------------------------------------------------------2 2 2 2 4 ⋅ C AC ⋅ f ⋅ R 1 ⋅ π + 1 The simplified transfer function does not include the high pass filter defined by C MIC and RMICIN. With the recommended values of 2.2μF for C MIC and 22kΩ for RMICIN this filter can be neglected because of the very low cut-off frequency of 1.5Hz. Page 12 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description The cut-off frequency for this filter can be calculated with the following formula: (EQ3) 1 f cut – off = ----------------------------------------------------2 ⋅ π ⋅ R MICIN ⋅ C MIC The simulated frequency response for the microphone preamplifier with the recommended component values is shown in Figure 13. Figure 13: Simulated Microphone Frequency Response 35 Frequency Response [dB] Microphone Frequency Response: This graph shows the frequency response of the microphone preamplifier with different gain settings with CAC=10μF, CMIC=2.2μF and RMICIN=22kΩ. 30 30dB 25 24dB 20 18dB 15 12dB 10 6dB 5 0dB 0 -5 10 100 1k 10k f [Hz] In application with PCB space limitations it is also possible to remove the capacitors C AC and connect MICACL and MICACR pins directly to AGND. In this configuration AC coupling of the QMICR and QMICL signals is recommended. ams Datasheet [v1-00] 2016-Apr-06 Page 13 Document Feedback AS3412 − Detailed Description Parameter V BAT=1.8V, TA= 25ºC, C AC=10μF, CMIC=4.7μF and RMICIN=2.2kΩ unless otherwise specified. Figure 14: Microphone Parameter Symbol Parameter VMICIN0 VMICIN1 Input Signal Level VMICIN2 SNR VNOISE-A IMIC Signal to Noise Ratio A-Weighted Output Noise Floor Block Current Consumption Page 14 Document Feedback Condition Min Typ Max Unit AMIC = 10dB 80 mVRMS AMIC = 20dB 40 mVRMS AMIC = 30dB 10 mVRMS 0dB gain, High quality mode, AGC off 118.5 dB 10dB gain, High quality mode, AGC off 109 dB 20dB gain, High quality mode, AGC off 99.5 dB 0dB gain, ECO mode, AGC off 117 dB 10dB gain, ECO mode, AGC off 107 dB 20dB gain, ECO mode, AGC off 98 dB 0dB gain, 20Hz – 20kHz bandwidth, high quality 1.2 μV 10dB gain, 20Hz – 20kHz bandwidth, High quality 4.2 μV 20dB gain, 20Hz – 20kHz bandwidth, High quality 13.5 μV 0dB gain, 20Hz – 20kHz bandwidth, ECO mode 1.4 μV 10dB gain, 20Hz – 20kHz bandwidth, ECO mode 4.6 μV 20dB gain, 20Hz – 20kHz bandwidth, ECO mode 14.8 μV VBAT = 1.8V; no signal, stereo, normal mode 0.82 1.4 2 mA VBAT = 1.8V; no signal, stereo, ECO mode 0.58 1.2 1.4 mA ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Symbol Parameter Programmable Gain AMIC Condition Min Discrete logarithmic gain steps Typ 0 Gain Steps Size Max Unit +31 dB 0.5 Gain Step Precision dB 0.2 ΔAMIC Gain Ramp Rate VPEAK related to VBAT or VNEG VATTACK Limiter Activation Level VDECAY VPEAK related to VBAT or VNEG 64 @ 0.5dB Limiter Release Level AMICLIMIT dB 1 ms/step 0.40 1 0.31 1 Limiter Minimum Gain 0 dB tATTACK Limiter Attack Time 5 μs/step tDECAY Limiter Decay Time 1 ms/step Microphone Parameter: This table shows the detailed electrical characteristics of the microphone preamplifier gain stage. Figure 15: Microphone Frequency Response 35 Frequency Response [dB] Microphone Frequency Response: This graph shows the frequency response of the microphone preamplifier with different gain settings without RMICIN resistor, CAC capacitor (MICACx pin connected to AGND) and CMIC=10uF. 30dB 30 25 20dB 20 15 10dB 10 5 0dB 0 -5 10 100 1k 10k f [Hz] ams Datasheet [v1-00] 2016-Apr-06 Page 15 Document Feedback AS3412 − Detailed Description Figure 16: Microphone THD+N vs. Vinput Microphone THD+N vs. Vinput: This graph shows the A-weighted THD+N versus input voltage of the microphone preamplifier with 0dB gain and VBAT=1.8V. 1 THD+N [%] 0,1 0,01 0,001 0,0001 10 100 Vinput [mV] Figure 17: Microphone THD+N vs. Vinput ECO Mode Microphone THD+N vs. Vinput: This graph shows the A-weighted THD+N versus input voltage of the microphone preamplifier with 0dB gain and VBAT=1.8V. The amplifier runs in ECO mode. 1 THD+N [%] 0,1 0,01 0,001 0,0001 10 100 Vinput [mV] Page 16 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Microphone Supply The AS3412 features an integrated microphone supply charge pump. This charge pump provides the proper microphone supply voltage even with a 1.8V chip supply voltage in order to increase the sensitivity of the microphone. Figure 18: Microphone Supply CP Bypass Microphone BIAS resis tors RMICSF CMICSF MICS CMICS MIC Charge Pump VBAT MICS_ON Therefore the integrated charge pump generates a microphone supply voltage which is typically 2.7V. The microphone supply voltage is also used to switch off the integrated music bypass switch of the AS3412 is in active mode. Therefore, during normal operation the microphone supply must not be switched off if the TRSDA/BPL and TRSCL/BPR pins are in use. ams Datasheet [v1-00] 2016-Apr-06 Page 17 Document Feedback AS3412 − Detailed Description Bypass Switch Operation: When using the TRSDA/BPL and TRSCL/BPR pins you must not switch off the microphone supply! Parameter V BAT=1.8V, TA= 25ºC, CMICS = 22μF, C MICSF = 47μF and R MICSF = 220Ω unless otherwise specified. Figure 19: Microphone Supply Parameter Symbol VMICS IMICS VNoise-A Parameter Microphone Supply Voltage Block Current Consumption Microphone Supply Noise Condition Min Typ Max Unit VBAT = 1.8V, no load 3.4 V VBAT = 1.65V, no load 3.2 V VBAT = 1.8V; no load 0.36 0.5 0.9 mA VBAT = 1.65V; no load 0.36 0.4 0.85 mA A-Weighted, 500μA load 1.4 μV A-Weighted, 550μA load, only CMICS = 22uF assembled 11 μV A-Weighted, 500μA load, only CMICS = 10uF assembled 15 μV Microphone Supply Parameter: This table shows the detailed electrical characteristics of the microphone supply. Figure 20: Microphone Supply Load Characteristic Microphone Supply Load Characteristic: This diagram shows output voltage of the microphone supply vs. output load on the microphone supply. VMICS [V] 3 2 1 VBAT=1.65 VBAT=1.8V 0 1 2 3 4 Iload [mA] Page 18 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Headphone Amplifier The headphone amplifier is a true ground output using V NEG as negative supply. It is designed to feature an output power of 2x34mW @ 32Ω load. For higher output requirements, the headphone amplifier is also capable of operating in bridged mode. In this mode the left output is carrying the inverted signal of the right output shown in Figure 22. With a V BAT voltage of 1.8V, a maximum output power of 90mW can be achieved. This is required for over- and on ear headsets with higher output power requirements. The amplifier itself features various input sources. The line input signal is directly connected to the headphone amplifier. The input multiplexer supports three different input signals which can be configured according to the HPH_MUX register. The “Open” setting is being used to disable the active noise cancelling function. Figure 21: Headphone Amplifier Single Ended HPH_MUX 2kΩ MUX QMICR QOP1R 2kΩ open LINE_MUTE 2kΩ LINR HPR RLI N AGND RLI N HPL LINE_MUTE LINL QMICL QOP1L MUX 2kΩ open 2kΩ 2kΩ HPH_MUX Headphone Amplifier Single Ended: This figure shows the block diagram of the headphone amplifier including the integrated music bypass switches as well as the summation input of the amplifier in single ended configuration. ams Datasheet [v1-00] 2016-Apr-06 Page 19 Document Feedback AS3412 − Detailed Description Figure 22: Headphone Amplifier Differential HPH_MUX MUX QMICL QOP1L 2kΩ 2kΩ open LINL 2kΩ LINE_MUTE HPL RLI N AGND HPR 2kΩ 2kΩ Headphone Amplifier Differential: This figure shows the block diagram of the headphone amplifier including the integrated music bypass switches as well as the summation input of the amplifier in differential output mode. Page 20 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Parameter V BAT =1.8V, TA= 25ºC, unless otherwise specified. Figure 23: Headphone Amplifier Parameter Symbol RL_HP CL_HP PHP PHP_BRIDGE IHPH PSRRHP SNR Parameter Condition Min Typ Stereo mode 16 32 Mono 32 Max Unit Ω Load Impedance Load Capacitance Nominal Output Power Stereo Mode Nominal Output Power Differential Mode Ω Stereo mode 100 pF Vbat = 1.8V; 32Ω load; THD<0.1% 34 mW Vbat = 1.65V; 32Ω load; THD<0.1% 29 mW Vbat = 1.8V; 16Ω load; THD<0.1% 50 mW Vbat = 1.65V; 16Ω load; THD<0.1% 41 mW Vbat = 1.8V; 32Ω load 90 mW Vbat = 1.65V; 32Ω load 75 mW VBAT = 1.8V; no signal, normal mode 1.5 2.4 3.1 mA VBAT = 1.8V; no signal, ECO mode 1.18 2 2.9 mA Supply current Power Supply Rejection Ratio 1kHz 100 dB High Quality Mode, Line Input -> HPH stereo in phase test signal; 32Ω load; VBAT = 1.8V; 111.5 dB High Quality Mode, Line Input -> HPH stereo out of phase test signal; 32Ω load; VBAT = 1.8V; 112.5 dB ECO Mode, Line Input -> HPH stereo in phase test signal; 32Ω load; VBAT = 1.8V; 109.5 dB ECO Mode, Line Input -> HPH stereo out of phase test signal; 32Ω load; VBAT = 1.8V; 110.5 dB 93 dB Signal to Noise Ration Channel Separation ams Datasheet [v1-00] 2016-Apr-06 32Ω load Page 21 Document Feedback AS3412 − Detailed Description Symbol VNoise-A Parameter Condition Output Noise Floor A-Weighted Min Typ Max Unit High Quality Mode; 32Ω load; HP_MUX = nc; LINx connected to ground 2.5 μV ECO Mode; 32Ω load; HP_MUX = nc; LINx connected to ground 3.1 μV Headphone Amplifier Parameter: This table shows the detailed electrical characteristics of the headphone amplifier like output power, SNR and channel separation. Figure 24: Headphone THD+N vs. Output Power 32Ω Stereo 1 1 Vbat = 1.8V Vbat = 1.8 ECO Vbat = 1.65V Vbat = 1.65V ECO 0,1 THD+N [%] THD+N [%] 0,1 0,01 0,01 0,001 0,001 1 10 100 1 Pout [mW] 10 100 Pout [mW] Headphone THD+N vs. Output Power: These figures shows the THD+N measurements of the headphone amplifier with different supply voltages in normal mode and ECO mode. The amplifier gain is 0dB with 32Ω load. Figure 25: Headphone THD+N vs. Output Power 16Ω Stereo 1 1 Vbat = 1.8V Vbat = 1.8 ECO Vbat = 1.65V Vbat = 1.65V ECO 0,1 THD+N [%] THD+N [%] 0,1 0,01 0,01 0,001 0,001 1 Pout [mW] 10 100 1 10 100 Pout [mW] Headphone THD+N vs. Output Power: These figures shows the THD+N measurements of the headphone amplifier with different supply voltages in normal mode and ECO mode. The amplifier gain is 0dB with 16Ω load. Page 22 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 26: Headphone THD+N vs. Output Power 32Ω Mono 1 1 Vbat = 1.8 ECO Vbat = 1.8V Vbat = 1.65V Vbat = 1.65V ECO 0,1 THD+N [%] THD+N [%] 0,1 0,01 0,01 0,001 0,001 1 10 100 1 1k 10 100 1k Pout [mW] Pout [mW] Headphone THD+N vs. Output Power: These figures shows the A-weighted THD+N measurements of the headphone amplifier with different supply voltages in normal mode and ECO mode. The amplifier gain is 6dB with 32Ω load in mono configuration. Figure 27: Headphone THD+N vs. Frequency 32Ω Stereo/Mono 100 30 THD+N THD+N ECO Pout 10 25 10 20 1 80 THD+N Mono THD+N Mono ECO Pout Mono 0,01 10 THD+N [%] 15 Pout [mW] THD+N [%] 0,1 0,1 40 Pout [mW] 60 1 0,01 20 0,001 0,0001 10 100 1k f [Hz] 10k 5 0,001 0 0,0001 0 10 100 1k 10k f [Hz] Headphone THD+N vs. Frequency: These figures shows the A-weighted THD+N measurements over frequency in stereo and mono differential mode with VBAT=1.8V. The amplifier gain is 0dB and the load in both modes is 32Ω with 1mW and 5mW output power. ams Datasheet [v1-00] 2016-Apr-06 Page 23 Document Feedback AS3412 − Detailed Description Figure 28: Headphone THD+N vs. Frequency 16Ω Stereo Headphone THD+N vs. Frequency: These figures shows the A-weighted THD+N measurements over frequency in stereo mode with VBAT=1.8V. The amplifier gain is 0dB and the load is 16Ω. 40 THD+N THD+N ECO Pout 10 THD+N [%] 0,1 20 0,01 Pout [mW] 30 1 10 0,001 0,0001 0 10 100 1k 10k f [Hz] Page 24 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Integrated Music Bypass Switch If the AS3412 is switched off, the device features a unique integrated music bypass function. The bypass switches can be used to replace a mechanical switch to bypass the music signal in off mode or if the headset runs out of battery. Figure 29 shows the basic music playback path of the AS3412 with a full battery. In this mode the line input signal is feed to the headphone amplifier. The integrated bypass switches are automatically disabled in this operation mode. VBAT Figure 29: Bypass Mode Inactive 100% TRSDA/BYPL Music Bypass HPL LINL AGND 3.5mm audio jack HPR LINR TRSCL/BYPR Music Bypass Bypass Mode Active: This block diagram shows the general music playback path of AS3412 with the integrated music bypass switches disabled. Figure 30 shows the AS3412 in off mode with an empty battery. This is basically the same use case as no battery at all. In this mode the internal bypass switch becomes active. The headphone amplifier is not powered because the headset has run out of battery and the bypass switch becomes active. Thus the music signal coming from the 3.5mm audio jack is routed through the ANC chip, without any power source connected to the device, to the speakers. ams Datasheet [v1-00] 2016-Apr-06 Page 25 Document Feedback AS3412 − Detailed Description Integrated Bypass Switch: The integrated bypass switch works even without any battery connected to the device. It helps to reduce BOM costs and PCB area. Furthermore it facilitates new industrial designs to ANC solutions. VBAT Figure 30: Bypass Mode Active TRSDA/BYPL Music Bypass 0% HPL LINL AGND 3.5mm audio jack HPR LINR TRSCL/BYPR Music Bypass Bypass Mode Inactive: This block diagram shows the general music playback path of AS3412 with the integrated music bypass switches enabled. The device has no supply any more but music playback is still possible via the internal bypass switches. Parameter V BAT =0V, TA= 25ºC, unless otherwise specified. Figure 31: Bypass Switch Parameter Symbol RSwitch THD Parameter Impedance Condition Min Typ Max Unit Power down 1.5 Ω 0dBV input signal, 32Ω load -90 dB 0dBV input signal, 16Ω load -80 dB Total Harmonic Distortion Bypass Switch Parameter: This table shows the detailed electrical characteristics of the integrated bypass switch. Page 26 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 32: Bypass THD+N vs. Output Power 16Ω Load Bypass THD+N vs. Output Power: This graph shows A-weighted THD+N characteristics of the integrated bypass switch for 16Ω load. 1 16 Ohm THD+N [%] 0,1 0,01 0,001 1 10 100 Pout [mW] Figure 33: Bypass THD+N vs. Output Power 32Ω Load Bypass THD+N vs. Output Power: This graph shows A-weighted THD+N characteristics of the integrated bypass switch for 32Ω load. 1 32 Ohm THD+N [%] 0,1 0,01 0,001 1 10 100 Pout [mW] ams Datasheet [v1-00] 2016-Apr-06 Page 27 Document Feedback AS3412 − Detailed Description Operational Amplifier The AS3412 offers one general purpose operational amplifier for feed-forward ANC applications. The amplifier is used to develop the gain- and phase compensation filter for the ANC signal path. Figure 34: Operational Amplifiers Operational Amplifier: This figure shows the block diagram of the operational amplifiers to be used for ANC filter design. OP1L QOP1L AGND OP1R Page 28 Document Feedback QOP1R ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Parameter V BAT =1.8V, TA= 25ºC, R input = RFB = 1kΩ unless otherwise specified. Figure 35: Operational Amplifier Parameter Symbol VLIN SNR IOP1 VNOISE-A Parameter Input Signal Level Signal to Noise Ratio Block Current Consumption Input Referred Noise Floor A-Weighted Voffset DC offset voltage CL Load Capacitance ALoop Open Loop Gain RL Load Impedance Condition Min Gain=0dB Typ Max Unit 0.9*VBAT VBAT VPEAK 10kΩ load, Gain = 0dB(1), VBAT=1.8V, High Quality Mode 122.5 dB 10kΩ load, Gain = 0dB, VBAT=1.65V High Quality Mode 121.5 dB 10kΩ load, Gain = 0dB, VBAT=1.8V, ECO Mode 121 dB 10kΩ load, Gain = 0dB, VBAT=1.65V, ECO Mode 119.5 dB VBAT = 1.8V; OP1L and OP1R enabled, normal mode 0.85 1.25 1.75 mA VBAT = 1.8V; OP1L and OP1R enabled, ECO mode 0.65 0.9 1.37 mA VBAT = 1.65V; OP1L and OP1R enabled, normal mode 0.8 1.2 1.68 mA VBAT = 1.65V; OP1L and OP1R enabled, ECO mode 0.6 0.85 1.32 mA High Quality Mode 900 nV ECO Mode 1.1 μV Gain = 0dB 100Hz 120 1 2 mV 100 pF dB kΩ Operational Amplifier: This table shows the detailed electrical characteristics of the operational amplifiers to be used for ANC signal processing. Note(s): 1. SNR figure measured with 20dB gain to minimize audio analyzer noise floor ams Datasheet [v1-00] 2016-Apr-06 Page 29 Document Feedback AS3412 − Detailed Description Figure 36: Operational Amplifier Frequency Response 1 Frequency Response [dB] Operational Amplifier Frequency Response: This graph shows the frequency response of the operational amplifiers with 0dB gain in normal and ECO mode. ECO Mode 0,8 HighQ Mode 0,6 0,4 0,2 0 -0,2 -0,4 -0,6 -0,8 -1 10 100 1k 10k f [Hz] Figure 37: Operation Amplifier THD+N vs. Frequency V BAT = 1.8V Operation Amplifier THD+N vs. Frequency: The diagram shows the A-weighted THD+N measurement of the line input amplifier with 0dB gain and VBAT=1.8V. 1 HighQ Mode ECO Mode THD+N [%] 0,1 0,01 0,001 0,0001 10 100 1k 10k f [Hz] Page 30 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description System The system block handles the power up and power down sequencing as well as the mode switching. Power Up/Down Conditions The chip powers up when one of the following conditions is true: Figure 38: Power Up Conditions # Source 1 MODE pin 2 I²C start Description In stand-alone mode, MODE pin has to be driven high for >2ms to turn on the device In I²C mode, an I²C start condition turns on the device Power Up Conditions: This table shows the available power up conditions of the AS3412. The chip automatically shuts off if one of the following conditions arises: Figure 39: Power Down Conditions # Source 1 MODE pin 2 Serial Interface 3 VNEG CP OVC Description Slider Mode: Mode pin has to be driven low for 10ms to turn off Push Button Mode: Mode pin has to be driven high for >2.4sec to turn off Power down by serial interface by clearing the PWR_HOLD bit. (Please mind that the I²C_MODE bit has to be set before clearing the PWR_HOLD bit for security reasons) Power down if VNEG is higher than the VNEG off-threshold Power Down Conditions: This table shows the available power down conditions of the AS3412. ams Datasheet [v1-00] 2016-Apr-06 Page 31 Document Feedback AS3412 − Detailed Description Start-Up Sequence The AS3412 has a defined startup sequence. Once the AS3412 MODE pin is pulled high, the device initiates the automatic startup sequence shown in Figure 40. Figure 40: Start-Up Sequence VBAT min. 1.65V MODE/CSCL min. 70% VBAT VOL/CSDA don‘t care BIAS & OSC ON VNEG ON VNEG OK OTP READ PWR_HOLD MICS & OP1 ON MIC STAGE ON HPH & LINE ON PWRUP COMPLETE FADE IN MIC GAIN 1 2 3 4 203 ~ 0 ~ ~ Time Axis 405 981 t [ms] Start-Up Sequence: This timing diagram shows the startup sequence of the AS3412 in detail. Page 32 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Operation Modes If the AS3412 is in stand-alone mode (no I²C control), the device can work in different operation modes. An overview of the different operation modes is shown in Figure 41. Figure 41: Operation Modes MODE Description OFF Chip is turned off. ANC Chip is turned on and active noise cancellation is active MONITOR PBO In monitor mode, a different (normally higher) microphone preamplifier gain can be configured to get an amplification of the ambient noise. To get rid of the low pass filtering needed for the noise cancellation, the headphone input multiplexer can be set to a different (typically MIC) source to increase speech intelligibility. In addition, the Line Input can be muted to further enhance speech intelligibility. If the device is operated in I²C mode, it is also possible to enter the monitor mode by setting the MON_MODE bit in register 0x3D. The Playback Only Mode is a special mode that disables the noise cancelling function and just keeps the line input amplifier as well as the headphone amplifier active. Operation Modes: This table gives an overview of the different operation modes of the AS3412. With the AS3412 the design engineer has different options to enter the described operation modes shown in Figure 41. In addition to the different switch and push button connections described in the following three chapters, it is also important to configure the chipset accordingly. Figure 42 shows the required register configuration settings to enable the different AS3412 control modes. Figure 42: User Interface Control Modes Register Name MODE SLIDE_PWR_UP SLIDER_MON Button Mode 0 0 Do not use 0 1 Slider Mode 1 0 Full Slider Mode 1 1 Stand Alone Operation Mode: Shows the different operation modes that can be selected with push button control or slide switch control. ams Datasheet [v1-00] 2016-Apr-06 Page 33 Document Feedback AS3412 − Detailed Description Full Slider Mode Full Slider Mode enables the AS3412 to be connected to two slide switches for Power, ANC and Monitor Mode control. To enable this operation mode both bits, SLIDE_PWR_UP and SLIDER_MON, have to be set to ‘1’. The typical connection of the slide switches is shown in Figure 43. Figure 43: Full Slider Mode VBAT MODE/CSCL 22kΩ Control Logic ANC/CSDA S1 22kΩ OFF ON 1MΩ MON S2 ANC PBO Full Slider Mode: The diagram shows the external connection of the switches in full slider mode. In Full Slider Mode the MODE/CSCL pin can detect three different input levels to distinguish between different operating modes: On, Off and Monitor mode. The timing diagram with all relevant information is shown in Figure 44. Figure 44: Full Slider Mode Timing Diagram Operation Mode OFF ON MONITOR OFF VBAT >=1.65V MODE/CSCL Pin ON 45% - 55% VBAT >2ms 200-400ms 200-400ms >10ms Full Slider Mode Timing Diagram: The diagram shows the necessary pin voltages and timings for different operation modes in Full Slider Mode configuration. Page 34 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Slider Mode Slider Mode is similar to Full Slider Mode with the only difference that it is possible to use a push button (S3) to enable and disable the Monitor Mode. Be aware that for Slider Mode operation bit SLIDE_PWR_UP has to be set to ‘1’ and the SLIDER_ MON bit has to be set to ‘0’. Figure 45: Slider Mode VBAT MODE/CSCL S1 S2 S3 ON Control Logic ANC/CSDA 22kΩ OFF 22kΩ MONITOR ANC PBO Slider Mode: The diagram shows the external connection of the switches and push button in slider mode. The advantage of this mode compared to Full Slider Mode is the automatic hold function of the Monitor Mode. Once the push button S3 is pressed the device enters monitor mode. This mode stays active until the user pushes the button again. Figure 46: Slider Mode Timing Diagram Operation Mode OFF ON MONITOR ON VBAT >=1.65V MODE/CSCL Pin OFF 45% - 55% VBAT <0.3V >2ms >24ms >24ms >10ms Slider Mode Timing Diagram: The diagram shows the necessary voltages and timings for different operation modes in Slider Mode configuration. ams Datasheet [v1-00] 2016-Apr-06 Page 35 Document Feedback AS3412 − Detailed Description Push Button Mode Push Button mode allows the user to control the device with a single normally open (NO) push button. A simple key press powers up the AS3512. Once the device is running, a long key press (~2.4 seconds) shuts the device down. As long as the device is active a short key press enters monitor mode. The monitor mode can be deactivated with a second, short key press. A timing diagram of this function is shown in Figure 48. If the monitor mode function is not desired, it is possible to deactivate the monitor mode by setting the bit DISABLE_ MONITOR in register 0x15. The typical connection of the push button to the AS3412 is shown in Figure 47. Figure 47: Push Button Mode VBAT MODE/CSCL ANC/CSDA Control Logic S2 S4 22kΩ ANC ON/OFF/MONITOR PBO Push Button Mode: The diagram shows the external connection of the switches and push button in slider mode. Figure 48: Push Button Timing Diagram Operation Mode OFF ON MONITOR ON OFF >65% VBAT MODE/CSCL Pin <35% VBAT >2ms >24ms >24ms >2.4s Push Button Mode Timing Diagram: The diagram shows the necessary voltages and timings for different operation modes in Push Button configuration. Page 36 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Playback Only Mode The active noise cancelling feature of the AS3412 can also be disabled with the ANC/CSDA pin. The ANC/CSDA pin has to be pulled high to enable the ANC function during startup (ANC MODE). If the pin is connected to ground, the chip enters playback only mode (PBO MODE) in which the ANC function is disabled. The operating mode of the line input mute switch, as well as the mixer input, can be defined in register PBO_MODE. The microphone amplifier shuts down automatically, but it is possible to control the operational amplifiers in this mode separately. Typically only the line input amplifiers and the headphone amplifier are enabled in the playback only mode. If this function is not desired you just need to pull the pin high through a 22kΩ resistor. Figure 49: Playback Only Mode Timing Diagram Operation Mode ANC ON Playback Only Mode ANC ON >65% VBAT ANC/CSDA Pin <35% VBAT 200-400ms 200-400ms Playback Only Mode Timing Diagram: The diagram shows the necessary voltages and timings for different operation modes in Playback Only Mode. ams Datasheet [v1-00] 2016-Apr-06 Page 37 Document Feedback AS3412 − Detailed Description V NEG Charge Pump The V NEG charge pump uses one external 1μF ceramic capacitor (C FLY ) to generate a negative supply voltage out of the input voltage to supply all audio related blocks. This allows a true-ground headphone output with no need of external DC-decoupling capacitors. Figure 50: VNEG Charge Pump 1µF CPP CPN CFL Y VBAT VBAT Charge Pump Connection to audio blocks VNEG 10µF GND 10µF VNEG CVNEG CVBAT VNEG Charge Pump: This figure shows the block diagram of the VNEG charge pump that supplies all audio blocks of the AS3412. The charge pump typically requires an additional input capacitor, C VBAT of 10μF and output capacitor, C VNEG, with the same size as the input capacitor. The flying capacitor, C FLY, should be 1μF. Parameter V BAT =1.8V, TA= 25ºC, unless otherwise specified. Figure 51: VNEG Charge Pump Parameter Symbol VIN Parameter Condition Min Typ Max Unit Input voltage VBAT 1.65 1.8 V VOUT Output voltage VNEG -1.45 -1.8 V CFLY External flying capacitor 1 μF CVBAT VBAT input capacitor 10 μF CVNEG VNEG output capacitor 10 μF VNEG Charge Pump Parameter: This table describes the electrical characteristics of the VNEG charge pump. Page 38 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description OTP Memory and Internal Registers The OTP (one-time programmable) memory consists of OTP registers (0x10 - 0x17 and 0x30 - 0x35) and OTP fuses. The OTP registers can be written as often as wanted but they are volatile memory cells. It is possible to access the OTP registers using the I²C interface for “soft programming” the part or via the production programming interface pins (TRSDA and TRSCL). In order to store chip configuration data to the ANC chip, the OTP registers are linked together with the OTP fuses shown in Figure 52. The OTP fuse block is a shadow register of the OTP registers that are nonvolatile memory cells. These registers store chip parameters during power-down. Programming the fuses can be done three times and is a permanent change. In order to configure the ANC chip during startup the OTP fuse content is loaded to the OTP registers. The AS3412 offers 3 OTP fuse sets for storing the microphone gain making it possible to change the gain 2 times for re-calibration or other purposes. In order to determine the right register settings for microphone gain in production, as well as in the engineering design phase, the non-volatile OTP registers should be used without OTP programming. This allows you to configure all registers as many times as desired to find the best microphone gain calibration value. Once all the right register settings have been found, the OTP fuse block should be used to store these settings. Figure 52: Register Access I2C READ Production Interface TRSDA/BPL TRSCL/BPR OTP Register 0x30...0x35; 0x10...0x17 STORE ANC/CSDA WRITE LOAD MODE/CSCL WRITE READ OTP Fuses Register Access: This diagram shows the OTP and register architecture of the AS3412. A single OTP cell can be programmed only once. By default, the cell is “0”; a programmed cell contains a “1”. Because it is not possible to reset a programmed bit from “1” to “0”, multiple OTP writes are possible, but only additional un-programmed “0”-bits can be programmed to “1”. ams Datasheet [v1-00] 2016-Apr-06 Page 39 Document Feedback AS3412 − Detailed Description Independent of the OTP programming, it is possible to overwrite the OTP register temporarily if the chip is controlled via I²C. The chip configuration can be stored for example in the flash memory of a Bluetooth- or wireless chipset and can be loaded to the ANC chip during startup of the device via the I²C interface. Because the OTP fuses upload their contents into the OTP register at power-up, the new OTP settings from the microcontroller will overwrite the default settings of the AS3412. All I²C OTP registers settings can be changed as many times as desired, but will be lost during power off. OPT Registers and Fuses: The OTP registers are volatile memory cells which lose the content once the device is switched off. Multiple read and write commands are possible but in order to store chip settings during power off mode, the OTP fuses have to be used. The OTP memory can be accessed in the following ways: • LOAD Operation The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically executed after each power-on-reset. • WRITE Operation The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another WRITE or LOAD operation. • READ Operation The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP memory after a LOAD command. • STORE Operation The STORE operation programs the contents of the OTP register permanently into the OTP fuses. Don’t use old or nearly empty batteries for programming the fuses. Page 40 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description OTP Read/Write and Load Access With the OTP register architecture of the AS3412 it is important to know how to access the registers for reading and writing. Before an I²C read command can be sent there are two registers that have to be configured prior to the desired I²C read command. The flow chart in Figure 53 shows the correct read access sequence. The first step is to configure the EVAL_REG_ ON register. This register enables access to the OTP_MODE register. The OTP_MODE register defines whether you want to read or write to the OTP registers. By setting the OTP_MODE register ‘00’ we select OTP read access. Once the OTP_MODE register has been configured you can start reading from the OTP registers. Figure 53: OTP Read Access Flow Chart Set bit EVAL_REG_ON in register 0x20 Set OTP_MODE register to ‘00'b Read from desired OTP register OTP Read Access Flow Chart: This flow chart shows how to successfully read from an OTP register via the I²C or production trimming interface. The principle for writing to a register is basically the same. The only difference is the configuration of the OTP_MODE register, shown in Figure 54. The first step is to enable the OTP_MODE register by setting the EVAL_REG_ON register to ‘1’. The next step is to configure the OTP_MODE register to ‘10’ in order to select OTP write access. Now you can start writing to any OTP register of AS3412. Figure 54: OTP Write Access Flow Chart Set bit EVAL_REG_ON in register 0x20 Set OTP_MODE register to ‘10'b Write to desired OTP register OTP Write Access Flow Chart: This flow chart shows how to successfully write to an OTP register via the I²C or production trimming interface. ams Datasheet [v1-00] 2016-Apr-06 Page 41 Document Feedback AS3412 − Detailed Description If you want to read out the OTP fuse content, the OTP load function is necessary. In order to load the OTP fuse content to the OTP registers, a special sequence is necessary, as shown in Figure 55. Figure 55: OTP Load Access Flow Chart Set bit EVAL_REG_ON in register 0x20 Dummy read from register 0x30 Set OTP_MODE register to ‘01'b OTP registers are successfully loaded with OTP fuses content Dummy read from register 0x14 Wait 15ms Wait 15ms Dummy read from register 0x10 Dummy read from register 0x34 Wait 15ms OTP Load Access Flow Chart: This flow chart shows how to successfully load the OTP fuse content back to the OTP register via the I²C or production trimming interface. OTP Fuse Process Many wireless applications, like Bluetooth single chips support programmable solutions, as well as ROM versions. As such, it is necessary for ROM versions to store microphone gain compensation data and the general ANC configuration inside the ANC chip. This is necessary because there is no other way to configure the ANC chip during startup. In order to guarantee successful trimming of AS3412 it is necessary to provide a decent environment for the trimming process. Figure 56 shows a principal block diagram for trimming the AS3412 properly in production using the I²C interface. The most important block is the external power supply. Usually it is possible to trim the AS3412 with a single supply voltage of min. 1.8V in laboratory environment, but as soon as it comes to mass production V NEG supply buffering is highly recommended. As highlighted in the block diagram, it is mandatory to get a voltage difference between V POS and VNEG of 3.4V (minimum) to guarantee proper trimming of the device, therefore it is possible to buffer it externally with a negative power supply. The V NEG voltage applied to VNEG pin must be lower than the voltage generated by the charge pump. This means if the typical V NEG output voltage is -1.5V you can apply externally -1.7V. The charge pump enters then automatically skip mode. Page 42 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 56: Production Environment I²C Interface Trimming Voltage has to be >3.4V for proper trimming V Power Supply -1.8V - 1.8V + GND CFL Y VBAT CPP CPN Digital Interface Supply Voltage max. 3.6V GND VNEG CVNEG Charge Pump OTP Memory I2C compatible Hardware E.g. BT chip, MCU, ... I2C Clock I2C Data GND MODE/CSCL ANC/CSDA I2C GND I²C Trimming: This block diagram shows a general overview of the production environment when storing the register settings to the AS3412 using a standard I²C interface. Timing is important, to avoid latch-up, when using an external buffer and switching on the ANC device. The timing diagram in Figure 57 shows that it is important that there is a certain delay requirement between VBAT and the MODE /CSCL pin. This delay is mandatory in order to guarantee that the device starts up properly. The MODE /CSCL pin powers up the ANC device. The whole sequence to power up the internal charge pump of the AS3412 takes approximately 1ms. Once V NEG is settled the external V NEG buffer (e.g. power supply) can be enabled in order to support the charge pump especially during the trim process. ams Datasheet [v1-00] 2016-Apr-06 Page 43 Document Feedback AS3412 − Detailed Description Figure 57: Timing Diagram VNEG Buffering >10ms VBAT ~1ms MODE/CSCL VOL/CSDA ~1ms VNEG OK VNEG BUFFER ON Start Trim-Process VNEG Buffer Timing: This timing diagram shows how to buffer the VNEG supply during the OTP programming process. To guarantee a successful trimming process it is important to follow the predefined trimming sequence shown in Figure 57. As a first step it is important to do a register dump of all OTP registers. This register backup in your system memory is a backup of all register settings and is necessary for verification after the trim process to make sure that all bits are trimmed correctly. Once the register dump has been done it is important to check registers 0x30 and 0x31. These registers typically indicate if the device is already trimmed or not. If both registers have the value 0x80 you can enter the trim mode and start the trimming process. Once trimming is done, the most important step is comparing the values trimmed to the device with the original register dump performed just before we started the actual trimming process. If the verification was successful we know that all bits have been trimmed correctly. What is important to mention is that the AS3412 has a couple of test bits inside which are by default set to ‘1’. We do not recommend overwriting these bits. Furthermore, it is important to know that it is not possible to change bits once they are trimmed. It is not possible to change a bit from ‘1’ back to zero. If an additional trimming is done it is only possible to change bits from ‘0’ to ‘1’. It is important that all necessary bits are trimmed exactly like in the block diagram shown in Figure 58. Page 44 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 58: OTP Programming Process Register dump of OTP registers 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x14 and 0x15 ANC_L and ANC_R registers programmed Start application trim to register 0x30-0x35 and 0x14 and 0x15 Start trim verification with OTP load tests Verification OK? Device trimming failed Is ALT2_ENABLE bit set in 0x11? Start alternative microphone trim to register 0x10 and 0x11 with ALT2_ENABLE bit set Start trim verification with OTP load tests Verification OK? Device trimming failed Is ALT3_ENABLE bit set in 0x13? Start alternative microphone trim to register 0x12 and 0x13 with ALT3_ENABLE bit set Start trim verification with OTP load tests Verification OK? Device trimming failed Device trimming successful Device is already trimmed. No more trimming possible. Exit trimming mode OTP Programming: This flow chart describes the OTP programming process in detail. Besides production trimming using the I²C interface, the AS3412 features a second unique trimming mechanism. This very special mode enables the analog music inputs of the AS3412 to become a production trimming input. ams Datasheet [v1-00] 2016-Apr-06 Page 45 Document Feedback AS3412 − Detailed Description Figure 59: Production Trim Box LINL MUTE Application Trim Box TRSDA/BPL TRSCL/BPR 3x PROM LINR MUTE to HPH AS3412 to HPH Production Trim Box: This block diagram shows the connection of the Trim Box enabling the audio inputs to become a trim input for mass production. With this new system, there is no need for mechanical potentiometers any more. Up to now, operators in production use screw drivers to fine tune the ANC performance of each headset. The disadvantage of this is reliability and cost of potentiometers. Additionally, operators are not always precise in their work, thus yielding inconsistent results. With the new production trimming system from ams there are no mechanical potentiometers required. The operator connects a 3.5mm audio jack to a trimming box and this box enables the audio input of the headset to become the ANC tuning input. This new feature also helps industrial designers of headset because there are no more considerations concerning leakage holes for the old mechanical trimming. Thus, the headset can be fully assembled and ready for the ANC test system at the end of the manufacturing process. The trim box can be easily controlled with an RS232 interface so it is also possible to create fully automated trimming systems. For further details please contact our local sales office; they can provide you with source code examples and application notes. Page 46 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description 2 Wire Serial Interface In order to configure the device using the evaluation software or a MCU the AS3412 features a serial two wire interface. The I²C address for the device can be found in Figure 60. Figure 60: I²C Slave Address 7 Bit I²C Address 8 Bit Read Address 8 Bit Write Address 0x47 0x8F 0x8E I²C Slave Address Table: Shows the I²C address of the AS3412. Protocol Figure 61: I²C Serial Interface Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 1110b (8Eh) DR Device address for read R 1000 1111b (8Fh) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit Stop condition R 1 bit Increment word address internally R during acknowledge P WA++ AS3412 (=slave) transmits data AS3412 (=slave) receives data Symbol Definition: The table shows the symbol definitions being used in the explanations for the data transfer between master and slave. ams Datasheet [v1-00] 2016-Apr-06 Page 47 Document Feedback AS3412 − Detailed Description Figure 62: Byte Write S DW A WA A reg_data A P WA++ Byte Write: This figure shows the sequence for a byte write command. Figure 63: Page Write S DW A WA A reg_data 1 A reg_data 2 WA++ A ... reg_data n WA++ A P WA++ Page Write: This figure shows the sequence for a page write command. Byte Write and Page Write formats are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes to subsequent address locations. For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. Figure 64: Random Read S DW A WA A Sr DR A data N P RA++ Random Read: This figure shows the I²C sequence for a random read function. Page 48 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 65: Sequential Read S DW A WA A Sr DR A reg_data 1 A reg_data 2 RA++ A ... reg_data n RA++ N P RA++ Sequential Read: This figure shows the read sequence for a sequential read command. Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. Different from the Random Read, for a sequential read, the transferred register-data bytes are responded with an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and then generate the STOP condition. Figure 66: Current Address Read S DR A data A RA++ reg_data 2 A RA++ ... reg_data n N P RA++ Current Address Read: This figure shows the I²C read sequence. ams Datasheet [v1-00] 2016-Apr-06 Page 49 Document Feedback AS3412 − Detailed Description To keep the access time as short as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes have to be responded with an acknowledge from the master. For termination of the transmission, the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. Parameter Figure 67: I²C Serial Timing TS T SU TH T HD TL T PD ANC/CSDA MODE/CSCL Start Condition 1-7 8 9 Address R/W ACK 1-7 8 Data 9 ACK 1-7 8 Data 9 ACK Stop Condition I²C Serial Timing: This figure shows the I²C timing diagram. Page 50 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Detailed Description V BAT =1.8V, TA=25ºC, unless otherwise specified. Figure 68: I²C Serial Interface Parameter Symbol Parameter Condition VCSL CSCL, CSDA Low Input Level (max 30% VBAT ) VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70% VBAT ) HYST CSCL, CSDA Input Hysteresis Min Typ Max Unit 0 - 0.42 V 1.16 - 200 450 800 mV - - 0.4 V 50 100 - ns V VOL CSDA Low Output Level Tsp Spike insensitivity TH Clock high time max. 400kHz clock speed 500 ns TL Clock low time max. 400kHz clock speed 500 ns TSU CSDA has to change TSU before rising edge of CSCL 250 - - ns THD No hold time needed for CSDA relative to rising edge of CSCL 0 - - ns TS CSDA H hold time relative to CSDA edge for start/stop/rep_ start 200 - - ns TPD CSDA prop delay relative to low going edge of CSCL at 3mA 50 ns I²C Serial Interface Parameter: This table shows the serial interface timing parameter. ams Datasheet [v1-00] 2016-Apr-06 Page 51 Document Feedback A S 3 4 1 2 − Register Description Register Description Register Overview Figure 69: Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 EVAL_REG_ON - - PWR_HOLD MIC_ON - MICS_CP_ON MICS_ON System Registers 20h SYSTEM 21h PWR_READ 2h-2Fh Reserved DESIGN_VERSION<3:0> 1111 - LOW_BAT PWRUP COMPLETE HPH_ON OTP Registers 10h ANC_R2 TEST_BIT_1 - MICR_VOL_OTP2<5:0> Gain from MICR to QMICR or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 11h ANC_L2 ALT2_ENABLE - MICL_VOL_OTP2<5:0> Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 12h ANC_R3 TEST_BIT_2 - MICR_VOL_OTP3<5:0> Gain from MICR to QMICR or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 13h ANC_L3 ALT3_ENABLE - MICL_VOL_OTP3<5:0> Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 14h ANC_MODE Page 52 Document Feedback HPH_MUX<1:0> 0: MIC; 1: OP1; 2: Do not use; 3: Not connected - LIN_MUTE - - OP1R_ON OP1L_ON ams Datasheet [v1-00] 2016-Apr-06 A S 3 4 1 2 − Register Description Addr Name b5 b4 b3 b2 b1 b0 15h MON_MODE - MON_LIN_ MUTE - - SLIDER_MON DISABLE_ MONITOR 16h PBO_MODE TEST_BIT_4 NO_PBO - PBO_LIN_MUTE - - PBO_OP1R_ ON PBO_OP1L_ ON 17h ECO SLIDE_PWR_ UP - - - ENABLE_HPH_ ECO ENABLE_MIC_ ECO - ENABLE_ OPAMP_ECO 30h ANC_R TEST_BIT_3.1 - MICR_VOL<5:0> Gain from MICR to QMICR or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 31h ANC_L TEST_BIT_6 - MICL_VOL<5:0> Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 32h MIC_MON_R - - MICR_MON<5:0> Gain from MICR to QMICL/R = 0dB...+31dB; MUTE and 63 steps of 0.5dB if MON_MODE is active 33h MIC_MON_L - - MICL_MON<5:0> Gain from MICL to QMICL/R = 0dB...+31dB; MUTE and 63 steps of 0.5dB if MON_MODE is active 34h MODE_1 MICS_CP_OFF MICS_OFF 35h MODE_2 ams Datasheet [v1-00] 2016-Apr-06 b7 b6 MON_HPH_MUX<1:0> 0: MIC; 1: OP1; 2: Do not use; 3: - TEST_BIT_7 - MIC_AGC_ON - MIC_OFF - - CP_OFF HPH_OFF - MICS_DC_OFF DELAY_HPH_ MUX HPH_MODE 0: Stereo 1: Mono Differential I2C_MODE Page 53 Document Feedback A S 3 4 1 2 − Register Description Addr Name b7 b6 b5 b4 b3 b2 b1 b0 PBO_MODE MICR_MUTE MICL_MUTE Evaluation Registers 3Dh EVAL 3Eh CONFIG_1 3Fh CONFIG_2 EVAL_ON - - MASTER_ LIN_MUTE MON_MODE EXTBURNCLK TM34 BURNSW TM_REG34-35 TM_REG30-33 OTP_MODE<1:0> 0: READ; 1: LOAD; 2: WRITE; 3: BURN Register Overview: This table provides a handy overview of all AS3412 registers. Page 54 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Detailed Register Description System Registers Figure 70: SYSTEM Register Description Name Address Default Value SYSTEM 0x20 81h This register contains control bits for monitor mode, OTP register and power up/down functions. Bit Bit Name Default Access Bit Description 7:4 DESIGN_VERSION 1111 R Design version number to identify the design version of the AS3412. 1111: for chip version 1v0 R/W This register controls read and write access to the OTP register banks. 0: Normal operation 1: Enables writing to register 0x3D, 0x3E and 0x3F to configure the OTP and set the access mode. R/W This bit allows an MCU using the I²C interface a power down of the AS3412. A start condition on the I²C interface will wake up the device again. This function works only if the I2C_MODE bit is set before you write this register. 0: Power up hold is cleared and chip powers down 1: It is automatically set to on after power on 3 0 EVAL_REG_ON PWR_HOLD ams Datasheet [v1-00] 2016-Apr-06 0 1 Page 55 Document Feedback AS3412 − Register Description Figure 71: PWR_SET Register Description Name Address Default Value PWR_READ 0x21 0x3F A readout of this register returns the status of each block o f the chip. Bit Bit Name Default Access Bit Description 6 LOW_BAT x R VBAT supervisor status 0: VBAT is above brown out level 1: VBAT has reached brown out level 5 PWRUP_ COMPLETE x R Power-up sequencer status 0: Power-up sequence incomplete 1: Power-up sequence completed R This register returns the power status of the headphone amplifier. 0: Headphone amplifier switched off 1: Headphone amplifier switched on R This register returns the power status of the microphone preamplifier. 0: Microphone preamplifier switched off 1: Microphone preamplifier switched on R This register returns the power status of the microphone charge pump. 0: Microphone charge pump switched off 1: Microphone charge pump switched on R This register returns the power status of the microphone supply (MICS). 0: Microphone supply switched off 1: Microphone supply switched on 4 3 1 0 HPH_ON MIC_ON MICS_CP_ON MICS_ON Page 56 Document Feedback 0 0 0 0 ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description OTP Register Figure 72: ANC_R2 Register Description Name Address Default Value ANC_R2 0x10 80h The ANC_R2 register configures the gain for the right microphone input. This register is the first alternative microphone gain register for OTP programming in case the ANC_R register is already programmed. Bit 7 5:0 Bit Name TEST_BIT_1 MICR_VOL_ OTP2<6:0> ams Datasheet [v1-00] 2016-Apr-06 Default Access 1 R Test register. Please do not write this register. R/W Volume settings for right microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0 dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain … 11 1110: 30.5dB gain 11 1111: 31dB gain 000 0000 Bit Description Page 57 Document Feedback AS3412 − Register Description Figure 73: ANC_L2 Register Description Name Address Default Value ANC_L2 0x11 00h The ANC_L2 Register configures the gain for the left microphone input. This register is the first alternative microphone gain register for OTP programming in case the ANC_L register is already programmed. Bit 7 5:0 Bit Name ALT2_ENABLE MICL_VOL_ OTP2<6:0> Page 58 Document Feedback Default 0 000 0000 Access Bit Description R/W In case the register is being used for microphone programming this bit has to be set. The bit is being used by the internal state machine of the AS3412 to determine which alternative microphone gain register has to be used during startup. 0: Microphone registers 0x10 and 0x11 are not active 1: Microphone registers 0x10 and 0x11 are active. Gain settings in registers 0x30 and 0x31 are ignored R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain … 11 1110: 30.5dB gain 11 1111: 31dB gain ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 74: ANC_R3 Register Description Name Address Default Value ANC_R3 0x12 80h The ANC_R3 Register configures the gain for the right microphone input. This register is the second alternative microphone gain register for OTP programming in case the ANC_R and ANC_R2 registers are already programmed. Bit Bit Name Default Access 7 TEST_BIT_6 1 R Test register. Please do not write this register. R/W Volume settings for right microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain … 11 1110: 30.5dB gain 11 1111: 31dB gain 5:0 MICR_VOL_ OTP3<6:0> ams Datasheet [v1-00] 2016-Apr-06 000 0000 Bit Description Page 59 Document Feedback AS3412 − Register Description Figure 75: ANC_L3 Register Description Name Address Default Value ANC_L3 0x13 00h The ANC_L3 Register configures the gain for the left microphone input. This register is the second alternative microphone gain register for OTP programming in case the ANC_L and ANC_L2 registers are already programmed. Bit 7 5:0 Bit Name ALT3_ENABLE MICL_VOL_ OTP3<6:0> Page 60 Document Feedback Default 0 000 0000 Access Bit Description R/W In case the register is being used for microphone programming this bit has to be set. The bit is being used by the internal state machine of the AS3412 to determine which alternative microphone gain register has to be used during startup. 0: Microphone registers 0x12 and 0x13 are not active 1: Microphone registers 0x12 and 0x13 are active. Gain settings in registers 0x30, 0x31, 0x10 and 0x11 are ignored. R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain … 11 1110: 31dB gain 11 1111: 31dB gain ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 76: ANC_MODE Register Description Name Address Default Value ANC_MODE 0x14 00h The ANC_MODE register controls various settings for the chipset in active noise cancelling mode like which amplifiers are enabled as well as which audio inputs are active. Bit 7:6 4 1 0 Bit Name HPH_MUX<1:0> LIN_MUTE OP1R_ON OP1L_ON ams Datasheet [v1-00] 2016-Apr-06 Default 00 0 0 0 Access Bit Description R/W This register selects the ANC input source for the headphone amplifier in ANC mode. Depending on the register setting the outputs of microphone preamplifier or OPAMP1 can be connected to the headphone amplifier input. It is also possible to disconnect all ANC input sources which is sometimes desired in monitor mode. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use this setting 11: Nothing connected to HPH input except line input in case it is enabled. R/W This bit mutes the line input signal. If the bit is set the line input signal is disconnected from the headphone amplifier. 0: Line input signal enabled 1: Line input signal muted R/W This register enables the right channel of OPAMP 1 in ANC mode. 0: Right OP1 is switched off 1: Right OP1 is switched on R/W This register enables the left channel of OPAMP 1 in ANC mode. 0: Left OP1 is switched off 1: Left OP1 is switched on Page 61 Document Feedback AS3412 − Register Description Figure 77: MONITOR_MODE Register Description Name Address Default Value MONITOR_MODE 0x15 00h The MONITOR_MODE register controls various settings for the chipset in monitor mode like line input monitor mode attenuation as well as which audio inputs are active. Bit 7:6 4 Bit Name MON_HPH_ MUX<1:0> MON_LIN_MUTE 1 SLIDER_MON 0 DISABLE_ MONITOR Page 62 Document Feedback Default 00 0 0 0 Access Bit Description R/W This register selects the ANC input source for the headphone amplifier in monitor mode. Depending on the register setting the outputs of microphone preamplifier, OPAMP1, OPAMP2 can be connected to the headphone amplifier input. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use this setting 11: Nothing connected to HPH input except line input. R/W This bit mutes the audio line input pin in Monitor mode. 0: Line input enabled in Monitor mode 1: Line input muted in Monitor mode R/W This bit enables the Full Slider Mode configuration. Please mind that this bit must not be set without setting SLIDE_PWR_UP to ‘1’. 0: Slider Mode activated 1: Full Slider Mode activated R/W This bit disables the monitor mode in push button control mode. 0: Monitor mode enabled 1: Monitor mode disabled ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 78: PBO_MODE Register Description Name Address Default Value PBO_MODE 0x16 0x00 The PBO_MODE register controls various settings for the chipset in playback only mode like which amplifiers are enabled as well as which audio inputs are active. Bit Bit Name Default Access 7 TEST_BIT_4 1 R 6 4 1 0 NO_PBO PBO_LIN_MUTE PBO_OP1R_ON PBO_OP1L_ON ams Datasheet [v1-00] 2016-Apr-06 0 0 0 0 Bit Description Test register. Please do not write this register. R/W This bit disables the playback only mode function. No external pull up resistor is required on ANC / CSDA pin is necessary if this bit is set to ‘1’ 0: Playback only mode enabled 1: Playback only mode disabled R/W This bit enables the eco mode of the microphone preamplifier. 0: Power save function disabled 1: Power save function enabled R/W This register enables the right channel of OPAMP 1 in playback only mode. 0: Right OP2 is switched off 1: Right OP2 is switched on R/W This register enables the left channel of OPAMP 1 in playback only mode. 0: Left OP2 is switched off 1: Left OP2 is switched on Page 63 Document Feedback AS3412 − Register Description Figure 79: ECO Register Description Name Address Default Value ECO 0x17 0x00 This register controls the economic (ECO) mode for all analog audio blocks. Furthermore it includes also other general settings. Bit Bit Name 7 SLIDE_PWR_UP 3 ENABLE_HPH_ ECO 2 ENABLE_MIC_ ECO 0 ENABLE_OPAMP_ ECO Default Access 0 0 0 0 Bit Description R/W This bit enables the slide switch control mode of the AS3512. If this bit is programmed the device can be powered up and powered down via a slide switch. 0: Slide switch control disabled 1: Slide switch control enabled R/W This bit enables the eco mode of the headphone amplifier. 0: Power save function disabled 1: Power save function enabled R/W This bit enables the eco mode of the microphone amplifier. 0: Power save function disabled 1: Power save function enabled R/W This bit enables the eco mode of the operational amplifier amplifiers for ANC filter design. 0: Power save function disabled 1: Power save function enabled Figure 80: ANC_R Register Description Name Address Default Value ANC_R 0x30 80h The ANC_R Register configures the gain for the right microphone input. Bit Bit Name Default Access 7 TEST_BIT_5 1 R/W Please do not write this register. R/W Volume settings for right microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1dB gain … 11 1110: 30dB gain 11 1111: 31dB gain 5:0 MICR_VOL<5:0> Page 64 Document Feedback 000 0000 Bit Description ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 81: ANC_L Register Description Name Address Default Value ANC_L 0x31 0x80 The ANC_L Register configures the gain for the left microphone input. Bit Bit Name Default Access 7 TEST_BIT_6 1 R/W Please do not write this register. R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain … 11 1110: 30.5dB gain 11 1111: 31dB gain 5:0 MICL_VOL_ OTP<5:0> 000 0000 Bit Description Figure 82: MIC_MON_R Register Description Name Address Default Value MIC_MON_R 0x32 0x00 This register controls the microphone gain in monitor mode for the right microphone channel. Bit 5:0 Bit Name MICR_MON<5:0> ams Datasheet [v1-00] 2016-Apr-06 Default 00 0000 Access Bit Description R/W Monitor mode gain setting for right microphone input adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0.5dB gain 00 0010: 1dB gain 00 0011: 1.5dB gain … 11 1110: 30.5dB gain 11 1111: 31dB gain Page 65 Document Feedback AS3412 − Register Description Figure 83: MIC_MON_L Register Description Name Address Default Value MIC_MON_L 0x33 0x00 This register controls the microphone gain in monitor mode for the left microphone channel. Bit 5:0 Bit Name MICL_MON<5:0> Page 66 Document Feedback Default 00 0000 Access Bit Description R/W Monitor mode gain setting for left microphone input adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0.5dB gain 00 0010: 1dB gain 00 0011: 1.5dB gain … 11 1110: 30.5dB gain 11 1111: 31dB gain ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 84: MODE_1 Register Description Name Address Default Value MODE_1 0x34 0x00 This register controls miscellaneous settings of the AS3512. Bit 7 6 Bit Name MICS_CP_OFF MICS_OFF Default 0 0 Access Bit Description R/W This bit controls the microphone supply charge pump. The microphone charge pump has a second function besides the bias voltage generation for microphones. It is also used to disable the integrated music bypass switch if the AS3412 is active. In case the integrated bypass switch is used in an application the MICS_CP_ OFF bit must not be set to ‘1’. 0: Microphone supply charge pump enabled 1: Microphone supply charge pump disabled R/W This bit controls the microphone supply. In case this bit is set to ‘1’ the MICS pin is disconnected from the internal microphone supply. 0: Microphone supply switched on 1: Microphone supply switched off 5 MIC_AGC_ON 0 R/W This bit disables the automatic gain control of the microphone preamplifier. 0: AGC disabled 1: AGC enabled 4 MIC_OFF 0 R/W This bit powers down the microphone preamplifier. 0: Microphone preamplifier enabled 1: Microphone preamplifier disabled R/W This bit disables the VNEG charge pump in case there is already a negative supply present in a system. 0: VNEG charge pump enabled 1: VNEG charge pump enabled R/W This bit allows the user to power down headphone amplifier in case it is not used in the final application in order to save system power. 0: Headphone amplifier enabled 1: Headphone amplifier disabled 2 1 CP_OFF HPH_OFF ams Datasheet [v1-00] 2016-Apr-06 0 0 Page 67 Document Feedback AS3412 − Register Description Figure 85: MODE_2 Register Description Name Address Default Value MODE_2 0x35 0x00 This register controls miscellaneous settings of the AS3512. Bit Bit Name Default Access 7 TEST_BIT_7 1 R/W Test register. Please do not write this register. R/W This bit disables the internal microphone supply discharge function if the microphone supply is switched off. 0: MICS discharge enabled 1: MICS discharge disabled R/W With this bit it is possible to delay the HPH_MUX setting during startup of the device to avoid unwanted pop noise in case of long charging times of external components. 0: HPH_MUX_OTP delay disabled 1: HPH_MUX_OTP delay enabled 3 2 MICS_DC_OFF DELAY_HPH_ MUX 0 0 Bit Description 1 HPH_MODE 0 R/W This register controls the operating mode of the headphone amplifier. The headphone amplifier supports single ended mode and differential mode. In differential output mode the right audio signal path is the active input signal for the headphone amplifier. 0: Stereo single ended mode 1: Mono differential mode 0 I2C_MODE 0 R/W This bit enables I²C power down of the AS3412. 0: I²C power down disabled 1: I²C power down enabled via PWR_HOLD bit. Page 68 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Evaluation Register Figure 86: EVAL Register Description Name Address Default Value EVAL 0x3D 0x00 This register enables miscellaneous operating modes, that are typically controlled via slide switch or push button, for evaluation purposes or MCU controlled applications. Bit 4 3 2 1 0 Bit Name MASTER_LIN_ MUTE MON_MODE PBO_MODE MICR_MUTE MICL_MUTE ams Datasheet [v1-00] 2016-Apr-06 Default 0 0 0 0 0 Access Bit Description R/W This register is the master register for the line input mute function. No matter in what operating mode the device is working the LINE_MUTE bit overrules any other setting in any operation mode. 0: Line Input master mute disabled 1: Line Input master mute enabled R/W This bit enables the monitor mode of AS3415/35 which can normally be enabled by pulling the MODE pin to VBAT/2. In case an MCU is connected to the device the Monitor mode can be enabled by setting this bit. 0: Monitor mode deactivated 1: Monitor mode activated R/W This bit enables the playback mode of AS3412 which can normally be enabled by pulling the ANC pin to 0V. In case an MCU is connected to the device Monitor mode can be enabled by setting this bit. 0: Monitor mode deactivated 1: Monitor mode activated R/W This register is the master mute register for the left microphone amplifier. No matter in what operating mode the device is working the MICL_MUTE bit overrules any other setting in any operation mode. 0: Mute disabled 1: Mute enabled R/W This register is the master mute register for the left microphone amplifier. No matter in what operating mode the device is working the MICR_MUTE bit overrules any other setting in any operation mode. 0: Mute disabled 1: Mute enabled Page 69 Document Feedback AS3412 − Register Description Figure 87: CONFIG_1 Register Description Name Address Default Value CONFIG_1 0x3E 0x00 This bit controls the OTP programming clock source. Bit 3 Bit Name EXTBURNCL Page 70 Document Feedback Default 0 Access R/W Bit Description This register controls the clock source for OTP programming. Typically the internal clock is being used for OTP programming. 0: External burn clock disabled 1: External burn clock enabled ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 88: CONFIG_2 Register Description Name Address Default Value CONFIG_2 0x3F 0x00 This register controls the register access to all OTP registers. In order to get access to these registers it is necessary to set EVAL_REG_ON bit to ‘1’. Bit 5 4 3 2 1:0 Bit Name TM34 BURNSW TM_REG34-35 TM_REG30-33 OTP_MODE<1:0> ams Datasheet [v1-00] 2016-Apr-06 Default 0 0 0 0 00 Access Bit Description R/W This Register defines the register bank selection for register 0x30-0x35 and 0x10-0x17. Depending on TM34 you can select either between Register bank 0x10-0x17 or 0x30h-0x34. 0: Test mode Registers 14h-17h and 10h-13h disabled test mode Registers 30h-33h and 34h-37h enabled 1: Test mode Registers 14h-17h and 10h-13h enabled test mode Registers 30h-33h and 34h-37h disabled R/W This register controls the internal buffer switch from line input to VNEG for VNEG buffering during OTP programming. 0: BURN switch disabled 1: BURN switch enabled R/W 0: Register 34h-35h disabled Register 14h-17h disabled 1: Register 34h-35h enabled Register 14h-17h enabled R/W 0: Register 30h-33h disabled Register 10h-13h disabled 1: Register 30h-33h enabled Register 10h-13h enabled R/W This register controls the OTP access. 00: READ 01: LOAD 10: WRITE 11: BURN Page 71 Document Feedback A S 3 4 1 2 − Application Information Application Information Schematic Figure 89: Push Button Operation Mode – Application Example VBAT MICS 1.8V – 1.65V Left ANC Filter R1 2k2 C2 R3 150 C5 AGND B1 B3 CPN VBAT D3 D2 IOP1L QOP1L E3 E2 QMICL HPL MICS ANC/CSDA On / Off / Monitor AGND HPR MODE/CSCL B5 AGND TRSCL/BPR AGND S1 Push Button WL-CSP IOP1R Music Input D5 AS3412 LINR QMICR E1 VBAT R5 VNEG QOP1R A2 A1 C5 10µF GND VNEG GND A3 Speaker Left D1 B2 AGND MICS E4 R2 A4 C6 Speaker Right C7 220 10µF 22µF B4 C2 CPP LINL MICR 4.7µF TRSDA/BPL A5 C9 C1 MICACR 4.7µF U1 GND C4 C8 C3 E5 L 3 AGND MICL AGND MICACL 10uF AGND D4 1µF C4 2k2 R4 150 C3 1uF Left ANC MIC R 2 GND 1 4.7µF GND MIC1 U2 C1 GND MICS GND C10 AGND R6 MIC2 2k2 C11 1uF 10uF AGND Right ANC Filter Right ANC MIC R7 2k2 AGND AGND Push Button Operation Mode – Application Example: This application example shows the typical schematic in push button configuration for a Feed-Forward ANC headset. A single push button can control the headset. For details on Push Button control please refer to chapter Operation Modes. Page 72 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 A S 3 4 1 2 − Application Information Figure 90: Slider Operation Mode – Application Example VBAT MICS 1.8V – 1.65V Left ANC Filt er R1 C1 4.7µF 2k2 GND MIC1 C2 Left ANC MIC R3 AGND AGND GND AGND ON OFF B1 B3 CPN VBAT D2 QOP1L D3 IOP1L QMICL E3 E2 MICS ANC/CSDA GND IOP1R S3 HPL MODE/CSCL AGND S2 R9 22k C5 HPR QOP1R A2 A1 C5 10µF GND VNEG GND A3 Speaker Left D1 B2 AGND E4 MICS R2 A4 C6 Speaker Right C7 220 10µF 22µF B4 D5 R8 22k WL-CSP TRSCL/BPR B5 150 MO NITOR R5 R4 150 Music Input VNEG AS3412 LINR QMICR E1 VBAT R 2 GND 1 C2 CPP LINL A5 4.7µF TRSDA/BPL MICR C9 C1 MICACR 4.7µF U1 GND E5 C8 C3 C4 L 3 AGND MICL AGND MICACL 10uF AGND D4 1µF C4 2k2 U2 C3 1uF GND MICS GND C10 AGND R6 MIC2 2k2 C11 1uF 10uF AGND Right ANC Filt er Right ANC MIC R7 2k2 AGND AGND Slider Operation Mode – Application Example: This application example shows the typical schematic in Slider configuration for a Feed-Forward ANC headset. A 3 pole slider is being used to switch the AS3412 on and off. A push button is used to enter Monitor mode. ams Datasheet [v1-00] 2016-Apr-06 Page 73 Document Feedback A S 3 4 1 2 − Application Information Figure 91: Full Slider Operation Mode – Application Example VBAT MICS 1.8V – 1.65V Left ANC Filt er R1 2k2 C2 R3 R9 22k S4 AGND AGND GND AGND OFF ON C5 R10 1M B1 B3 CPN VBAT D2 QOP1L D3 IOP1L QMICL E3 E2 MICS ANC/CSDA GND QOP1R MON A1 C5 10µF GND GND A3 Speaker Left D1 B2 AGND E4 MICS R2 A4 C6 Speaker Right C7 220 10µF GND AGND R6 2k2 VNEG 22µF GND C10 MICS MIC2 HPL MODE/CSCL IOP1R D5 HPR A2 B4 R8 22k AGND R5 150 WL-CSP TRSCL/BPR B5 R4 VNEG AS3412 LINR QMICR E1 VBAT 150 C2 CPP LINL A5 4.7µF TRSDA/BPL MICR C9 C1 MICACR 4.7µF U1 GND E5 C8 C3 C4 L 3 AGND MICL AGND MICACL 10uF AGND D4 1µF C4 2k2 Music Input C3 1uF Left ANC MIC R 2 GND 1 4.7µF GND MIC1 U2 C1 C11 1uF 10uF AGND Right ANC Filt er Right ANC MIC R7 2k2 AGND AGND Full Slider Operation Mode – Application Example: This application example shows the typical schematic in Full Slider configuration for a Feed-Forward ANC headset. A multi pole slide switch is being used to switch the AS3412 on, off and enter Monitor mode. Page 74 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Application Information External Components This chapter provides detailed information concerning recommended external components such as capacitors and resistors. Figure 92: External Components Symbol Parameter Temp. Characteristic Min. Rated Voltage Max. Tolerance Min. Nom. Capacitance Capacitors C1, CVBAT Input Capacitor Y5R; X5R 4V ±20% 4.7μF C3, CFLY VNEG charge pump flying capacitor Y5R; X5R 4V ±20% 1μF C4, C10, CACR, CACR AC coupling capacitor Y5R; X5R 4V ±10% 10μF C5, CVNEG Output Capacitor Y5R; X5R 4V ±20% 10μF C8, C9 AC coupling input capacitor Y5R; X5R 4V ±20% 4.7μF C6, CMICS Output Capacitor Y5R; X5R 4V ±20% 10μF C7 Output Capacitor (optional component) Y5R; X5R 4V ±20% 22μF C2, C11, CMICL, CMICR AC coupling capacitor; value depends on ANC filter design Y5R; X5R 4V ±10% - CFILTER ANC filter related capacitors Y5R; X5R 4V ±10% - Resistors R1, R6 Bias current resistor for microphones - - 5% 2.2kΩ R4, R5 Pull down resistors to avoid humming noise - - 5% 150Ω R3, R7 Microphone input high pass filter; value depends on ANC filter design - - 5% - R2 Microphone supply filter resistor (optional component) - - 10% 220Ω RFILTER ANC filter related resistors - - 1% - External Components: This table provides detailed information concerning the recommended external components to operate AS3412. ams Datasheet [v1-00] 2016-Apr-06 Page 75 Document Feedback AS3412 − Package Drawings & Mark ings Package Drawings & Markings Figure 93: Package Drawings WL-CSP 40 ccc 26 0 80 30 0 32 2.50 40 0 40 0 21 60 40 0 40 0 28 2.50 31 7.5 22 typ. 378 typ. Ball center to ed ge die size after cutti ng (Y2): 322.50μm Die size after cutting: 2235 x 2205 ± 20μm 80 29 5 40 0 40 0 40 0 40 0 200 typ. 29 5 600 ± 30 Ball center to ed ge die size after cutti ng (X2): 317.5 μm 31 7.50 21 90 RoHS Green Package Drawing: This figure shows the package drawing of the AS3412. Note(s): 1. Pin 1 = A1 2. ccc Coplanarity 3. All dimensions are in μm Page 76 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Package Drawings & Markings Figure 94: Package Marking Package Marking: This figure shows the package marking of the AS3412. AS3412 XXXXX Figure 95: Package Code XXXXX Tracecode Package Code: This table shows the package code of the AS3412 WL-CSP package. ams Datasheet [v1-00] 2016-Apr-06 Page 77 Document Feedback AS3412 − Ordering & Contact Information Ordering & Contact Information Figure 96: Ordering Information Ordering Code Package Marking Delivery Form Delivery Quantity AS3412-EWLT WL-CSP AS3412 Tape & Reel 10000 pcs/reel Ordering Information: Shows the ordering information of the AS3412. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: [email protected] For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30 8141 Premstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Page 78 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − RoHS Compliant & ams Green Statement RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. ams Datasheet [v1-00] 2016-Apr-06 Page 79 Document Feedback AS3412 − Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. Page 80 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Document Status Document Status Document Status Product Preview Preliminary Datasheet Datasheet Datasheet (discontinued) ams Datasheet [v1-00] 2016-Apr-06 Product Status Definition Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Page 81 Document Feedback AS3412 − Revision Information Revision Information Changes from 0-91 (2016-Mar-22) to current revision 1-00 (2016-Apr-06) Page Initial production version for release Updated Figure 7 8 Updated Figure 14 14 Updated Figure 19 18 Updated Figure 23 21 Updated Figure 35 29 Updated Figure 68 51 Note(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 2. Correction of typographical errors is not explicitly mentioned. Page 82 Document Feedback ams Datasheet [v1-00] 2016-Apr-06 AS3412 − Content Guide Content Guide ams Datasheet [v1-00] 2016-Apr-06 1 1 1 2 General Description Key Benefits & Features Applications Block Diagram 3 3 3 Pin Assignment Pin Diagram Pin Description 5 7 Absolute Maximum Ratings Electrical Characteristics 9 9 10 10 11 14 17 18 19 21 25 26 28 29 31 31 32 33 34 35 36 37 38 38 39 41 42 47 47 50 Detailed Description Audio Line Input Parameter Microphone Inputs Input Capacitor Selection Parameter Microphone Supply Parameter Headphone Amplifier Parameter Integrated Music Bypass Switch Parameter Operational Amplifier Parameter System Power Up/Down Conditions Start-Up Sequence Operation Modes Full Slider Mode Slider Mode Push Button Mode Playback Only Mode VNEG Charge Pump Parameter OTP Memory and Internal Registers OTP Read/Write and Load Access OTP Fuse Process 2 Wire Serial Interface Protocol Parameter 52 52 55 55 57 69 Register Description Register Overview Detailed Register Description System Registers OTP Register Evaluation Register Page 83 Document Feedback AS3412 − Content Guide Page 84 Document Feedback 72 72 75 Application Information Schematic External Components 76 78 79 80 81 82 Package Drawings & Markings Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information ams Datasheet [v1-00] 2016-Apr-06