ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 12-BIT 200-kHz MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • Qualified for Automotive Applications • 200-kHz Sampling Rate • Micropower: 1.6 mW at 200 kHz 0.54 mW at 75 kHz 0.06 mW at 7.5 kHz • Power-Down Current: 3 µA Max • MSOP-8 Package • Pseudo-Differential Input • Serial Interface • • • • 1 2 Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems DESCRIPTION The ADS7822 is a 12-bit sampling analog-to-digital (A/D) converter with ensured specifications over a 2.7-V to 5.25-V supply range. It requires very little power even when operating at the full 200-kHz rate. At lower conversion rates, the high speed of the device enables it to spend most of its time in the power-down mode—the power dissipation is less than 60 µW at 7.5 kHz. The ADS7822 also features operation from 2.0 V to 5 V, a synchronous serial interface, and a pseudo-differential input. The reference voltage can be set to any level within the range of 50 mV to VCC. Ultra low power and small size make the ADS7822 ideal for battery-operated systems. It is also a perfect fit for remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS7822 is available in an MSOP-8 package. Control SAR VREF DOUT +In Serial Interface CDAC -In S/H Amp Comparator DCLOCK CS/SHDN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) MSOP – DGK Reel of 2500 ORDERABLE PART NUMBER ADS7822IDGKRQ1 TOP-SIDE MARKING OCV For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage 6V Analog inputs –0.3 V to VCC + 0.3 V VIN Input voltage TC Case temperature 100°C TJ Junction temperature 150°C TSTG Storage temperature 125°C VREF External reference voltage 5.5 V (1) 2 Logic inputs –0.3 V to 6 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 ELECTRICAL CHARACTERISTICS: +VCC = 2.7 V At –40°C to 85°C, +VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 75 kHz, and fCLK = 16 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span Absolute input range +In – (–In) 0 VREF V +In – GND –0.2 VCC + 0.2 V –In – GND –0.2 +1.0 V Capacitance 25 pF Leakage current ±1 µA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes 11 Integral linearity error –2 ±0.5 +2 LSB (1) Bits Differential linearity error –2 ±0.5 +2 LSB Offset error –3 +3 LSB Gain error –3 +3 LSB Noise 33 µVrms Power-supply rejection 82 dB 12 Clk Cycles SAMPLING DYNAMICS Conversion time Acquisition time (2) 1.5 Clk Cycles Throughput rate 75 kHz DYNAMIC CHARACTERISTICS Total harmonic distortion VIN = 2.5 VPP at 1 kHz –82 dB SINAD VIN = 2.5 VPP at 1 kHz 71 dB Spurious-free dynamic range VIN = 2.5 VPP at 1 kHz 86 dB REFERENCE OUTPUT Voltage range 0.05 Resistance Current drain VCC CS = GND, fSAMPLE = 0 Hz 5 CS = VCC 5 At code 710h 8 fSAMPLE = 7.5 kHz GΩ GΩ 40 0.001 µA µA 0.8 CS = VCC V 3 µA DIGITAL INPUT/OUTPUT Logic family Logic levels CMOS VIH IIH = +5 µA 2.0 5.5 V VIL IIL = +5 µA –0.3 0.8 V VOH IOH = –250 µA VOL IOL = 250 µA Data format (1) (2) 2.1 V 0.4 V Straight Binary LSB means least significant bit. With VREF equal to 2.5 V, one LSB is 0.61 mV. Not production tested Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 3 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: +VCC = 2.7 V (continued) At –40°C to 85°C, +VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 75 kHz, and fCLK = 16 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY REQUIREMENTS Specified performance VCC See Notes See Note Quiescent current Power down current (3) and (4) (4) 2.7 3.6 V 2.0 2.7 V 2.7 3.6 fSAMPLE = 7.5 kHz (5) (6) fSAMPLE = 75 kHz (6) 200 CS = VCC V µA 20 325 µA 10 µA 85 °C TEMPERATURE RANGE Specified performance (3) (4) (5) (6) 4 –40 The maximum clock rate of the ADS7822 is less than 1.2 MHz in this power-supply range. See the Typical Characteristics for more information. fCLK = 1.2 MHz, CS = VCC for 145 clock cycles out of every 160. See the Power Dissipation section for more information regarding lower sample rates. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 ELECTRICAL CHARACTERISTICS: +VCC = 5 V At –40°C to 85°C, +VCC = 5 V, VREF = 5 V, fSAMPLE = 200 kHz, and fCLK = 16 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span Absolute input range +In – (–In) 0 VREF V +In – GND –0.2 VCC + 0.2 V –In – GND –0.2 +1.0 V Capacitance 25 pF Leakage current ±1 µA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes 11 Integral linearity error –2 Differential linearity error Bits +2 LSB (1) ±0.8 Offset error –3 Gain error –4 LSB +3 LSB +4 LSB Noise 33 µVrms Power-supply rejection 70 dB 12 Clk Cycles SAMPLING DYNAMICS Conversion time Acquisition time (2) 1.5 Clk Cycles Throughput rate 200 kHz DYNAMIC CHARACTERISTICS Total harmonic distortion VIN = 5 VPP at 10 kHz –78 dB SINAD VIN = 5 VPP at 10 kHz 71 dB Spurious-free dynamic range VIN = 5 VPP at 10 kHz 79 dB REFERENCE OUTPUT Voltage range 0.05 Resistance CS = GND, fSAMPLE = 0 Hz 5 CS = VCC 5 At code 710h Current drain VCC 40 fSAMPLE = 12.5 kHz GΩ GΩ 100 0.001 µA µA 2.5 CS = VCC V 3 µA DIGITAL INPUT/OUTPUT Logic family Logic levels CMOS VIH IIH = +5 µA 3.0 5.5 V VIL IIL = +5 µA –0.3 0.8 V VOH IOH = –250 µA VOL IOL = 250 µA 3.5 V 0.4 Data format V Straight Binary POWER-SUPPLY REQUIREMENTS VCC Specified performance Quiescent current fSAMPLE = 200 kHz Power down current CS = VCC 4.75 320 5.25 V 550 µA 10 µA 85 °C TEMPERATURE RANGE Specified performance (1) (2) –40 LSB means least significant bit. With VREF equal to 5 V, one LSB is 1.22 mV. Not production tested Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 5 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com PIN CONFIGURATION DGK PACKAGE (TOP VIEW) VREF 1 +In 2 8 +VCC 7 DCLOCK ADS7822 -In 3 6 DOUT GND 4 5 CS/SHDN PIN ASSIGNMENTS PIN NAME DESCRIPTION NO. VREF 1 Reference input +In 2 Noninverting input –In 3 Inverting input. Connect to ground or to remote ground sense point. GND 4 Ground CS/SHDN 5 Chip select when low; shutdown mode when high. DOUT 6 The serial output data word is comprised of 12 bits of data. In operation, the data are valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit, the data are valid for the next edges. DCLOCK 7 Data clock synchronizes the serial data transfer and determines conversion speed. +VCC 8 Power supply 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 TYPICAL CHARACTERISTICS TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 75 kHz, fCLK = 16 × fSAMPLE (unless otherwise noted) DIFFERENTIAL LINEARITY ERROR vs CODE 1.00 1.00 0.75 0.75 Differential Linearity Error (LSB) Integral Linearity Error (LSB) INTEGRAL LINEARITY ERROR vs CODE 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 0 2048 4095 0 2048 4095 Code Figure 1. Figure 2. SUPPLY CURRENT vs TEMPERATURE POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 350 120 300 100 Supply Current (nA) Supply Current (mA) Code 250 200 150 80 60 40 20 100 0 50 -50 0 -25 25 50 75 100 -50 0 -25 25 50 75 Temperature (°C) Temperature (°C) Figure 3. Figure 4. QUIESCENT CURRENT vs VCC MAXIMUM SAMPLE RATE vs VCC 400 100 1000 Sample Rate (kHz) Quiescent Current (mA) 350 300 250 200 100 10 150 100 1 1 2 3 4 5 1 VCC (V) 2 3 4 5 VCC (V) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 7 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 75 kHz, fCLK = 16 × fSAMPLE (unless otherwise noted) CHANGE IN OFFSET vs REFERENCE VOLTAGE CHANGE IN OFFSET vs TEMPERATURE 1.2 0.6 VCC = 5V 0.4 0.8 Delta from 25°C (LSB) Change in Offset (LSB) 1.0 0.6 0.4 0.2 0.0 -0.2 -0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 1 2 3 Reference Voltage (V) 4 5 -50 0 25 50 75 100 75 100 Temperature (°C) Figure 7. Figure 8. CHANGE IN GAIN vs REFERENCE VOLTAGE CHANGE IN GAIN vs TEMPERATURE 2.5 0.15 V = 5V VCC CC = 5V 2.0 0.10 1.5 Delta from 25°C (LSB) Change in Gain (LSB) -25 1.0 0.5 0.0 -0.5 0.05 0 -0.05 -0.10 -1.0 -0.15 -1.5 1 2 3 Reference Voltage (V) 4 -50 5 25 50 Figure 9. Figure 10. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 10 VCC = 5V 11.75 VCC = 5V 9 Peak-to-Peak Noise (LSB) Effective Number of Bits (rms) 0 Temperature (°C) 12.00 11.50 11.25 11.00 10.75 10.50 10.25 8 7 6 5 4 3 2 1 10.00 0 0.1 1 10 0.1 1 10 Reference Voltage (V) Reference Voltage (V) Figure 11. 8 -25 Figure 12. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 75 kHz, fCLK = 16 × fSAMPLE (unless otherwise noted) SPURIOUS FREE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 100 0 Spurious Free Dynamic Range SFDR and SNR (dB) 80 70 60 Signal-to-Noise Ratio 50 40 30 20 -30 -40 -50 -60 -70 -80 -90 0 -100 10 100 1 10 100 Frequency (kHz) Frequency (kHz) Figure 13. Figure 14. SIGNAL-TO-(NOISE+DISTORTION) vs FREQUENCY SIGNAL-TO-(NOISE+DISTORTION) vs INPUT LEVEL Signal-to-(Noise Ratio + Distortion) (dB) 100 Signal-to-(Noise + Distortion) (dB) -20 10 1 90 80 70 60 50 40 30 20 10 0 1 10 80 70 60 50 40 30 20 10 0 100 -40 -35 -30 -25 -20 -15 -10 -5 Frequency (kHz) Input Level (dB) Figure 15. Figure 16. REFERENCE CURRENT vs SAMPLE RATE REFERENCE CURRENT vs TEMPERATURE (Code = 710h) 14 14 12 12 Reference Current (A) Reference Current (mA) -10 Total Harmonic Distortion (dB) 90 10 8 6 4 0 10 8 6 4 2 2 0 0 15 30 45 60 75 -50 -25 0 25 50 75 100 Temperature (°C) Sample Rate (kHz) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 9 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 75 kHz, fCLK = 16 × fSAMPLE (unless otherwise noted) POWER-SUPPLY REJECTION vs RIPPLE FREQUENCY 0 -10 -20 POWER-SUPPLY REJECTION vs RIPPLE FREQUENCY 0 VCC = 2.7V Ripple = 500mVPP VIN = 1.25VDC VREF = 2.5V -10 -20 -30 PSR (dB) PSR (dB) -30 VCC = 5V Ripple = 500mVPP VIN = 2.5VDC VREF = 5V -40 -50 -60 -40 -50 -60 -70 -70 PSR (dB) = 20log(500mV/DVO) where DVO = change in digital result -80 -90 1k 10k 100k 1M PSR (dB) = 20log(500mV/DVO) where DVO = change in digital result -80 -90 10M 10 1 1k 10k 100k Ripple Frequency (Hz) Ripple Frequency (Hz) Figure 19. Figure 20. 1M 10M CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE Delta from +2.5V Reference (LSB) 0.20 VCC = 5V 0.15 Change in Integral Linearity (LSB) 0.10 0.05 0.00 Change in Differential Linearity (LSB) -0.05 -0.10 1 2 3 4 5 Reference Voltage (V) Figure 21. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 THEORY OF OPERATION The ADS7822 is a classic successive approximation register (SAR) A/D converter. The architecture is based on capacitive redistribution that inherently includes a sample/hold function. The converter is fabricated on a 0.6µ CMOS process. The architecture and process allow the ADS7822 to acquire and convert an analog signal at up to 200,000 conversions per second while consuming very little power. The ADS7822 requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 50 mV and VCC. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS7822. The external clock can vary between 10 kHz (625 Hz throughput) and 3.2 MHz (200 kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 400 ns for a supply range between 2.7 V to 3.6 V, or 125 ns for a supply range between 4.75 V to 5.25 V. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS7822. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS7822 after the conversion is complete and to obtain the serial data least significant bit first. See the Digital Interface section for more information. ANALOG INPUT The +In and –In input pins allow for a pseudo-differential input signal. Unlike some converters of this type, the –In input is not resampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and –In is captured on the internal capacitor array. The range of the –In input is limited to –0.2 V to 1 V. Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the –In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS7822 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pF) to a 12-bit settling level within 1.5 clock cycles. When the converter goes into the hold mode or while it is in the power-down mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –In input should not drop below GND – 200 mV or exceed GND + 1 V. The +In input should always remain within the range of GND – 200 mV to VCC + 200 mV. Outside of these ranges, the converter linearity may not meet specifications. REFERENCE INPUT The external reference sets the analog input range. The ADS7822 operates with a reference in the range of 50 mV to VCC. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5-V reference, the internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output code. When the external reference is 50 mV, the potential error contribution from the internal noise will be 50 times larger—16 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 11 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com For more information regarding noise, consult the typical characteristic curves Effective Number of Bits vs Reference Voltage and Peak-to-Peak Noise vs Reference Voltage. Note that the effective number of bits (ENOB) figure is calculated based on the converter signal-to-(noise + distortion) ratio with a 1-kHz 0-dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 × ENOB + 1.76 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. DIGITAL INTERFACE Signal Levels The digital inputs of the ADS7822 can accommodate logic levels up to 6 V regardless of the value of VCC. Thus, the ADS7822 can be powered at 3V and still accept inputs from logic powered at 5 V. The CMOS digital output (DOUT) will swing 0 V to VCC. If VCC is 3 V and this output is connected to a 5-V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay. Serial Interface The ADS7822 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as shown in Figure 22 and Table 1. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. tCYC CS/SHDN Power Down tSUCS DCLOCK tCSD DOUT Hi-Z Null Bit B11 B10 B9 B8 (MSB) tSMPL B7 B6 B5 B4 B3 B2 B1 B0 tCONV Null Bit Hi-Z (1) B11 B10 B9 B8 tDATA Note: (1) After completing the data transfer, if further clocks are applied with CS LOW, the A/D will output LSB-First data then followed with zeroes indefinitely. tCYC CS/SHDN tSUCS Power Down DCLOCK tCSD DOUT Hi-Z tSMPL Null Bit Hi-Z B11 B10 B9 (MSB) B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 tCONV B4 B5 B6 B7 B8 B9 B10 B11 (1) tDATA Note: (1) After completing the data transfer, if further clocks are applied with CS LOW, the A/D will output zeroes indefinitely. tDATA: During this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out LSB-first data or zeroes. Figure 22. Basic Timing Diagrams 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 Table 1. Timing Specifications (–40°C to 85°C) SYMBOL tSMPL (1) Analog input sample time tCONV Conversion time tCYC (1) Cycle time tCSD (1) CS falling to DCLOCK low tSUCS (1) VCC = 2.7 V DESCRIPTION MIN TYP 1.5 MIN 2.0 1.5 TYP Clk Cycles 2.0 Clk Cycles Clk Cycles 16 0 CS falling to DCLOCK rising UNITS MAX 12 16 0.03 1000 DCLOCK falling to current DOUT not valid tdDO (1) DCLOCK falling to next DOUT valid 130 tdis MAX 12 thDO (1) (1) VCC = 5 V 0.03 15 0 ns 1000 µs 15 ns 200 85 150 ns CS rising to DOUT high impedance 40 80 25 50 ns ten (1) DCLOCK falling to DOUT enabled 75 175 50 100 ns tf (1) DOUT fall time 90 200 70 100 ns DOUT rise time 110 200 60 100 ns tr (1) (1) Not production tested 1.4V 3kW DOUT VOH DOUT VOL Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VIL VCC DOUT tdDO VOH DOUT tdis Waveform 2, ten 3kW tdis Waveform 1 100pF CLOAD VOL thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO VIH CS/SHDN DOUT Waveform 1(1) CS/SHDN 90% DCLOCK 1 2 tdis DOUT Waveform 2(2) 10% VOL DOUT B11 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Figure 23. Timing Diagrams and Test Circuits for the Parameters in Table 1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 13 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com A falling CS signal initiates the conversion and data transfer. The first 1.5 to 2.0 clock periods of the conversion cycle are used to sample the input signal. After the second falling DCLOCK edge, DOUT is enabled and outputs a low value for one clock period. For the next 12 DCLOCK periods, DOUT outputs the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks repeat the output data, but in a least significant bit first format. After the most significant bit (B11) has been repeated, DOUT becomes high impedance. Subsequent clocks have no effect on the converter. A new conversion is initiated only when CS is taken high and returned low. 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 Data Format The output data from the ADS7822 is in straight binary format, as shown in Table 2. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. Table 2. Ideal Input Voltages and Output Codes DESCRIPTION DIGITAL OUTPUT STRAIGHT BINARY ANALOG VALUE Full-scale range VREF Least significant bit (LSB) VREF/4096 BINARY CODE HEX CODE Full-scale VREF – 1 LSB 1111 1111 1111 FFF Midscale VREF/2 1000 0000 0000 800 VREF/2 – 1 LSB 0111 1111 1111 7FF 0V 0000 0000 0000 000 Midscale – 1 LSB Zero POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS7822 to convert at up to a 75-kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS7822 scales directly with conversion rate. So, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS7822 goes into power-down mode under two conditions: when the conversion is complete and whenever CS is high (see Figure 22). Ideally, each conversion should occur as quickly as possible; preferably, at a 1.2MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important since the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power-down mode is entered. Figure 24 shows the current consumption of the ADS7822 versus sample rate. For this graph, the converter is clocked at 1.2 MHz regardless of the sample rate—CS is high for the remaining sample period. Figure 25 also shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/16th of the sample period—CS is high for one DCLOCK cycle out of every 16. 1000 Supply Current (mA) TA = 25°C fCLK = 1.2MHz 100 VCC = 5.0V VREF = 5.0V VCC = 2.7V VREF = 2.5V 10 1 0.1 1 10 100 Sample Rate (kHz) Figure 24. Maintaining fCLK at the Highest Possible Rate Allows the Supply Current to Drop Linearly with the Sample Rate Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 15 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com Supply Current (mA) 1000 100 10 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 16 · fSAMPLE 1 0.1 1 10 100 Sample Rate (kHz) Figure 25. Scaling fCLK Reduces the Supply Current Only Slightly with the Sample Rate There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is high. While both shut down the analog section, the digital section is completely shutdown only when CS is high. Thus, if CS is left low at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is high; see Figure 26 for more information. 10.0 Supply Current (mA) 8.0 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 16 · fSAMPLE 6.0 CS LOW (GND) 4.0 2.0 0.0 CS HIGH (VCC) 0.050 0.00 0.1 1 10 100 Sample Rate (kHz) Figure 26. Shutdown Current with CS High is Typically 50nA, Regardless of the Clock. Shutdown Current with CS Low varies with Sample Rate. Power dissipation can also be reduced by lowering the power-supply voltage and the reference voltage. The ADS7822 operates over a VCC range of 2.0 V to 5.25 V. It will run up to a 200-kHz throughput rate over a supply range of 4.75 V to 5.25 V; therefore, it can be clocked at up to 3.2 MHz. However, at voltages below 2.7 V, the converter does not run at a 75-kHz sample rate. See the Typical Characteristic curves for more information regarding power-supply voltage and maximum sample rate. Short Cycling Another way of saving power is to use the CS signal to short-cycle the conversion. Because the ADS7822 places the latest data bit on the DOUT line as it is generated, the converter can easily be short-cycled. This term means that the conversion can be terminated at any time. For example, if only eight bits of the conversion result are needed, then the conversion can be terminated (by pulling CS high) after the eighth bit has been clocked out. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 12-bit conversion result may not be needed. If so, the conversion can be terminated after the first n-bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system, because they spend more time in the power-down mode. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 ADS7822-Q1 www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7822 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 75 kHz conversion rate, the ADS7822 makes a bit decision every 830ns. If the supply range is limited to 4.75 V to 5.25 V, then up to a 200-kHz conversion rate can be used, which reduces the bit decision time to 312 ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 12-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter DCLOCK signal because the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS7822 should be clean and well-bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the ADS7822 package as possible. In addition, a 1-µF to 10-µF capacitor and a 5-Ω or 10-Ω series resistor can be used to lowpass filter a noisy supply. The reference should be similarly bypassed with a 0.1-µF capacitor. Again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. If the reference voltage originates from an op amp, be careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS7822 draws very little current from the reference on average, there are still instantaneous current demands placed on the external reference circuitry. Also, keep in mind that the ADS7822 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz), can be difficult to remove. The GND pin on the ADS7822 should be placed on a clean ground point. In many cases, this will be the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. APPLICATION CIRCUITS Figure 27 and Figure 28 show some typical application circuits for the ADS7822. Figure 27 uses an ADS7822 and a multiplexer to provide for a flexible data acquisition circuit. A resistor string provides for various voltages at the multiplexer input. The selected voltage is buffered and driven into VREF. As shown in Figure 27, the input range of the ADS7822 is programmable to 100 mV, 200 mV, 300 mV, or 400 mV. The 100-mV range would be useful for sensors such as the thermocouple shown. Figure 28 shows a basic data acquisition system. The ADS7822 input range is 0 V to VCC, as the reference input is connected directly to the power supply. The 5-Ω resistor and 1-µF to 10-µF capacitor filter the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 17 ADS7822-Q1 SGLS299 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com +3V +3V +3V R8 26kW D1 R1 150kW R9 1kW OPA237 C2 0.1mF R3 500kW R6 1MW R2 59kW TC1 0.4V R7 5W 0.3V U2 C1 10mF VREF Mux 0.2V DCLOCK C3 0.1mF TC2 ADS7822 DOUT A0 CS/SHDN A1 Thermocouple TC3 R4 1kW C4 10mF ISO Thermal Block R10 1kW U1 R5 500W U3 C5 0.1mF R11 1kW 0.1V R12 1kW P 3-Wire Interface U4 Figure 27. Thermocouple Application Using a Mux to Scale the Input Range of the ADS7822 +2.7V to +3.6V 5W + 1mF to 10mF ADS7822 VREF VCC +In CS -In DOUT 0.1mF GND + 1mF to 10mF Microcontroller DCLOCK Figure 28. Basic Data Acquisition System 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS7822-Q1 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device ADS7822IDGKRQ1 Status (1) Package Type Package Drawing ACTIVE VSSOP DGK Pins Package Qty 8 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF ADS7822-Q1 : • Catalog: ADS7822 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7822IDGKRQ1 Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7822IDGKRQ1 VSSOP DGK 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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